2 W, Filterless, Class-D Stereo Audio Amplifier SSM2306 The SSM2306 features ultralow idle current, high efficiency, and a low noise modulation scheme. It operates with >87% efficiency at 1.4 W into 8 Ω from a 5.0 V supply and has a signal-to-noise ratio (SNR) that is better than 96 dB. PDM modulation offers lower EMI radiated emissions compared to other Class-D architectures. FEATURES Filterless Class-D amplifier with built-in output stage 2 W into 4 Ω and 1.4 W into 8 Ω at 5.0 V supply Ultralow idle current with load resistance >87% efficiency at 5.0 V, 1.4 W into 8 Ω speaker Better than 96 dB SNR (signal-to-noise ratio) Available in 16-lead, 3 mm × 3 mm LFCSP Single-supply operation from 2.5 V to 5.0 V 20 nA ultralow shutdown current Short-circuit and thermal protection Pop-and-click suppression Built-in resistors reduce board component count Default fixed 18 dB gain and user-adjustable The SSM2306 has a micropower shutdown mode with a typical shutdown current of 20 nA. Shutdown is enabled by applying a logic low to the SD pin. The architecture of the device allows it to achieve a very low level of pop and click to minimize voltage glitches at the output during turn-on and turn-off, thereby reducing audible noise on activation and deactivation. The fully differential input of the SSM2306 provides excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. APPLICATIONS Mobile phones MP3 players Portable gaming Portable electronics Educational toys Notebook computers The SSM2306 also has excellent rejection of power supply noise, including noise caused by GSM transmission bursts and RF rectification. The SSM2306 has a preset gain of 18 dB that can be reduced by using external resistors. GENERAL DESCRIPTION The SSM2306 is a fully integrated, high efficiency, Class-D stereo audio amplifier designed to maximize performance for portable applications. The application circuit requires minimum external components and operates from a single 2.5 V to 5.0 V supply. It is capable of delivering 2 W of continuous output power with less than 10% THD + N driving a 4 Ω load from a 5.0 V supply. The SSM2306 is specified over the commercial temperature range (−40°C to +85°C). It has built-in thermal shutdown and output short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm lead frame chip scale package (LFCSP). FUNCTIONAL BLOCK DIAGRAM VBATT 2.5V TO 5.0V 10µF 0.1µF 22nF1 RIGHT IN+ SSM2306 REXT 344kΩ 22nF1 REXT VDD OUTR+ INR+ RIGHT IN– VDD 43kΩ INR– MODULATOR FET DRIVER OUTR– 43kΩ 344kΩ SHUTDOWN BIAS SD INTERNAL OSCILLATOR 344kΩ LEFT IN+ REXT 43kΩ OUTL+ INL+ LEFT IN– 22nF1 REXT INL– GAIN = 344kΩ/(43kΩ + REXT ) MODULATOR FET DRIVER OUTL– 43kΩ 344kΩ 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. GND GND 06542-001 22nF1 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. SSM2306 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Application Circuits ......................................................... 11 Applications....................................................................................... 1 Application Notes ........................................................................... 12 General Description ......................................................................... 1 Overview ..................................................................................... 12 Functional Block Diagram .............................................................. 1 Gain Selection............................................................................. 12 Revision History ............................................................................... 2 Pop-and-Click Suppression ...................................................... 12 Specifications..................................................................................... 3 EMI Noise.................................................................................... 12 Absolute Maximum Ratings............................................................ 4 Layout .......................................................................................... 13 Thermal Resistance ...................................................................... 4 Input Capacitor Selection.......................................................... 13 ESD Caution.................................................................................. 4 Proper Power Supply Decoupling ............................................ 13 Pin Configuration and Function Descriptions............................. 5 Outline Dimensions ....................................................................... 14 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 4/07—Revision 0: Initial Version Rev. 0 | Page 2 of 16 SSM2306 SPECIFICATIONS VDD = 5.0 V; TA = 25oC; RL = 4 Ω, 8 Ω; gain = 6 dB, unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol Conditions PO RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT = 2 W, 4 Ω, VDD = 5.0 V POUT = 1.4 W, 8 Ω, VDD = 5.0 V PO = 2 W into 4 Ω each channel, f = 1 kHz, VDD = 5.0 V PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V Efficiency η Total Harmonic Distortion + Noise THD + N Input Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRRGSM Channel Separation Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio XTALK fSW VOOS Typ Max 1.8 1.4 0.9 0.615 0.35 0.275 2.4 1.53 1.1 0.77 0.45 0.35 75 85 0.4 0.02 70 W W W W W W W W W W W W % % % % V dB 78 420 2.0 dB kHz mV 1.0 VCM = 2.5 V ± 100 mV at 217 Hz, G = 18 dB, input referred PO = 100 mW , f = 1 kHz VDD − 1 Supply Current ISY Shutdown Current ISD GAIN Closed-Loop Gain Differential Input Impedance Av ZIN REXT = 0 SD = VDD 18 43 dB kΩ SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance VIH VIL tWU tSD OUT ISY ≥ 1 mA ISY ≤ 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND 1.2 0.5 30 5 >100 V V ms μs kΩ NOISE PERFORMANCE Output Voltage Noise en VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac-grounded, AV = 18 dB, RL = 4 Ω, A weighting POUT = 2.0 W, RL = 4 Ω 44 μV 96 dB SNR Rev. 0 | Page 3 of 16 2.5 70 Unit Guaranteed from PSRR test VDD = 2.5 V to 5.0 V VRIPPLE = 100 mV rms at 217 Hz, inputs ac GND, CIN = 0.1 μF, input referred VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V SD = GND Signal-to-Noise Ratio VDD PSRR PSRRGSM Min 85 75 5.0 V dB dB 6.5 5.7 5.1 20 mA mA mA nA SSM2306 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. THERMAL RESISTANCE Table 2. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 6V VDD VDD 4 kV −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Table 3. Thermal Resistance Package Type 16-Lead, 3 mm × 3 mm LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 16 θJA 44 θJC 31.5 Unit °C/W SSM2306 12 OUTR+ 11 OUTR– 10 NC 14 VDD NC = NO CONNECT 06542-002 9 INR+ INR– 8 NC 7 TOP VIEW (Not to Scale) INL– 5 INL+ 4 SSM2306 NC 6 SD 3 13 GND PIN 1 INDICATOR OUTL+ 1 OUTL– 2 15 VDD 16 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic OUTL+ OUTL− SD INL+ INL− NC NC INR− INR+ NC OUTR− OUTR+ GND VDD VDD GND Description Inverting Output for Left Channel. Noninverting Output for Left Channel. Shutdown Input. Active low digital input. Noninverting Input for Left Channel. Inverting Input for Left Channel. No Connect. No Connect. Inverting Input for Right Channel. Noninverting Input for Right Channel. No Connect. Noninverting Output for Right Channel. Inverting Output for Right Channel. Ground for Output Amplifiers. Power Supply for Output Amplifiers. Power Supply for Output Amplifiers. Ground for Output Amplifiers. Rev. 0 | Page 5 of 16 SSM2306 TYPICAL PERFORMANCE CHARACTERISTICS 100 THD + N (%) VDD = 3.6V 0.1 0.001 0.0001 0.001 0.01 0.1 1 1 VDD = 3.6V 0.1 VDD = 5V VDD = 5V 0.01 10 OUTPUT POWER (W) 0.001 0.0001 06542-003 THD + N (%) 1 0.01 0.01 0.1 1 10 100k Figure 6. THD + N vs. Output Power into 8 Ω, AV = 6 dB 100 RL = 8Ω, 33µH AV = 18dB VDD = 2.5V 10 0.001 OUTPUT POWER (W) Figure 3. THD + N vs. Output Power into 4 Ω, AV = 18 dB VDD = 5V RL = 8Ω, 33µH AV = 18dB 10 1 THD + N (%) THD + N (%) VDD = 2.5V 10 10 100 RL = 8Ω, 33µH AV = 6dB VDD = 2.5V 06542-006 RL = 4Ω, 33µH AV = 18dB 06542-007 100 VDD = 3.6V 0.1 1 0.1 1W 0.25W 0.01 0.01 VDD = 5V 0.5W 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 10 06542-004 0.001 0.0001 VDD = 2.5V 10 VDD = 5V AV = 18dB RL = 4Ω, 33µH 1 THD + N (%) 10 VDD = 3.6V VDD = 5V 0.1 2W 1 0.1 1W 0.5W 0.01 0.001 0.0001 0.001 0.01 0.1 1 OUTPUT POWER (W) 10 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, AV = 18 dB Figure 5. THD + N vs. Output Power into 4 Ω, AV = 6 dB Rev. 0 | Page 6 of 16 06542-008 0.01 06542-005 THD + N (%) 10k Figure 7. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, AV = 18 dB 100 RL = 4Ω, 33µH AV = 6dB 1k FREQUENCY (Hz) Figure 4. THD + N vs. Output Power into 8 Ω, AV = 18 dB 100 100 SSM2306 100 VDD = 3.6V AV = 18dB RL = 8Ω, 33µH 10 10 1 1 THD + N (%) 0.1 VDD = 2.5V AV = 18dB RL = 4Ω, 33µH 0.5W 0.1 0.25W 0.5W 0.125W 0.01 0.01 0.125W 100 1k 10k 100k FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, AV = 18 dB Figure 9. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, AV = 18 dB 100 0.25W 0.001 10 06542-009 0.001 10 06542-012 THD + N (%) 100 7.5 VDD = 3.6V AV = 18dB RL = 4Ω, 33µH ISY FOR BOTH CHANNELS 7.0 SUPPLY CURRENT (mA) THD + N (%) 10 1W 1 0.1 0.5W 0.25W 0.01 RL = 8Ω, 33µH 6.5 RL = 4Ω, 33µH 6.0 NO LOAD 5.5 5.0 1k 10k 100k FREQUENCY (Hz) 4.0 2.5 4.5 5.0 5.5 0.8 12 10 SUPPLY CURRENT (µA) 10 THD + N (%) 4.0 Figure 13. Supply Current vs. Supply Voltage, No Load VDD = 2.5V AV = 18dB RL = 8Ω, 33µH 1 0.1 0.25W 0.125W 0.075W 8 VDD = 5V 6 VDD = 3.6V 4 VDD = 2.5V 2 100 1k 10k 100k FREQUENCY (Hz) 06542-011 0.01 0.001 10 3.5 SUPPLY VOLTAGE (V) Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, AV = 18 dB 100 3.0 06542-013 100 06542-010 0.001 10 06542-014 4.5 Figure 11. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, AV = 18 dB 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 SHUTDOWN VOLTAGE (V) Figure 14. Supply Current vs. Shutdown Voltage Rev. 0 | Page 7 of 16 SSM2306 3.0 2.5 1.8 f = 1kHz AV = 18dB RL = 4Ω, 33µH f = 1kHz A = 6dB 1.6 RV = 8Ω, 33µH L OUTPUT POWER (W) OUTPUT POWER (W) 1.4 2.0 10% 1.5 1% 1.0 1.2 10% 1.0 1% 0.8 0.6 0.4 0.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 15. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 18 dB 3.0 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 18. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 6 dB 100 f = 1kHz AV = 6dB RL = 4Ω, 33µH RL = 4Ω, 33µH 90 80 70 2.0 EFFICIENCY (%) OUTPUT POWER (W) 2.5 0 2.5 06542-015 0 2.5 06542-018 0.2 10% 1.5 1% 1.0 60 VDD = 5V VDD = 3.6V VDD = 2.5V 50 40 30 20 0.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0 06542-016 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Figure 19. Efficiency vs. Output Power into 4 Ω 100 1.8 f = 1kHz A = 18dB 1.6 RV = 8Ω, 33µH L RL = 8Ω, 33µH 90 80 1.4 70 1.2 1.0 EFFICIENCY (%) OUTPUT POWER (W) 0.4 OUTPUT POWER (W) Figure 16.Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 6 dB 10% 0.8 1% 0.6 VDD = 2.5V VDD = 5V VDD = 3.6V 60 50 40 30 0.4 20 0.2 10 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 06542-017 0 2.5 0.2 Figure 17. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 18 dB Rev. 0 | Page 8 of 16 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 OUTPUT POWER (W) Figure 20. Efficiency vs. Output Power into 8 Ω 1.8 06542-020 0 2.5 06542-019 10 SSM2306 2.2 1.4 VDD = 5V RL= 8Ω, 33µH FOR BOTH CHANNELS 1.8 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 VDD = 3.6V RL = 4Ω, 33µH FOR BOTH CHANNELS 2.0 1.0 0.8 0.6 0.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 OUTPUT POWER (W) 0 06542-021 0 OUTPUT POWER (W) Figure 24. Power Dissipation vs. Output Power at VDD = 3.6 V, RL = 4 Ω Figure 21. Power Dissipation vs. Output Power at VDD = 5 V, RL = 8 Ω 900 1.0 VDD = 3.6V RL = 8Ω, 33µH FOR BOTH CHANNELS 0.9 700 0.7 600 0.6 ISY (mA) 0.5 0.4 VDD = 3.6V 500 VDD = 2.5V 400 300 0.3 200 0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT POWER (W) 0 06542-022 0 0 2.4 1300 0.8 1.0 1.2 1.4 1.6 VDD = 5V RL = 4Ω, 33µH ISY IS FOR BOTH CHANNELS 1200 VDD = 3.6V 1100 2.2 1000 2.0 900 1.8 800 ISY (mA) 1.6 1.4 1.2 VDD = 2.5V 700 600 500 1.0 0.8 400 0.6 300 0.4 200 0.2 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 OUTPUT POWER (W) 06542-023 POWER DISSIPATION (W) 0.6 Figure 25. Supply Current vs. Output Power into 8 Ω VDD = 5V RL = 4Ω, 33µH FOR BOTH CHANNELS 2.6 0.4 PO (W) Figure 22. Power Dissipation vs. Output Power at VDD = 3.6 V, RL = 8 Ω 2.8 0.2 06542-025 100 0.1 0 VDD = 5V Figure 23. Power Dissipation vs. Output Power at VDD = 5 V, RL = 4 Ω 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 PO (W) Figure 26. Supply Current vs. Output Power into 4 Ω Rev. 0 | Page 9 of 16 2.2 06542-026 POWER DISSIPATION (W) RL = 8Ω, 33µH ISY IS FOR BOTH CHANNELS 800 0.8 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 06542-024 0.2 0 SSM2306 0 7 –10 6 –20 5 4 VOLTAGE (V) –40 –50 –60 SD INPUT 2 1 –70 OUTPUT 0 –80 100 1k 10k 100k FREQUENCY (Hz) –2 –10 06542-027 10 0 20 30 40 50 60 70 80 90 140 160 180 TIME (ms) Figure 27. PSRR vs. Frequency 0 10 06542-030 –1 –90 –100 3 06542-031 PSRR (dB) –30 Figure 30. Turn-On Response 7 RL = 8Ω, 33µH OUTPUT 6 –10 SD INPUT 5 –20 VOLTAGE (V) CMRR (dB) 4 –30 –40 –50 0 –70 10 100 1k 10k 100k 06542-028 –1 FREQUENCY (Hz) 0 VDD = 3.6V VRIPPLE = 1V rms –20 RL = 8Ω, 33µH –60 –80 –100 –120 100 1k 10k FREQUENCY (Hz) 100k 06542-029 CROSSTALK (dB) –40 10 –2 –20 0 20 40 60 80 100 120 TIME (ms) Figure 31. Turn-Off Response Figure 28. CMRR vs. Frequency –140 2 1 –60 –80 3 Figure 29. Crosstalk vs. Frequency Rev. 0 | Page 10 of 16 SSM2306 TYPICAL APPLICATION CIRCUITS 10µF 0.1µF SSM2306 22nF1 RIGHT IN+ REXT VDD 22nF1 OUTR+ SD 22nF1 REXT BIAS 22nF1 OUTR– INTERNAL OSCILLATOR OUTL+ INL+ FET DRIVER MODULATOR INL– LEFT IN– FET DRIVER MODULATOR REXT SHUTDOWN LEFT IN+ VDD INR+ INR– RIGHT IN– VBATT 2.5V TO 5.0V OUTL– REXT GND 06542-037 GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 32. Stereo Differential Input Configuration 10µF 0.1µF SSM2306 22nF RIGHT IN REXT VDD OUTR+ MODULATOR SD 22nF REXT BIAS OUTR– INTERNAL OSCILLATOR INL+ INL– OUTL+ MODULATOR FET DRIVER OUTL– REXT GND GND 06542-038 22nF FET DRIVER REXT SHUTDOWN LEFT IN VDD INR+ INR– 22nF VBATT 2.5V TO 5.0V Figure 33. Stereo Single-Ended Input Configuration Rev. 0 | Page 11 of 16 SSM2306 APPLICATION NOTES OVERVIEW EMI NOISE The SSM2306 stereo, Class-D, audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and, thus, reducing systems cost. The SSM2306 does not require an output filter; instead, it relies on the inherent inductance of the speaker coil and the natural filtering capacity of the speaker and human ear to fully recover the audio component of the square wave output. The SSM2306 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. Figure 34 shows SSM2306 EMI emission starting from 100 kHz to 30 MHz. Figure 35 shows SSM2306 EMI emission from 30 kHz to 2 GHz. These figures clearly depict the SSM2306 EMI behavior as being well below the FCC regulation values, starting from 100 kHz and passing beyond 1 GHz of frequency. Although the overall EMI noise floor is slightly higher, frequency spurs from the SSM2306 are greatly reduced. 70 60 40 30 20 GAIN SELECTION 10 100 10k FREQUENCY (MHz) Figure 34. EMI Emissions from SSM2306 70 60 External Gain Settings = 344 kΩ/(43 kΩ + REXT) POP-AND-CLICK SUPPRESSION 1 06542-039 0 0.1 06542-040 10 The SSM2306 has a pair of internal resistors that set an 18 dB default gain for the amplifier. It is possible to adjust the SSM2306 gain by using external resistors at the input. To set a gain lower than 18 dB, refer to Figure 32 for the differential input configuration and Figure 33 for the single-ended configuration. Calculate the external gain configuration as = HORIZONTAL = VERTICAL = REGULATION VALUE LEVEL (dB(µV/m)) 50 Voltage transients at the output of audio amplifiers can occur with the activation or deactivation of shutdown. Furthermore, voltage transients as low as 10 mV are audible as an audio pop in the speaker. Likewise, clicks and pops are classified as undesirable audible transients generated by the amplifier system, and as such, as not coming from the system input signal. These types of transients generate when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: • • • • = HORIZONTAL = VERTICAL = REGULATION VALUE 50 LEVEL (dB(µV/m)) Although most Class-D amplifiers use some variation of pulsewidth modulation (PWM), the SSM2306 uses sigma-delta (Σ-Δ) modulation to determine the switching pattern of the output devices. This provides a number of important benefits. Σ-Δ modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation provides the benefits of reducing the amplitude of spectral components at high frequencies; that is, reducing EMI emission that might otherwise radiate by the use of speakers and long cable traces. The SSM2306 also offers protection circuits for overcurrent and overtemperature protection. 40 30 20 10 0 10 100 1k FREQUENCY (MHz) Figure 35. EMI Emissions from SSM2306 System power-up/power-down Mute/unmute Input source change Sample rate change The SSM2306 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. The measurements for Figure 34 and Figure 35 were taken with a 1 kHz input signal, producing 0.5 W output power into an 8 Ω load from a 3.6 V supply. Cable length was approximately 5 cm. To detect EMI, a magnetic probe was used touching the 2-inch output trace to the load. Rev. 0 | Page 12 of 16 SSM2306 LAYOUT INPUT CAPACITOR SELECTION As output power continues to increase, careful layout is needed for proper placement of PCB traces and wires between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Make track widths at least 200 mil for every inch of track length for lowest DCR, and use 1 oz. or 2 oz. of copper PCB traces to further reduce IR drops and inductance. Poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. The SSM2306 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed (see Figure 32), or if using a single-ended source (see Figure 33). If high-pass filtering is needed at the input, the input capacitor together with the input resistor of the SSM2306 form a high-pass filter whose corner frequency is determined by the following equation: To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended to use a large area ground plane for minimum impedances. Good PCB layouts isolate critical analog paths from sources of high interference; furthermore, separate high frequency circuits (analog and digital) from low frequency ones. Properly designed multilayer printed circuit boards can reduce EMI emission and increase immunity to RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes or analog and digital power planes. fC = 1/(2π × RIN × CIN) Input capacitors can have very important effects on the circuit performance. Not using input capacitors degrades the output offset of the amplifier as well as the PSRR performance. PROPER POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality, low ESL and low ESR capacitor, usually around 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 μF capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2306 helps maintain efficiency performance. Rev. 0 | Page 13 of 16 SSM2306 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR TOP VIEW 13 12 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX 16 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 0.50 0.40 0.30 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model SSM2306CPZ-R2 1 SSM2306CPZ-REEL1 SSM2306CPZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Package Option CP-16-3 CP-16-3 CP-16-3 Branding A1R A1R A1R SSM2306 NOTES Rev. 0 | Page 15 of 16 SSM2306 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06542-0-4/07(0) Rev. 0 | Page 16 of 16