AD SSM2305CPZ

Filterless High Efficiency
Mono 2.8 W Class-D Audio Amplifier
SSM2305
The SSM2305 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modulation provides high efficiency even at low output power. The
SSM2305 operates with 90% efficiency at 1.3 W into 8 Ω or 83%
efficiency at 2.2 W into 4 Ω from a 5.0 V supply and has an SNR of
>98 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers
from Analog Devices, Inc.
2.8 W into 4 Ω load and 1.6 W into 8 Ω load at 5.0 V supply
with <10% total harmonic distortion (THD)
89% efficiency at 5.0 V, 1.3 W into 8 Ω speaker
>98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations
The SSM2305 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a Logic 0 to the SD pin. The device also includes pop-and-click
suppression circuitry. This minimizes voltage glitches at the
output during turn-on and turn-off, thus reducing audible noise
on activation and deactivation.
The fully differential input of the SSM2305 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2305 has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 60 dB at 217 Hz.
GENERAL DESCRIPTION
The SSM2305 is a fully integrated, high efficiency, Class-D
audio amplifier designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 2.2 W of continuous output
power with less than 1% THD + N driving a 4 Ω load from a
5.0 V supply. It has built-in thermal shutdown and output shortcircuit protection.
The default gain of the SSM2305 is 18 dB, but users can reduce the
gain by using a pair of external resistors.
The SSM2305 is specified over the commercial temperature range
(−40°C to +85°C). It is available in both an 8-lead, 3 mm ×
3 mm lead frame chip scale package (LFCSP) and an 8-lead
mini small outline package (MSOP).
FUNCTIONAL BLOCK DIAGRAM
0.1µF
10µF
SSM2305
47nF*
AUDIO IN+
IN+
IN–
AUDIO IN–
VBATT
2.5V TO 5.5V
VDD
160kΩ
20kΩ
OUT+
MODULATOR
(Σ-Δ)
20kΩ
FET
DRIVER
OUT–
47nF*
160kΩ
SHUTDOWN
SD
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
07243-001
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
SSM2305
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 11
Applications ....................................................................................... 1
Overview ..................................................................................... 11
General Description ......................................................................... 1
Gain .............................................................................................. 12
Functional Block Diagram .............................................................. 1
Pop-and-Click Suppression ...................................................... 12
Revision History ............................................................................... 2
Output Modulation Description .............................................. 12
Specifications..................................................................................... 3
Layout .......................................................................................... 12
Absolute Maximum Ratings............................................................ 4
Input Capacitor Selection .......................................................... 12
Thermal Resistance ...................................................................... 4
Proper Power Supply Decoupling ............................................ 13
ESD Caution .................................................................................. 4
Outline Dimensions ....................................................................... 14
Pin Configurations and Function Descriptions ........................... 5
Ordering Guide .......................................................................... 14
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
3/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
SSM2305
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.
Table 1.
Parameter
DEVICE CHARACTERISTICS
Output Power
Symbol
Conditions
PO
RL = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 5.0 V
RL = 8 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V
RL = 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 5.0 V
RL = 8 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V
RL = 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 5.0 V
RL = 4 Ω, THD = 1%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V
RL = 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 5.0 V
RL = 4 Ω, THD = 10%, f = 1 kHz, BW = 20 kHz, VDD = 3.6 V
PO = 1.3 W, 8 Ω, VDD = 5.0 V
PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V
PO = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V
Efficiency
Total Harmonic Distortion + Noise
η
THD + N
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
Supply Voltage Range
Power Supply Rejection Ratio
VCM
CMRRGSM
fSW
VOOS
Supply Current
VDD
PSRR
PSRRGSM
ISY
Shutdown Current
Min
Typ
Max
1.34
0.68
1.67
0.85
2.22
1.1
2.8
1.3
89
0.02
0.02
1.0
VCM = 2.5 V ± 100 mV at 217 Hz, output referred
VDD − 1
55
280
2.0
G = 18 dB
ISD
GAIN CONTROL
Closed-Loop Gain
Differential Input Impedance
Av
ZIN
SD = VDD
18
20
dB
kΩ
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Wake-Up Time
Shutdown Time
Output Impedance
VIH
VIL
tWU
tSD
ZOUT
ISY ≥ 1 mA
ISY ≤ 300 nA
SD rising edge from GND to VDD
SD falling edge from VDD to GND
SD = GND
1.2
0.5
30
5
>100
V
V
ms
μs
kΩ
NOISE PERFORMANCE
Output Voltage Noise
en
VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
AV = 18 dB, A weighting
PO = 1.4 W, RL = 8 Ω
40
μV
98
dB
SNR
Rev. 0 | Page 3 of 16
5.5
W
W
W
W
W
W
W
W
%
%
%
V
dB
kHz
mV
Guaranteed from PSRR test
VDD = 2.5 V to 5.0 V, dc input floating
VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.1 μF
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
VIN = 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V
SD = GND
Signal-to-Noise Ratio
2.5
70
Unit
85
60
3.2
3.3
2.8
2.9
2.4
2.4
20
V
dB
dB
mA
mA
mA
mA
mA
mA
nA
SSM2305
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Absolute maximum ratings apply at TA = 25°C, unless otherwise noted.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2.
Parameter
Supply Voltage
Input Voltage
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
6V
VDD
VDD
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Table 3.
Package Type
8-Lead, 3 mm × 3 mm LFCSP
8-Lead MSOP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
θJA
62
210
θJC
20.8
45
Unit
°C/W
°C/W
SSM2305
SD 1
SD 1
PIN 1
INDICATOR
NC 2
SSM2305
7 GND
TOP VIEW
(Not to Scale)
5 OUT+
IN– 4
NC 2
IN+ 3
6 VDD
8
SSM2305
OUT–
7
TOP VIEW
(Not to Scale)
GND
6
VDD
5
OUT+
IN– 4
07243-002
IN+ 3
8 OUT–
07243-103
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
NC = NO CONNECT
Figure 3. MSOP Pin Configuration
Figure 2. LFSCP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
SD
NC
IN+
IN−
OUT+
VDD
GND
OUT−
Description
Shutdown Input. Active low digital input.
No Connect. This pin has no function, tie it to GND.
Noninverting Input.
Inverting Input.
Noninverting Output.
Power Supply.
Ground.
Inverting Output.
Rev. 0 | Page 5 of 16
SSM2305
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
RL = 4Ω + 33µH
GAIN = 18dB
THD + N (%)
VDD = 3.6V
0.1
0.01
0.1
OUTPUT POWER (W)
1
0.1
VDD = 5V
10
0.001
0.0001
07243-004
0.001
VDD = 3.6V
0.01
VDD = 5V
0.01
0.0001
1
Figure 4. THD + N vs. Output Power into 4 Ω + 33 μH, AV = 18 dB
0.001
1
0.01
0.1
OUTPUT POWER (W)
10
07243-007
1
VDD = 2.5V
10
VDD = 2.5V
10
THD + N (%)
RL = 8Ω + 33µH
GAIN = 6dB
Figure 7. THD + N vs. Output Power into 8 Ω + 33 μH, AV = 6 dB
100
100
RL = 4Ω + 33µH
GAIN = 6dB
10
10
VDD = 5V
GAIN = 18dB
RL = 4Ω + 33µH
VDD = 2.5V
0.01
0.001
0.01
0.1
OUTPUT POWER (W)
1
1W
0.1
0.01
VDD = 5V
0.001
0.0001
1
10
0.001
10
Figure 5. THD + N vs. Output Power into 4 Ω + 33 μH, AV = 6 dB
0.5W
100
1000
FREQUENCY (Hz)
10000
100000
07243-008
THD + N (%)
0.1
07243-005
THD + N (%)
2W
VDD = 3.6V
1
Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω + 33 μH, AV = 18 dB
100
100
RL = 8Ω + 33µH
GAIN = 18dB
10
VDD = 2.5V
10
VDD = 5V
GAIN = 18dB
RL = 8Ω + 33µH
THD + N (%)
THD + N (%)
VDD = 3.6V
1
0.1
1
0.1
0.5W
0.01
1W
0.01
VDD = 5V
0.01
0.1
OUTPUT POWER (W)
1
10
Figure 6. THD + N vs. Output Power into 8 Ω + 33 μH, AV = 18 dB
07243-006
0.001
0.001
10
100
1000
FREQUENCY (Hz)
10000
100000
07243-009
0.25W
0.001
0.0001
Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω + 33 μH, AV = 18 dB
Rev. 0 | Page 6 of 16
SSM2305
100
10
VDD = 3.6V
GAIN = 18dB
RL = 4Ω + 33µH
10
1
1W
1
0.1
THD + N (%)
THD + N (%)
100
0.5W
0.25W
0.1
0.01
0.01
VDD = 2.5V
GAIN = 18dB
RL = 8Ω + 33µH
0.25W
0.075W
100
1000
FREQUENCY (Hz)
10000
100000
0.001
10
07243-010
Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω + 33 μH, AV = 18 dB
SUPPLY CURRENT (mA)
THD + N (%)
3.4
0.5W
0.25W
3.2
RL = 4Ω + 33µH
3.0
RL = 8Ω + 33µH
2.8
NO LOAD
2.6
2.4
0.01
0.25W
1000
FREQUENCY (Hz)
10000
100000
2.0
2.5
07243-011
100
2.2
3.5
4.0
4.5
5.0
5.5
6.0
Figure 14. Supply Current vs. Supply Voltage
100
12
VDD = 2.5V
GAIN = 18dB
RL = 4Ω + 33µH
SHUTDOWN CURRENT (µA)
10
0.5W
1
0.25W
0.01
0.125W
100
1000
FREQUENCY (Hz)
8
VDD = 5V
6
VDD = 3.6V
4
VDD = 2.5V
2
10000
100000
0
07243-015
0.1
07243-012
THD + N (%)
3.0
SUPPLY VOLTAGE (V)
Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω + 33 μH, AV = 18 dB
0.001
10
100000
3.6
0.1
10
10000
3.8
VDD = 3.6V
GAIN = 18dB
RL = 8Ω + 33µH
1
0.001
10
1000
FREQUENCY (Hz)
Figure 13. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω + 33 μH, AV = 18 dB
100
10
100
07243-014
0.001
10
07243-013
0.125W
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SHUTDOWN VOLTAGE (V)
Figure 12. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω + 33 μH, AV = 18 dB
Rev. 0 | Page 7 of 16
Figure 15. Shutdown Current vs. Shutdown Voltage
0.8
SSM2305
3.0
f = 1kHz
GAIN = 18dB
RL = 4Ω + 33µH
f = 1kHz
GAIN = 6dB
RL = 8Ω + 33µH
1.6
1.4
OUTPUT POWER (W)
OUTPUT POWER (W)
2.5
1.8
2.0
10%
1.5
1%
1.0
1.2
1.0
10%
0.8
1%
0.6
0.4
0.5
3.0
3.5
4.0
4.5
07243-019
07243-016
0
2.5
0.2
0
2.5
5.0
3.0
3.5
VDD = 5V
80
VDD = 3.6V
70
EFFICIENCY (%)
10%
1.5
1%
1.0
VDD = 2.5V
60
50
40
30
20
07243-017
0.5
3.0
3.5
4.0
4.5
07243-020
OUTPUT POWER (W)
RL = 4Ω + 33µH
GAIN = 18dB
90
f = 1kHz
GAIN = 6dB
RL = 4Ω + 33µH
2.0
10
0
5.0
0
0.2
0.4
0.6
Figure 17. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, AV = 6 dB
100
1.4
1.6
1.8
2.0
VDD = 3.6V
VDD = 2.5V
70
EFFICIENCY (%)
10%
0.8
1%
0.6
60
50
40
20
0.2
10
3.0
3.5
4.0
4.5
0
5.0
07243-021
30
0.4
07243-018
OUTPUT POWER (W)
80
1.2
0
2.5
1.2
VDD = 5V
RL = 8Ω + 33µH
GAIN = 18dB
90
f = 1kHz
GAIN = 18dB
RL = 8Ω + 33µH
1.0
1.0
Figure 20. Efficiency vs. Output Power into 4 Ω + 33 μH
1.8
1.4
0.8
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
1.6
5.0
100
3.0
0
2.5
4.5
Figure 19. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, AV = 6 dB
Figure 16. Maximum Output Power vs. Supply Voltage,
RL = 4 Ω + 33 μH, AV = 18 dB
2.5
4.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
Figure 21. Efficiency vs. Output Power into 8 Ω + 33 μH
Figure 18. Maximum Output Power vs. Supply Voltage,
RL = 8 Ω + 33 μH, AV = 18 dB
Rev. 0 | Page 8 of 16
SSM2305
0.6
0.14
VDD = 5.0V
RL = 4Ω + 33µH
0.3
0.2
0.1
0.5
1.0
1.5
2.0
2.5
0.08
0.06
0.04
0.02
07243-022
0
0.10
0
3.0
07243-025
0.4
0
VDD = 3.6V
RL = 8Ω + 33µH
0.12
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.5
0
0.1
0.2
0.3
OUTPUT POWER (W)
0.5
0.6
0.7
0.8
0.9
1.0
Figure 25. Power Dissipation vs. Output Power into 8 Ω + 33 μH
at VDD = 3.6 V
Figure 22. Power Dissipation vs. Output Power into 4 Ω + 33 μH
at VDD = 5.0 V
800
0.20
RL = 4Ω + 33µH
0.18
VDD = 5V
700
VDD = 5.0V
RL = 8Ω + 33µH
SUPPLY CURRENT (mA)
0.16
POWER DISSIPATION (W)
0.4
OUTPUT POWER (W)
0.14
0.12
0.10
0.08
0.06
600
VDD = 3.6V
500
400
VDD = 2.5V
300
200
0.04
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
1.8
07243-026
0
100
07243-023
0.02
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 26. Supply Current vs. Output Power into 4 Ω + 33 μH
Figure 23. Power Dissipation vs. Output Power into 8 Ω + 33 μH
at VDD = 5.0 V
0.40
450
VDD = 3.6V
RL = 8Ω + 33µH
VDD = 5V
350
SUPPLY CURRENT (mA)
0.30
0.25
0.20
0.15
0.10
VDD = 3.6V
300
250
VDD = 2.5V
200
150
100
50
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
1.6
OUTPUT POWER (W)
07243-027
0.05
0
RL = 8Ω + 33µH
400
07243-024
POWER DISSIPATION (W)
0.35
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
OUTPUT POWER (W)
Figure 24. Power Dissipation vs. Output Power into 4 Ω + 33 μH
at VDD = 3.6 V
Figure 27. Supply Current vs. Output Power into 8 Ω + 33 μH
Rev. 0 | Page 9 of 16
1.8
8
–10
7
–20
6
–30
5
–40
–50
–60
3
2
1
–80
0
–90
–1
100
1000
FREQUENCY (Hz)
10000
100000
–2
–10
0
10
20
30
40
50
60
70
80
90
TIME (ms)
Figure 28. Power Supply Rejection Ratio vs. Frequency
Figure 30. Turn-On Response
8
–10
7
–20
6
–30
5
VOLTAGE (V)
0
–40
–50
–60
–70
OUTPUT
4
3
2
–80
0
–90
–1
–100
10
100
1000
FREQUENCY (Hz)
10000
100000
Figure 29. Common-Mode Rejection Ratio vs. Frequency
SD INPUT
–2
–500 –400 –300 –200 –100
0
100
200
TIME (µs)
Figure 31. Turn-Off Response
Rev. 0 | Page 10 of 16
300
400
07243-031
1
07243-029
CMRR (dB)
SD INPUT
4
–70
–100
10
OUTPUT
07243-030
VOLTAGE (V)
0
07243-028
PSSR (dB)
SSM2305
500
SSM2305
APPLICATIONS INFORMATION
a number of important benefits. Σ-Δ modulators do not produce
a sharp peak with many harmonics in the AM frequency band, as
pulse-width modulators often do. Σ-Δ modulation provides the
benefits of reducing the amplitude of spectral components at high
frequencies, that is, reducing EMI emission that might otherwise
be radiated by speakers and long cable traces. Due to the inherent
spread spectrum nature of Σ-Δ modulation, the need for oscillator synchronization is eliminated for designs incorporating
multiple SSM2305 amplifiers.
OVERVIEW
The SSM2305 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count that, in turn, conserves board space thereby reducing
systems cost. The SSM2305 does not require an output filter,
relying instead on the inherent inductance of the speaker coil
and the natural filtering of the speaker and human ear to
recover fully the audio component of the square wave output.
Most Class-D amplifiers use some variation of pulse-width
modulation (PWM), but the SSM2305 uses Σ-Δ modulation to
determine the switching pattern of the output devices resulting in
The SSM2305 also offers protection circuits for overcurrent and
temperature protection.
EXTERNAL GAIN SETTINGS = 160kΩ/(20kΩ + REXT )
0.1µF
10µF
SSM2305
AUDIO IN+
47nF* R
EXT
REXT
AUDIO IN–
IN+
IN–
VBATT
2.5V TO 5.5V
VDD
160kΩ
20kΩ
20kΩ
OUT+
MODULATOR
(Σ-Δ)
FET
DRIVER
OUT–
47nF*
160kΩ
SD
SHUTDOWN
INTERNAL
OSCILLATOR
BIAS
POP/CLICK
SUPPRESSION
07243-032
GND
*INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
Figure 32. Differential Input Configuration, User-Adjustable Gain
EXTERNAL GAIN SETTINGS = 160kΩ/(20kΩ + REXT )
0.1µF
10µF
SSM2305
AUDIO IN+
47nF R
EXT
IN+
20kΩ
REXT
IN–
20kΩ
VBATT
2.5V TO 5.5V
VDD
160kΩ
OUT+
MODULATOR
(Σ-Δ)
FET
DRIVER
OUT–
47nF
160kΩ
SHUTDOWN
SD
BIAS
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
07243-033
GND
Figure 33. Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 11 of 16
SSM2305
GAIN
LAYOUT
The SSM2305 has a default gain of 18 dB that can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 160 kΩ/(20 kΩ + REXT)
As output power continues to increase, care needs to be taken
to lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
track length for lowest dc resistance (DCR), and use 1 oz or 2 oz
of copper PCB traces to further reduce IR drops and inductance.
A poor layout increases voltage drops, consequently affecting
efficiency. Use large traces for the power supply inputs and
amplifier outputs to minimize losses due to parasitic trace
resistance.
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown activates or deactivates. Voltage transients as low as
10 mV can be heard as audio pops in the speaker. Clicks and
pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2305 has a pop-and-click suppression architecture
that reduces these output transients resulting in noiseless activation
and deactivation.
OUTPUT MODULATION DESCRIPTION
The SSM2305 uses 3-level, Σ-Δ output modulation. Each output is
able to swing from GND to VDD and vice versa. Ideally, when no
input signal is present, the output differential voltage is 0 V because
there is no need to generate a pulse. In a real-world situation,
there are always noise sources present. Due to this constant presence of noise, a differential pulse generates when it is required
in response to this stimulus. A small amount of current flows
into the inductive load when the differential pulse is generated.
However, most of the time, output differential voltage is 0 V,
due to the Analog Devices patented 3-level, Σ-Δ output modulation. This feature ensures that the current flowing through
the inductive load is small.
When the user wants to send an input signal, an output pulse is
generated to follow the input voltage. The differential pulse density
is increased by raising the input signal level. Figure 34 depicts
3-level, Σ-Δ output modulation with and without input stimuli.
OUTPUT = 0V
+5V
Proper grounding guidelines help improve audio performance,
minimize crosstalk between channels, and prevent switching noise
from coupling into the audio signal. To maintain high output swing
and high peak output power, the PCB traces that connect the
output pins to the load and supply pins should be as wide as
possible to maintain the minimum trace resistances. It is also
recommended that a large ground plane be used for minimum
impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. Separate high frequency circuits
(analog and digital) from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted with
signal crossover.
If the system has separate analog and digital ground and power
planes, place the analog ground plane underneath the analog
power plane, and, similarly, place the digital ground plane
underneath the digital power plane. There should be no overlap
between analog and digital ground planes or analog and digital
power planes.
OUT+
INPUT CAPACITOR SELECTION
0V
+5V
OUT–
The SSM2305 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass
filtering is needed, or if using a single-ended source. If high-pass
filtering is needed at the input, the input capacitor, together with
the input resistor of the SSM2305, form a high-pass filter whose
corner frequency is determined by the following equation:
0V
+5V
VOUT
0V
–5V
OUTPUT > 0V
+5V
OUT+
0V
+5V
OUT–
0V
+5V
VOUT
0V
fC = 1/(2π × RIN × CIN)
OUTPUT < 0V
+5V
OUT+
0V
+5V
OUT–
0V
VOUT
–5V
07243-003
0V
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the dc PSRR performance.
Figure 34. 3-Level Σ-Δ Output Modulation With and Without Input Stimuli
Rev. 0 | Page 12 of 16
SSM2305
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short duration
voltage spikes. Although the actual switching frequency can range
from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz. The
power supply input needs to be decoupled with a good quality
low ESL, low ESR capacitor, usually of around 4.7 μF. This
capacitor bypasses low frequency noises to the ground plane.
For high frequency transient noise, use a 0.1 μF capacitor as
close as possible to the VDD pin of the device. Placing the
decoupling capacitor as close as possible to the SSM2305 helps
maintain efficient performance.
Rev. 0 | Page 13 of 16
SSM2305
OUTLINE DIMENSIONS
3.25
3.00 SQ
2.75
0.60 MAX
5
2.95
2.75 SQ
2.55
TOP
VIEW
PIN 1
INDICATOR
8
12° MAX
(BOTTOM VIEW)
1
0.50
0.40
0.30
0.70 MAX
0.65 TYP
1.60
1.45
1.30
EXPOSED
PAD
4
PIN 1
INDICATOR
1.89
1.74
1.59
0.05 MAX
0.01 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
061507-B
0.90 MAX
0.85 NOM
0.50
BSC
0.60 MAX
Figure 35. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
5.15
4.90
4.65
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 36. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
SSM2305CPZ-R2 1
SSM2305CPZ-REEL1
SSM2305CPZ-REEL71
SSM2305RMZ-R21
SSM2305RMZ-REEL1
SSM2305RMZ-REEL71
SSM2305-EVALZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
Evaluation Board with LFCSP Model
Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
Package Option
CP-8-2
CP-8-2
CP-8-2
RM-8
RM-8
RM-8
Branding
Y10
Y10
Y10
Y10
Y10
Y10
SSM2305
NOTES
Rev. 0 | Page 15 of 16
SSM2305
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07243-0-3/08(0)
Rev. 0 | Page 16 of 16