Filterless High Efficiency Mono 1.4 W Class-D Audio Amplifier SSM2301 Preliminary Technical Data output power. It operates with 85% efficiency at 1.4 W into 8 Ω from a 5.0 V supply and has a signal-to-noise ratio (SNR) that is better than 93 dB. Spread-spectrum modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. FEATURES Filterless Class-D amplifier with built-in output stage 1.4 W into 8 Ω at 5.0 V supply with less than 1% THD 85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker Better than 98 dB SNR (signal-to-noise ratio) Single-supply operation from 2.5 V to 5.0 V 20 nA ultralow shutdown current Short-circuit and thermal protection Available in 8-lead, 3 mm × 3 mm LFCSP Pop-and-click suppression Built-in resistors reduce board component count Fixed and user-adjustable gain configurations The SSM2301 has a micropower shutdown mode with a maximum shutdown current of 30 nA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry. This minimizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. APPLICATIONS Mobile phones MP3 players Portable gaming Portable electronics Educational toys The fully differential input of the SSM2301 provides excellent rejection of common-mode noise on the input. Input coupling capacitors can be omitted if the dc input common-mode voltage is approximately VDD/2. GENERAL DESCRIPTION The SSM2301 also has excellent rejection of power supply noise, including noise caused by GSM transmission bursts and RF rectification. PSRR is typically 63 dB at 217 Hz. The SSM2301 is a fully integrated, high efficiency, Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of continuous output power with less than 1% THD + N driving an 8 Ω load from a 5.0 V supply. The gain can be set to 6 dB or 12 dB utilizing the gain control select pin connected respectively to ground or VDD. Gain can also be adjusted externally by using an external resistor. The SSM2301 is specified over the comercial temperature range (−40°C to +85°C). It has built-in thermal shutdown and output short-circuit protection. It is available in an 8-lead, 3 mm × 3 mm lead-frame chip scale package (LFCSP). The SSM2301 features a high efficiency, low noise modulation scheme that does not require any external LC output filters. The modulation continues to provide high efficiency even at low FUNCTIONAL BLOCK DIAGRAM 10µF 0.1µF SSM2301 0.01µF1 AUDIO IN+ VDD OUT+ IN+ IN– AUDIO IN– VBATT 2.5V TO 5.0V GAIN CONTROL MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– 0.01µF1 GAIN SD SHUTDOWN BIAS 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. 06163-001 GND Figure 1. Rev. PrH Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. SSM2301 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Pop-and-Click Suppression ...................................................... 11 Applications....................................................................................... 1 Layout .......................................................................................... 12 General Description ......................................................................... 1 Input Capacitor Selection.......................................................... 12 Functional Block Diagram .............................................................. 1 Proper Power Supply Decoupling ............................................ 12 Revision History ............................................................................... 2 Evaluation Board Information...................................................... 13 Specifications..................................................................................... 3 Introduction................................................................................ 13 Absolute Maximum Ratings............................................................ 4 Operation .................................................................................... 13 Thermal Resistance ...................................................................... 4 SSM2301 Application Board Schematic.................................. 14 ESD Caution.................................................................................. 4 SSM2301 Stereo Class-D Amplifier Evaluation Module Component List.......................................................................... 15 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Typical Application Circuits............................................................ 9 Application Notes ........................................................................... 11 SSM2301 Application Board Layout........................................ 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 Overview...................................................................................... 11 Gain Selection ............................................................................. 11 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. PrH | Page 2 of 19 Preliminary Technical Data SSM2301 SPECIFICATIONS VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted Table 1. Parameter DEVICE CHARACTERISTICS Output Power Symbol Conditions PO RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V POUT =1.4 W, 8 Ω, VDD = 5.0 V 1.4 0.615 0.275 1.53 0.77 0.35 85 W W W W W W % PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V PO = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.1 0.04 % % V dB MHz mV Efficiency η Total Harmonic Distortion + Noise THD + N Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio VCM CMRRGSM fSW VOOS VDD PSRR PSRRGSM Supply Current ISY Shutdown Current ISD GAIN CONTROL Closed-Loop Gain Min Typ 1.0 VCM = 2.5 V ± 100 mV at 217 Hz VDD − 1 55 1.8 2.0 G = 6 dB; G = 12 dB Guaranteed from PSRR test VDD = 2.5 V to 5.0 V, 50 Hz, input floating/ground VRIPPLE = 100 mV at 217 Hz, inputs ac GND, CIN = 0.01 μF, input referred VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V SD = GND Max 2.5 70 5.0 Unit 85 63 V dB dB 5.5 4.5 4.0 20 mA mA mA nA Av0 Av1 ZIN GAIN pin = 0 V GAIN pin = VDD SD = VDD, SD = GND 6 12 150 210 dB dB KΩ KΩ SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance VIH VIL tWU tSD ZOUT ISY ≥ 1 mA ISY ≤ 300 nA SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND 1.2 0.5 30 5 >100 V V ms μs KΩ NOISE PERFORMANCE Output Voltage Noise en VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are ac grounded, sine wave, AV = 6 dB, A weighting POUT = 1.4 W, RL = 8 Ω 35 μV 98 dB Differential Input Impedance Signal-to-Noise Ratio SNR Rev. PrH | Page 3 of 19 SSM2301 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 2. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering, 60 sec) Rating 6V VDD VDD −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 8-lead, 3 mm × 3 mm LFCSP θJA 62 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrH | Page 4 of 19 θJC TBD Unit °C/W Preliminary Technical Data SSM2301 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SD 1 PIN 1 INDICATOR GAIN 2 SSM2301 7 GND TOP VIEW (Not to Scale) 5 OUT+ IN– 4 6 VDD 06163-002 IN+ 3 8 OUT– Figure 2. SSM2301 LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic SD GAIN IN+ INL− OUT+ VDD GND OUT− Description Shutdown Input. Active low digital input. Gain Selection. Digital input. Noninverting Input. Inverting Input. Noninverting Output. Power Supply. Ground. Inverting Output. Rev. PrH | Page 5 of 19 SSM2301 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 100 100 RL = 8Ω, 33µH GAIN = 12dB VDD = 3.6V RL = 8Ω, 33µH 10 VDD = 2.5V 10 THD + N (%) THD + N (%) 1 1 VDD = 3.6V 500mW 0.1 125mW 250mW 0.01 0.1 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.0001 10 1k 10k 100k 100k FREQUENCY (Hz) Figure 3. THD + N vs. Output Power into 8 Ω, AV = 12 dB 100 100 06163-006 0.001 0.0001 06163-007 0.01 0.000001 0.00001 06163-003 VDD = 5V Figure 6. THD + N vs. Frequency, VDD = 3.6 V 100 RL = 8Ω, 33µH GAIN = 6dB VDD = 2.5V RL = 8Ω, 33µH 10 VDD = 2.5V 10 THD + N (%) THD + N (%) 1 1 250mW 0.1 750mW 125mW 0.01 VDD = 3.6V 0.1 0.001 0.000001 0.0001 0.0000001 0.00001 0.001 0.01 0.1 1 06163-004 VDD = 5V 0.01 10 OUTPUT POWER (W) 0.0001 10 Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB 100 100 1k 10k FREQUENCY (Hz) Figure 7. THD + N vs. Frequency, VDD = 2.5 V VDD = 5V RL = 8Ω, 33µH 10 THD + N (%) 1 1W 0.1 0.01 250mW 500mW 0.0001 10 100 1k 10k FREQUENCY (Hz) 100k 06163-005 0.001 Figure 5. THD + N vs. Frequency, VDD = 5.0 V Figure 8. Supply Current vs. Supply Voltage, No Load Rev. PrH | Page 6 of 19 Preliminary Technical Data SSM2301 12 0.9 VDD = 3.6V RL = 8Ω, 33µH 0.8 POWER DISSIPATION (W) SHUTDOWN CURRENT (µA) 10 8 VDD = 5V 6 VDD = 2.5V 4 VDD = 3.6V 0.7 0.6 0.5 0.4 0.3 0.2 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 SHUTDOWN VOLTAGE (V) 0 06163-009 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 OUTPUT POWER (W) Figure 9. Supply Current vs. Shutdown Voltage 06163-012 0.1 Figure 12. Power Dissipation vs. Output Power at VDD = 3.6 V 1.6 VDD = 5V RL = 8Ω, 33µH POWER DISSIPATION (W) 1.4 1.2 1.0 0.8 0.6 0.4 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 OUTPUT POWER (W) Figure 13. Power Dissipation vs. Output Power at VDD = 5.0 V Figure 10. Maximum Output Power vs. Supply Voltage 100 90 RL = 8Ω, 33µH 350 VDD = 5V 300 VDD = 2.5V RL = 8Ω, 33µH 80 SUPPLY CURRENT (mA) VDD = 3.6V 50 40 30 20 10 VDD = 5V VDD = 3.6V 250 200 VDD = 2.5V 150 100 50 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT POWER (W) 1.4 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 OUTPUT POWER (W) Figure 11. Efficiency vs. Output Power into 8 Ω Figure 14. Output Power vs. Supply Current, One Channel Rev. PrH | Page 7 of 19 1.6 06163-014 0 06163-011 EFFICIENCY (%) 70 60 06163-013 0.2 SSM2301 Preliminary Technical Data 0 7 –10 6 –20 5 4 –40 VOLTAGE –50 –60 SD INPUT 3 2 1 –70 OUTPUT 0 –80 100 1k 10k 100k FREQUENCY (Hz) –2 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 06163-015 –100 10 TIME (ms) Figure 15. Power Supply Rejection Ratio vs. Frequency 0 –10 Figure 17. Turn-On Response 7 RL = 8Ω, 33µH GAIN = 6dB 5 SD INPUT 4 VOLTAGE –30 –40 –50 3 2 1 –60 0 –70 –1 100 1k 10k FREQUENCY (Hz) 100k 06163-016 CMRR (dB) OUTPUT 6 –20 –80 10 06163-017 –1 –90 Figure 16. Common-Mode Rejection Ratio vs. Frequency –2 –20 0 20 40 60 80 100 120 TIME (ms) Figure 18. Turn-Off Response Rev. PrH | Page 8 of 19 140 160 180 06163-018 PSRR (dB) –30 Preliminary Technical Data SSM2301 TYPICAL APPLICATION CIRCUITS 10µF 0.1µF VBATT 2.5V TO 5.0V SSM2301 0.01µF1 VDD IN+ AUDIO IN+ OUT+ GAIN CONTROL IN– AUDIO IN– MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– 0.01µF1 VDD GAIN SD SHUTDOWN BIAS 06163-019 GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 19. Differential Input Configuration, Gain = 12 dB 10µF 0.1µF VBATT 2.4V TO 5.0V SSM2301 0.01µF VDD IN+ AUDIO IN OUT+ GAIN CONTROL IN– MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– 0.01µF GAIN SD SHUTDOWN BIAS 06163-020 GND Figure 20. Single-Ended Input Configuration, Gain = 6 dB EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)] 10µF 0.1µF SSM2301 VDD IN+ R IN– AUDIO IN– 0.01µF1 V DD MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– GAIN SD SHUTDOWN OUT+ GAIN CONTROL BIAS GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 21. Differential Input Configuration, User-Adjustable Gain Rev. PrH | Page 9 of 19 06163-021 AUDIO IN+ 0.01µF1 R VBATT 2.4V TO 5.0V SSM2301 Preliminary Technical Data EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)] 10µF 0.1µF SSM2301 0.01µF AUDIO IN R VDD IN+ R IN– 0.01µF V DD OUT+ GAIN CONTROL MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– GAIN SD SHUTDOWN VBATT 2.4V TO 5.0V BIAS 06163-022 GND Figure 22. Single-Ended Input Configuration, User-Adjustable Gain EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)] 10µF 0.1µF SSM2301 AUDIO IN+ 0.01µF1 R R AUDIO IN– VBATT 2.4V TO 5.0V VDD IN+ IN– OUT+ GAIN CONTROL MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– 0.01µF1 GAIN SD SHUTDOWN BIAS 06163-023 GND 1 INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE VOLTAGE IS APPROXIMATELY VDD/2. Figure 23. Differential Input Configuration, User-Adjustable Gain EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)] 10µF 0.1µF SSM2301 0.01µF AUDIO IN R VDD IN+ IN– 0.01µF VBATT 2.4V TO 5.0V OUT+ GAIN CONTROL MODULATOR FET DRIVER OSCILLATOR POP/CLICK SUPRESSION OUT– R GAIN SD BIAS GND 06163-024 SHUTDOWN Figure 24. Single-Ended Input Configuration, User-Adjustable Gain Rev. PrH | Page 10 of 19 Preliminary Technical Data SSM2301 APPLICATION NOTES OVERVIEW POP-AND-CLICK SUPPRESSION The SSM2301 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external components count, conserving board space and thus reducing systems cost. The SSM2301 does not require an output filter, but instead relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square-wave output. While most Class-D amplifiers use some variation of pulse-width modulation (PWM), the SSM2301 uses a Σ-Δ modulation to determine the switching pattern of the output devices. This provides a number of important benefits. Σ-Δ modulators do not produces a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation provides the benefits of reducing the amplitude of spectral components at high frequencies; that is, reducing EMI emission that might otherwise be radiated by speakers and long cable traces. The SSM2301 also offers protection circuits for overcurrent and temperature protection. Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system, therefore as not coming from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, the following can be sources of audible transients: system power-up/ power-down, mute/unmute, input source change, and sample rate change. The SSM2301 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. GAIN SELECTION Pulling the GAIN pin high of the SSM2301 sets the gain of the speaker amplifier to 12 dB; pulling it low sets the gain of the speaker amplifier to 6 dB. It is possible to adjust the SSM2301 gain by using external resistors at the input. To set a gain lower than 12 dB refer to Figure 21 for differential input configuration and Figure 22 for single-ended configuration. For external gain configuration from a fixed 12 dB gain, use the following formula: External Gain Settings = 20 log[4/(1 + R/150 kΩ)] To set a gain lower than 6 dB refer to Figure 23 for differential input configuration and Figure 24 for single-ended configuration. For external gain configuration from a fixed 6 dB gain, use the following formula: External Gain Settings = 20 log[2/(1 + R/150 kΩ)] Rev. PrH | Page 11 of 19 SSM2301 Preliminary Technical Data LAYOUT INPUT CAPACITOR SELECTION As output power continues to increase, care needs to be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Make track widths at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins should be as wide as possible to maintain the minimum trace resistances. It is also recommended to use a large-area ground plane for minimum impedances. Good PCB layouts also isolate critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency ones. Properly designed multilayer printed circuit boards can reduce EMI emission and increase immunity to RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for ground plane, whereas the ground plane side of a doubleside board is often disrupted with signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be underneath the analog power plane, and, similarly, the digital ground plane should be underneath the digital power plane. There should be no overlap between analog and digital ground planes nor analog and digital power planes. The SSM2301 will not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed (Figure 19), or if using a singleended source (Figure 20). If high-pass filtering is needed at the input, the input capacitor along with the input resistor of the SSM2301 will form a high-pass filter whose corner frequency is determined by the following equation: fC = 1/(2π × RIN × CIN) Input capacitor can have very important effects on the circuit performance. Not using input capacitors degrades the output offset of the amplifier as well as the PSRR performance. PROPER POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. Although the actual switching frequency can range from 10 kHz to 100 kHz, these spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input needs to be decoupled with a good quality low ESL and low ESR capacitor—usually around 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transients noises, use a 0.1 μF capacitor as close as possible to the VDD pin of the device. Placing the decoupling capacitor as close as possible to the SSM2301 helps maintain efficiency performance. Rev. PrH | Page 12 of 19 Preliminary Technical Data SSM2301 EVALUATION BOARD INFORMATION INTRODUCTION Gain Control The SSM2301 audio power amplifier is a complete low power, Class-D, stereo audio amplifier capable of delivering 1.4 W/channel into 8 Ω load. In addition to the minimal parts required for the application circuit, measurement filters are provided on the evaluation board so that conventional audio measurements can be made without additional components. The gain select header controls the gain setting of the SSM2301. This section provides an overview of Analog Devices SSM2301 evaluation board. It includes a brief description of the board as well as a list of the board specifications. Table 5. SSM2301 Evaluation Board Specifications Parameter Supply Voltage Range, VDD Power Supply Current Rating Continuous Output Power, PO (RL = 8 Ω, f = 1 kHz, 22 kHz BW) Minimum Load Impedance Specification 2.5 V to 5.0 V 1.5 A 1.4 W 8Ω 1. Select jumper to LG for 6 dB gain. 2. Select jumper to HG for 12 dB gain. External Gain Settings It is possible to adjust the SSM2301 gain using external resistors at the input. To set a gain lower than 12 dB refer to Figure 21 and Figure 22 on the product data sheet for proper circuit configuration. For external gain configuration from a fixed 12 dB gain, use the following formula: External Gain Settings = 20 log[4/(1 + R/150 kΩ)] To set a gain lower than 6 dB refer to Figure 23 and Figure 24 on the product data sheet for proper circuit configuration. For external gain configuration from a fixed 6 dB gain, use the following formula: External Gain Settings = 20 log[2/(1 + R/150 kΩ)] OPERATION Shutdown Control Use the following steps when operating the SSM2301 evaluation board. Power and Ground 1. Set the power supply voltage between 2.5 V and 5.0 V. When connecting the power supply to the SSM2301 evaluation board, make sure to attach the ground connection to the GND header pin first and then connect the positive supply to the VDD header pin. Inputs and Outputs 1. Ensure that the audio source is set to the minimum level. 2. Connect the audio source to Inputs IN± and IN±. 3. Connect the speakers to Outputs OUT± and OUT±. The shutdown select header controls the shutdown function of the SSM2301. The shutdown pin on the SSM2301 is active low, meaning that a low voltage (GND) on this pin places the SSM2301 into shutdown mode. 1. Select jumper to 1-2 position. Shutdown pulled to VDD. 2. Select jumper to 2-3 position. Shutdown pulled to GND. Input Configurations 1. For differential input configuration with input capacitors do not place a jumper on J2 and J3. 2. For differential input configuration without input capacitors place a jumper on J2 and J3. Rev. PrH | Page 13 of 19 SSM2301 Preliminary Technical Data SSM2301 APPLICATION BOARD SCHEMATIC J3 POWER 1 2 VDD J2 C7 0.1µF C6 0.1µF C5 10µF 1 2 J1 C1 0.1µF 2 1 SD GAIN C2 0.1µF 1 2 3 4 SD OUT– GAIN GND IN+ VDD IN– OUT+ 8 J4 7 1 2 6 OUTPUT VDD 5 2 1 JP3 VDD R3 100kΩ GAIN VDD JP6 1 3 5 2 4 6 HEADER 3X2 SD R4 100kΩ Figure 25. SSM2301 Application Board Schematic Rev. PrH | Page 14 of 19 06163-025 4 3 Preliminary Technical Data SSM2301 SSM2301 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST Table 6. Reference C6, C7 C5 C1, C2, C3, C4 R3, R4 L1, L2, U1 EVAL BOARD Description Capacitor, 0.1 μF Capacitor, 10 μF Capacitor, 1 nF Resistor, 100 kΩ Ferrite bead IC, SSM2301 PCB evaluation board Footprint 0603 0805 0402 0603 0402 3.0 mm × 3.0 mm Quantity 2 1 4 2 2 1 1 Rev. PrH | Page 15 of 19 Manufacturer/Part Number Murata Manufacturing Co., Ltd./GRM18 Murata Manufacturing Co., Ltd./GRM21 Murata Manufacturing Co., Ltd./GRM15 Vishay/CRCW06031003F Murata Manufacturing Co., Ltd./BLM15EG121 SSM2301CSPZ SSM2301 Preliminary Technical Data 06163-035 SSM2301 APPLICATION BOARD LAYOUT Figure 26. SSM2301 Application Board Layout Rev. PrH | Page 16 of 19 Preliminary Technical Data SSM2301 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 1 8 PIN 1 INDICATOR 0.90 MAX 0.85 NOM 2.75 BSC SQ TOP VIEW 0.50 BSC 1.50 REF 5 1.89 1.74 1.59 4 1.60 1.45 1.30 0.70 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 0.05 MAX 0.01 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model SSM2301CPZ-R21 SSM2301CPZ-REEL1 SSM2301CPZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VD] 16-Lead Lead Frame Chip Scale Package [LFCSP_VD] 16-Lead Lead Frame Chip Scale Package [LFCSP_VD] Z = Pb-free part. Rev. PrH | Page 17 of 19 Package Option CP-8-2 CP-8-2 CP-8-2 Branding A1C A1C A1C SSM2301 Preliminary Technical Data NOTES Rev. PrH | Page 18 of 19 Preliminary Technical Data SSM2301 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06163-0-7/06(PrH) Rev. PrH | Page 19 of 19