Filterless, High Efficiency, Mono 2.5 W Class-D Audio Amplifier SSM2377 The SSM2377 operates with 92% efficiency at 1.4 W into 8 Ω from a 5.0 V supply and has an SNR of >100 dB. FEATURES Filterless, Class-D amplifier with spread-spectrum Σ-Δ modulation 2.5 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) 92% efficiency at 5.0 V, 1.4 W into 8 Ω speaker >100 dB signal-to-noise ratio (SNR) High PSRR at 217 Hz: 80 dB Ultralow EMI emissions Single-supply operation from 2.5 V to 5.5 V Gain select function: 6 dB or 12 dB Fixed input impedance of 80 kΩ 100 nA shutdown current Short-circuit and thermal protection with autorecovery Available in a 9-ball, 1.2 mm × 1.2 mm WLCSP Pop-and-click suppression Spread-spectrum pulse density modulation (PDM) is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The inherent randomized nature of spread-spectrum PDM eliminates the clock intermodulation (beating effect) of several amplifiers in close proximity. The SSM2377 produces ultralow EMI emissions that significantly reduce the radiated emissions at the Class-D outputs, particularly above 100 MHz. The SSM2377 passes FCC Class B radiated emission testing with 50 cm, unshielded speaker cable without any external filtering. The ultralow EMI emissions of the SSM2377 are also helpful for antenna and RF sensitivity problems. The device is configured for either a 6 dB or a 12 dB gain setting by connecting the GAIN pin to the VDD pin or the GND pin, respectively. Input impedance is a fixed value of 80 kΩ, independent of the gain select operation. APPLICATIONS Mobile phones MP3 players Portable electronics The SSM2377 has a micropower shutdown mode with a typical shutdown current of 100 nA. Shutdown is enabled by applying a logic low to the SD pin. GENERAL DESCRIPTION The device also includes pop-and-click suppression circuitry, which minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. Built-in input low-pass filtering is also included to suppress outof-band noise interference to the PDM modulator. The SSM2377 is a fully integrated, high efficiency, Class-D audio amplifier. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a single 2.5 V to 5.5 V supply. It is capable of delivering 2.5 W of continuous output power with <1% THD + N driving a 4 Ω load from a 5.0 V supply. The SSM2377 is specified over the industrial temperature range of −40°C to +85°C. It has built-in thermal shutdown and output short-circuit protection. It is available in a halide-free, 9-ball, 0.4 mm pitch, 1.2 mm × 1.2 mm wafer level chip scale package (WLCSP). The SSM2377 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The modulation operates with high efficiency even at low output power. FUNCTIONAL BLOCK DIAGRAM POWER SUPPLY 2.5V TO 5.5V 10µF 0.1µF SSM2377 22nF AUDIO IN– IN+ AUDIO IN+ 22nF SHUTDOWN VDD 80kΩ 80kΩ IN– OUT+ MODULATOR (Σ-Δ) BIAS SD INTERNAL OSCILLATOR POP/CLICK AND EMI SUPPRESSION OUT– GND 09824-001 GAIN FET DRIVER GAIN SELECT GAIN = 6dB OR 12dB Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. SSM2377 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Overview ..................................................................................... 13 General Description ......................................................................... 1 Gain Selection ............................................................................. 13 Functional Block Diagram .............................................................. 1 Pop-and-Click Suppression ...................................................... 13 Revision History ............................................................................... 2 EMI Noise.................................................................................... 13 Specifications..................................................................................... 3 Output Modulation Description .............................................. 13 Absolute Maximum Ratings............................................................ 5 Layout .......................................................................................... 14 Thermal Resistance ...................................................................... 5 Input Capacitor Selection .......................................................... 14 ESD Caution .................................................................................. 5 Power Supply Decoupling ......................................................... 14 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 15 Typical Application Circuits.......................................................... 12 REVISION HISTORY 5/11—Revision 0: Initial Version Rev. 0 | Page 2 of 16 SSM2377 SPECIFICATIONS VDD = 5.0 V, TA = 25°C, RL = 8 Ω +33 μH, unless otherwise noted. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Efficiency Total Harmonic Distortion Plus Noise Symbol Test Conditions/Comments POUT f = 1 kHz, 20 kHz BW RL = 8 Ω, THD = 1%, VDD = 5.0 V RL = 8 Ω, THD = 1%, VDD = 3.6 V RL = 8 Ω, THD = 1%, VDD = 2.5 V RL = 8 Ω, THD = 10%, VDD = 5.0 V RL = 8 Ω, THD = 10%, VDD = 3.6 V RL = 8 Ω, THD = 10%, VDD = 2.5 V RL = 4 Ω, THD = 1%, VDD = 5.0 V RL = 4 Ω, THD = 1%, VDD = 3.6 V RL = 4 Ω, THD = 1%, VDD = 2.5 V RL = 4 Ω, THD = 10%, VDD = 5.0 V RL = 4 Ω, THD = 10%, VDD = 3.6 V RL = 4 Ω, THD = 10%, VDD = 2.5 V POUT = 1.4 W into 8 Ω, VDD = 5.0 V POUT = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V η THD + N Min CMRR fSW fOSC VOOS VDD Supply Current PSRRGSM PSRR ISY Shutdown Current ISD GAIN CONTROL Closed-Loop Gain Gain Input Impedance ZIN SHUTDOWN CONTROL Input Voltage High Input Voltage Low Turn-On Time Turn-Off Time Output Impedance VIH VIL tWU tSD ZOUT Unit W W W W W W W W W W W W % % 0.009 1.0 VCM Max 1.41 0.72 0.33 1.78 0.90 0.41 2.49 1.25 0.54 3.17 1 1.56 0.68 92.4 0.007 POUT = 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V Input Common-Mode Voltage Range Common-Mode Rejection Ratio Average Switching Frequency Clock Frequency Differential Output Offset Voltage POWER SUPPLY Supply Voltage Range Power Supply Rejection Ratio Typ VDD − 1 % V 100 mV rms at 1 kHz 51 dB Gain = 6 dB 256 6.2 0.4 5.0 kHz MHz mV 5.5 V Guaranteed from PSRR test Inputs are ac-grounded, CIN = 0.1 μF, gain = 6 dB VRIPPLE = 100 mV at 217 Hz VRIPPLE = 100 mV at 1 kHz VIN = 0 V, no load, VDD = 5.0 V VIN = 0 V, no load, VDD = 3.6 V VIN = 0 V, no load, VDD = 2.5 V VIN = 0 V, RL = 8 Ω + 33 μH, VDD = 5.0 V VIN = 0 V, RL = 8 Ω + 33 μH, VDD = 3.6 V VIN = 0 V, RL = 8 Ω + 33 μH, VDD = 2.5 V SD = GND 2.5 GAIN = GND GAIN = VDD SD = VDD, gain = 6 dB or 12 dB 80 80 2.5 2.0 1.9 2.5 2.0 1.8 100 dB dB mA mA mA mA mA mA nA 12 6 80 dB dB kΩ 1.35 0.35 SD rising edge from GND to VDD SD falling edge from VDD to GND SD = GND Rev. 0 | Page 3 of 16 12.5 5 100 V V ms μs kΩ SSM2377 Parameter NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio 1 Symbol Test Conditions/Comments en f = 20 Hz to 20 kHz, inputs are ac-grounded, gain = 6 dB, A-weighted VDD = 5.0 V VDD = 3.6 V POUT = 1.4 W, RL = 8 Ω, A-weighted SNR Min Typ Max 30 30 101 Although the SSM2377 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations. Rev. 0 | Page 4 of 16 Unit μV μV dB SSM2377 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. THERMAL RESISTANCE Table 2. Junction-to-air thermal resistance (θJA) is specified for the worstcase conditions, that is, a device soldered in a printed circuit board (PCB) for surface-mount packages. θJA is determined according to JEDEC JESD51-9 on a 4-layer PCB with natural convection cooling. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) ESD Susceptibility Rating 6V VDD VDD −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C 4 kV Table 3. Thermal Resistance Package Type 9-Ball, 1.2 mm × 1.2 mm WLCSP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 5 of 16 PCB 2S2P θJA 88 Unit °C/W SSM2377 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 IN+ GAIN OUT– VDD VDD GND IN– SD OUT+ A B 09824-002 C TOP VIEW (BALL SIDE DOWN) Not to Scale Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. A1 B1 C1 A2 B2 C2 A3 B3 C3 Mnemonic IN+ VDD IN− GAIN VDD SD OUT− GND OUT+ Description Noninverting Input. Power Supply. Inverting Input. Gain Selection Pin. Power Supply. Shutdown Input. Active low digital input. Inverting Output. Ground. Noninverting Output. Rev. 0 | Page 6 of 16 SSM2377 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 RL = 8Ω + 33µH GAIN = 6dB RL = 8Ω + 33µH GAIN = 12dB 10 10 VDD = 3.6V 1 THD + N (%) THD + N (%) VDD = 3.6V VDD = 2.5V 0.1 1 0.1 VDD = 2.5V 0.01 0.01 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 09824-003 0.001 0.0001 10 RL = 4Ω + 15µH GAIN = 12dB 10 THD + N (%) VDD = 3.6V 0.1 VDD = 5V 10 VDD = 5V 1 VDD = 2.5V 0.01 1 VDD = 3.6V 0.1 VDD = 2.5V 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 09824-005 0.001 0.001 0.01 0.1 1 10 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 4 Ω, Gain = 6 dB 09824-006 0.01 0.001 0.0001 Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 12 dB 100 100 VDD = 5V GAIN = 6dB RL = 8Ω + 33µH 10 THD + N (%) 1 0.1 VDD = 5V GAIN = 12dB RL = 8Ω + 33µH 1 0.1 1W 1W 0.25W 0.01 0.25W 0.01 1k 10k 100k FREQUENCY (Hz) 09824-007 100 Figure 5. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 6 dB 0.001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 8. THD + N vs. Frequency, VDD = 5 V, RL = 8 Ω, Gain = 12 dB Rev. 0 | Page 7 of 16 09824-008 0.5W 0.5W 0.001 10 1 100 RL = 4Ω + 15µH GAIN = 6dB THD + N (%) 0.1 Figure 6. THD + N vs. Output Power into 8 Ω, Gain = 12 dB 100 THD + N (%) 0.01 OUTPUT POWER (W) Figure 3. THD + N vs. Output Power into 8 Ω, Gain = 6 dB 10 0.001 09824-004 VDD = 5V VDD = 5V SSM2377 100 2W 0.1 1 VDD = 5V GAIN = 12dB RL = 4Ω + 15µH 2W 0.1 0.5W 0.5W 0.01 0.01 1W 1W 100 1k 10k 100k FREQUENCY (Hz) 0.001 10 09824-009 0.001 10 100k 100 VDD = 3.6V GAIN = 6dB RL = 8Ω + 33µH 10 1 THD + N (%) THD + N (%) 10k Figure 12. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 12 dB 100 0.1 1k FREQUENCY (Hz) Figure 9. THD + N vs. Frequency, VDD = 5 V, RL = 4 Ω, Gain = 6 dB 10 100 09824-010 THD + N (%) 1 10 THD + N (%) 10 100 VDD = 5V GAIN = 6dB RL = 4Ω + 15µH 0.5W VDD = 3.6V GAIN = 12dB RL = 8Ω + 33µH 1 0.1 0.5W 0.25W 0.125W 100 1k 10k 100k FREQUENCY (Hz) 0.001 10 09824-011 10 THD + N (%) 1W 1 100k VDD = 3.6V GAIN = 12dB RL = 4Ω + 15µH 1W 0.1 0.25W 0.25W 0.01 0.01 0.5W 100 1k 10k 100k FREQUENCY (Hz) 09824-013 THD + N (%) 10k 100 VDD = 3.6V GAIN = 6dB RL = 4Ω + 15µH 0.1 0.001 10 1k Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 12 dB 100 1 100 FREQUENCY (Hz) Figure 10. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, Gain = 6 dB 10 0.125W 0.25W Figure 11. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 6 dB 0.001 10 0.5W 100 1k 10k 100k FREQUENCY (Hz) Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, Gain = 12 dB Rev. 0 | Page 8 of 16 09824-014 0.001 10 0.01 09824-012 0.01 SSM2377 100 10 0.1 THD + N (%) THD + N (%) 1 0.25W VDD = 2.5V GAIN = 12dB RL = 8Ω + 33µH 1 0.1 0.25W 0.0625W 0.01 0.0625W 0.01 0.125W 100 1k 0.125W 10k 100k FREQUENCY (Hz) 0.001 10 09824-015 0.001 10 10k 100k Figure 18. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 12 dB 100 VDD = 2.5V GAIN = 6dB RL = 4Ω + 15µH 10 10 VDD = 2.5V GAIN = 12dB RL = 4Ω + 15µH 0.5W 0.5W THD + N (%) 1 THD + N (%) 1k FREQUENCY (Hz) Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, Gain = 6 dB 100 100 09824-016 10 100 VDD = 2.5V GAIN = 6dB RL = 8Ω + 33µH 0.1 1 0.1 0.125W 0.125W 0.01 0.01 1k 10k 100k FREQUENCY (Hz) 09824-017 100 0.001 10 100k 3.0 2.9 QUIESCENT CURRENT (mA) 2.7 2.6 2.5 2.4 2.3 RL = 4Ω + 15µH 2.2 2.1 NO LOAD 2.0 1.9 2.5 2.4 2.3 2.2 2.0 1.9 5.0 5.5 SUPPLY VOLTAGE (V) 09824-019 1.7 4.5 Figure 17. Quiescent Current vs. Supply Voltage, Gain = 6 dB NO LOAD 2.1 1.8 4.0 RL = 4Ω + 15µH 2.6 1.7 3.5 RL = 8Ω + 33µH 2.7 1.8 3.0 GAIN = 12dB 2.8 RL = 8Ω + 33µH 1.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Figure 20. Quiescent Current vs. Supply Voltage, Gain = 12 dB Rev. 0 | Page 9 of 16 09824-020 GAIN = 6dB 2.8 QUIESCENT CURRENT (mA) 10k Figure 19. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 12 dB 3.0 1.6 2.5 1k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, Gain = 6 dB 2.9 100 09824-018 0.25W 0.25W 0.001 10 SSM2377 2.0 f = 1kHz GAIN = 6dB RL = 8Ω + 33µH 1.8 1.6 OUTPUT POWER (W) 1.4 1.2 1.0 THD + N = 10% 0.8 THD + N = 1% 0.6 1.0 3.5 4.0 4.5 5.0 Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 6 dB 0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 24. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, Gain = 12 dB 3.5 3.5 f = 1kHz GAIN = 6dB RL = 4Ω + 15µH 3.0 f = 1kHz GAIN = 12dB RL = 4Ω + 15µH 3.0 OUTPUT POWER (W) 2.5 2.0 THD + N = 10% 1.5 THD + N = 1% 1.0 2.5 2.0 THD + N = 10% 1.5 THD + N = 1% 1.0 0.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 22. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 6 dB 100 0 2.5 09824-023 0 2.5 3.0 100 VDD = 2.5V 5.0 VDD = 2.5V 80 VDD = 5V VDD = 3.6V 4.5 VDD = 3.6V 90 80 4.0 Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, Gain = 12 dB 90 70 EFFICIENCY (%) 70 3.5 SUPPLY VOLTAGE (V) 09824-024 0.5 60 50 40 30 VDD = 5V 60 50 40 30 20 RL = 8Ω + 33µH GAIN = 6dB 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 RL = 4Ω + 15µH GAIN = 6dB 10 2.0 OUTPUT POWER (W) 09824-025 10 Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 6 dB 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 OUTPUT POWER (W) Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 6 dB Rev. 0 | Page 10 of 16 09824-026 20 0 THD + N = 1% 0.6 0.2 3.0 THD + N = 10% 0.8 0.4 SUPPLY VOLTAGE (V) OUTPUT POWER (W) 1.2 0.2 0 2.5 EFFICIENCY (%) 1.4 0.4 09824-021 OUTPUT POWER (W) 1.6 f = 1kHz GAIN = 12dB RL = 8Ω + 33µH 1.8 09824-022 2.0 SSM2377 500 600 RL = 8Ω + 33µH GAIN = 6dB 450 RL = 4Ω + 15µH GAIN = 6dB VDD = 5V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 400 VDD = 3.6V 350 300 VDD = 2.5V 250 200 150 100 VDD = 5V VDD = 3.6V 500 VDD = 2.5V 400 300 200 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER (W) 0 –10 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 VDD = 5V RL = 8Ω + 33µH –20 –30 –30 –40 PSRR (dB) GAIN = 12dB –50 –60 GAIN = 6dB –40 –50 –60 –70 –70 –80 GAIN = 6dB GAIN = 12dB –80 –90 100 1k 10k –90 10 09824-029 –100 10 100k FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency 09824-030 CMRR (dB) 0.6 0 VDD = 5V RL = 8Ω + 33µH –20 Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency 7 7 6 SD INPUT SD INPUT OUTPUT 6 5 5 VOLTAGE (V) 4 3 2 OUTPUT 4 3 2 1 1 0 –4 0 4 8 12 16 20 24 TIME (ms) 28 32 36 09824-031 VOLTAGE (V) 0.4 Figure 30. Supply Current vs. Output Power into 4 Ω, Gain = 6 dB 0 –1 –8 0.2 OUTPUT POWER (W) Figure 27. Supply Current vs. Output Power into 8 Ω, Gain = 6 dB –10 0 Figure 29. Turn-On Response 0 –50 –30 –10 10 30 TIME (µs) Figure 32. Turn-Off Response Rev. 0 | Page 11 of 16 50 70 09824-032 0 09824-027 0 09824-028 50 SSM2377 TYPICAL APPLICATION CIRCUITS POWER SUPPLY 2.5V TO 5.5V 10µF 0.1µF SSM2377 22nF AUDIO IN– IN+ AUDIO IN+ 22nF SHUTDOWN VDD 80kΩ OUT+ MODULATOR (Σ-Δ) 80kΩ IN– BIAS SD INTERNAL OSCILLATOR POP/CLICK AND EMI SUPPRESSION OUT– GND 09824-033 GAIN FET DRIVER GAIN SELECT GAIN = 6dB OR 12dB Figure 33. Monaural Differential Input Configuration POWER SUPPLY 2.5V TO 5.5V 10µF 0.1µF SSM2377 22nF AUDIO IN– IN+ 22nF SHUTDOWN VDD 80kΩ OUT+ MODULATOR (Σ-Δ) 80kΩ IN– BIAS SD INTERNAL OSCILLATOR POP/CLICK AND EMI SUPPRESSION OUT– GND 09824-034 GAIN FET DRIVER GAIN SELECT GAIN = 6dB OR 12dB Figure 34. Monaural Single-Ended Input Configuration Rev. 0 | Page 12 of 16 SSM2377 THEORY OF OPERATION OVERVIEW EMI NOISE The SSM2377 mono Class-D audio amplifier features a filterless modulation scheme that greatly reduces the external component count, conserving board space and, thus, reducing system cost. The SSM2377 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. The SSM2377 uses a proprietary modulation and spread-spectrum technology to minimize EMI emissions from the device. For applications that have difficulty passing FCC Class B emission tests or experience antenna and RF sensitivity problems, the ultralow EMI architecture of the SSM2377 significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. Figure 35 shows the low radiated emissions from the SSM2377 due to its ultralow EMI architecture. + HORIZONTAL POLARIZATION 30 20 VERTICAL POLARIZATION 10 930 09824-035 FREQUENCY (MHz) 1000 830 730 630 530 430 330 0 The SSM2377 also integrates overcurrent and overtemperature protection. Figure 35. EMI Emissions from the SSM2377 The measurements for Figure 35 were taken in an FCC-certified EMI laboratory with a 1 kHz input signal, producing 1.0 W of output power into an 8 Ω load from a 5.0 V supply. The SSM2377 passed FCC Class B limits with 50 cm, unshielded twisted pair speaker cable. Note that reducing the power supply voltage greatly reduces radiated emissions. GAIN SELECTION The preset gain of the SSM2377 can be set to 6 dB or 12 dB using the GAIN pin, as shown in Table 5. Table 5. GAIN Pin Function Description Gain Setting (dB) 6 12 + + 40 230 • FCC CLASS B LIMIT + 130 • Σ-Δ modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing EMI emissions that might otherwise be radiated by speakers and long cable traces. Due to the inherent spread-spectrum nature of Σ-Δ modulation, the need for oscillator synchronization is eliminated for designs that incorporate multiple SSM2377 amplifiers. 50 30 • 60 ELECTRIC FIELD STRENGTH (dBµV/m) Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2377 uses Σ-Δ modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. GAIN Pin Configuration Tie to VDD Tie to GND OUTPUT MODULATION DESCRIPTION POP-AND-CLICK SUPPRESSION Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audible pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. The SSM2377 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation from the SD control pin. The SSM2377 uses three-level, Σ-Δ output modulation. Each output can swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. Due to the constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, Σ-Δ output modulation. This feature ensures that the current flowing through the inductive load is small. Rev. 0 | Page 13 of 16 SSM2377 When the user wants to send an input signal, an output pulse (OUT+ and OUT−) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 36 depicts three-level, Σ-Δ output modulation with and without input stimulus. OUTPUT = 0V OUT+ +5V 0V +5V OUT– 0V +5V VOUT 0V OUTPUT > 0V +5V 0V +5V OUT– 0V +5V VOUT 0V OUT+ OUT– VOUT INPUT CAPACITOR SELECTION +5V 0V +5V 0V 0V –5V 09824-037 OUTPUT < 0V Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be directly beneath the analog power plane, and, similarly, the digital ground plane should be directly beneath the digital power plane. There should be no overlap between the analog and digital ground planes or between the analog and digital power planes. –5V OUT+ In addition, good PCB layout isolates critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Figure 36. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. The SSM2377 does not require input coupling capacitors if the input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If highpass filtering is needed at the input, the input capacitor (CIN) and the input impedance of the SSM2377 form a high-pass filter with a corner frequency determined by the following equation: fC = 1/(2π × 80 kΩ × CIN) The input capacitor value and the dielectric material can significantly affect the performance of the circuit. Not using input capacitors can generate a large dc output offset voltage and degrade the dc PSRR performance. POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 μF. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 μF capacitor as close as possible to the VDD pins of the device. Placing the decoupling capacitors as close as possible to the SSM2377 helps to maintain efficient performance. Rev. 0 | Page 14 of 16 SSM2377 OUTLINE DIMENSIONS 1.280 1.240 SQ 1.200 3 2 1 A BALL A1 IDENTIFIER 0.80 REF B C 0.40 REF TOP VIEW (BALL SIDE DOWN) 0.645 0.600 0.555 0.415 0.400 0.385 END VIEW 0.80 REF BOTTOM VIEW (BALL SIDE UP) SEATING PLANE 0.300 0.260 0.220 0.230 0.200 0.170 09-23-2010-A COPLANARITY 0.05 Figure 37. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 SSM2377ACBZ-RL SSM2377ACBZ-R7 EVAL-SSM2377Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. This package option is halide free. Rev. 0 | Page 15 of 16 Package Option 2 CB-9-4 CB-9-4 Branding Y48 Y48 SSM2377 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09824-0-5/11(0) Rev. 0 | Page 16 of 16