SPT9689 DUAL ULTRAFAST VOLTAGE COMPARATOR TECHNICAL DATA FEBRUARY 20, 2001 FEATURES APPLICATIONS • • • • • • • • • • • • • • 650 ps propagation delay 100 ps propagation delay variation 70 dB CMRR Low feedthrough and crosstalk Differential latch control ECL compatible Automated test equipment High-speed instrumentation Window comparators High-speed timing Line receivers High-speed triggers Threshold detection Peak detection GENERAL DESCRIPTION The SPT9689 is a Subnanosecond monolithic dual comparator. The propagation delay variation is less than 100 ps from 5 to 50 mV input overdrive voltage. The input slew rate is 10 V/ns. The device utilizes a high precision differential input stage with a common-mode range of –2.5 V to +4.0 V. ECL-compatible complementary digital outputs are capable of driving 50 Ω terminated transmission lines and providing 30 mA output drive. The SPT9689 is pin compatible with the SPT9687. It is available in 20-lead PLCC and 20-contact LCC packages over the industrial temperature range. The SPT9689 is also available in die form. BLOCK DIAGRAM INVERTING INPUT LATCH ENABLE NONINVERTING INPUT + A Q OUTPUT LATCH ENABLE Q OUTPUT VEE VCC GNDB GNDA Q OUTPUT Q OUTPUT B LATCH ENABLE INVERTING INPUT + LATCH ENABLE NONINVERTING INPUT ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Positive Supply Voltage (VCC to GND) .... –0.5 to +6.0 V Negative Supply Voltage (VEE to GND) .. –6.0 to +0.5 V Ground Voltage Differential .................... –0.5 to +0.5 V Input Voltages Input Common Mode Voltage ................. –4.0 to +5.0 V Differential Input Voltage ........................ –3.0 to +3.0 V Input Voltage, Latch Controls .................... VEE to 0.5 V Output Output Current ................................................... 30 mA Temperature Operating Temperature, ambient ............ –40 to +85 °C junction ..................... +150 °C Lead Temperature, (soldering 60 seconds) ..... +300 °C Storage Temperature ............................ –65 to +150 °C Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS T A = +25 °C, VCC = +5.0 V, VEE =–5.20 V, RL = 50 Ohm to –2 V, unless otherwise specified. PARAMETERS DC CHARACTERISTICS Input Offset Voltage Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Input Offset Current Input Offset Current Positive Supply Current Negative Supply Current Positive Supply Voltage, VCC Negative Supply Voltage, VEE Input Common Mode Range Latch Enable Common Mode Range Open Loop Gain Differential Input Resistance Input Capacitance Power Supply Sensitivity Common Mode Rejection Ratio Power Dissipation Power Dissipation Output High Level Output Low Level AC CHARACTERISTICS Propagation Delay Latch Set-up Time Latch to Output Delay Latch Pulse Width Latch Hold Time Rise Time Fall Time Slew Rate Bandwidth 1RS = Source impedance TEST CONDITIONS VIN, CM=0, RS=0 Ohms1 VIN, CM=0, RS=0 Ohms1 TMIN<TA<TMAX TMIN<TA<TMAX TMIN<TA<TMAX Dual Dual VCM=–2.5 to +4.0 Dual, Without Load Dual, With Load ECL 50 Ohms to –2 V ECL 50 Ohms to –2 V 20 mV O.D. 250 mV O.D. 20% to 80% 20% to 80% –3 dB TEST LEVEL MIN I –10 ±3.0 10 –25 ±12 25 mV IV V I IV I IV I I IV IV V –15 ±4.5 15 10 ±8 ±25 ±12 ±38 ±1.0 ±3.0 ±2.0 ±5.0 18 30 40 55 5.0 5.25 –5.2 –5.45 +4.0 –30 30 4.75 –4.95 –2.5 ±15 40 ±8 ±12 ±2.0 ±4.0 18 40 5.0 –5.2 mV µV/°C µA µA µA µA mA mA V V V 0 –2.0 IV V V V V V I I I I IV V V V V V V V V 4.75 –4.95 –2.5 SPT9689A TYP MAX –2.0 66 500 0.6 70 70 350 400 –1.00 –1.95 650 150 500 500 0 180 80 10 900 425 550 –.81 –1.54 850 300 600 MIN SPT9689B TYP MAX ±25 ±38 ±5.0 ±7.0 35 60 5.25 –5.45 +4.0 0 66 500 0.6 70 70 350 400 –1.00 –1.95 750 150 500 500 0 180 80 10 900 475 550 –.81 –1.54 950 300 600 UNITS V dB kΩ pF dB dB mW mW V V ps ps ps ps ps ps ps V/ns MHz SPT9689 2 2/20/01 LEVEL TEST LEVEL CODES All electrical characteristics are subject to the following conditions: I II All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. TIMING INFORMATION falling edge for the comparator to accept data. After tH, the output ignores the input status until the latch is strobed again. A minimum latch pulse width of tpL is needed for strobe operation, and the output transitions occur after a time of tpLOH or tpLOL. The timing diagram for the comparator is shown in figure 1. If LE is high and LE low in the SPT9689, the comparator tracks the input difference voltage. When LE is driven low and LE high, the comparator outputs are latched into their existing logic states. The set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. Input signals occurring before tS will be detected and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected. The leading edge of the input signal (which consists of a 20 mV overdrive voltage) changes the comparator output after a time of tpdL or tpdH (Q or Q). The input signal must be maintained for a time tS (set-up time) before the LE falling edge and LE rising edge and held for time tH after the Figure 1 – Timing Diagram Latch Enable 50% Latch Enable tH tpL tS Differential Input Voltage VREF ± VOS VOD t pLOH t pdL Output Q 50% 50% Output Q t pdH t pLOL VIN+=100 mV (p-p), VOD=20 mV SPT9689 3 2/20/01 tpLOL LATCH ENABLE TO OUTPUT LOW DELAY – the propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output HIGH to LOW transition SWITCHING TERMS (Refer to figure 1) tpdH INPUT TO OUTPUT HIGH DELAY – the propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output LOW to HIGH transition tpdL INPUT TO OUTPUT LOW DELAY – the propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output HIGH to LOW transition tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY – the propagation delay measured from the 50% point of the Latch Enable signal LOW to HIGH transition to the 50% point of an output LOW to HIGH transition VOD VOLTAGE OVERDRIVE – the difference between the differential input and reference input voltages tH MINIMUM HOLD TIME – the minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs tpL MINIMUM LATCH ENABLE PULSE WIDTH – the minimum time that the Latch Enable signal must be HIGH in order to acquire an input signal change tS MINIMUM SET-UP TIME – the minimum time before the negative transition of the Latch Enable signal that an input signal change must be present in order to be acquired and held at the outputs GENERAL INFORMATION The negative common mode voltage is –2.5 V. The positive common mode voltage is +4.0 V. The SPT9689 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has differential analog inputs and complementary logic outputs compatible with ECL systems. The output stage is adequate for driving terminated 50 ohm transmission lines. The dual comparators share the same VCC and VEE connections but have separate grounds for each comparator to achieve high crosstalk rejection. The SPT9689 has a complementary latch enable control for each comparator. Both should be driven by standard ECL logic levels. Figure 2 – Internal Function Diagram Q VIN + VIN PRE AMP ECL OUT LATCH Q REF 1 VEE REF 2 VCC CLK BUF GND LE LE SPT9689 4 2/20/01 TYPICAL PERFORMANCE CHARACTERISTICS PROPAGATION DELAY VS OVERDRIVE VOLTAGE RISE AND FALL OF OUTPUTS VS TIME CROSSOVER 800 .90 1.10 OUTPUT RISE AND FALL (V) PROPAGATION DELAY TIME (ps) 750 700 650 600 1.30 1.50 1.70 550 1.90 500 0 20 40 60 OVERDRIVE (mV) 80 400 100 500 800 900 FALL TIME VS TEMPERATURE 260 280 220 FALL TME (ps) 240 200 180 140 160 100 120 60 80 -50 0 +50 +100 50 +150 0 +50 +100 +150 TEMPERATURE (°C) TEMPERATURE (°C) HYSTERESIS VS DLATCH INPUT BIAS CURRENT VS COMMON MODE VOLTAGE 11 20 9 INPUT BIAS CURRENT (µA) 16 7 HYSTERESIS (mV) 700 TIME (ps) RISE TIME VS TEMPERATURE RISE TIME (ps) 600 5 3 C 55 ° T=- 12 +25 T= °C 8 C 5° +12 T= 4 1 0 0 10 20 30 40 50 3.0 DLATCH = VLE VLE (mV) 2.0 1.0 0.0 +1.0 +2.0 +3.0 +4.0 +5.0 COMMON MODE VOLTAGE (V) SPT9689 5 2/20/01 TYPICAL INTERFACE CIRCUIT to decrease parasitic feedback. If the output board traces are longer than approximately half an inch, microstripline techniques must be employed to prevent ringing on the output waveform. Also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. Both supply voltage pins should be decoupled with high-frequency capacitors as close to the device as possible. All ground pins and no connects should be soldered to a common ground plane to further improve noise immunity. If using the SPT9689 as a single comparator, the outputs of the inactive comparator can be grounded, left open, or terminated with 50 ohms to –2 V. All outputs on the active comparator, whether used or unused, should have identical terminations to minimize ground current switching transients. The typical interface circuit using the comparator is shown in figure 3. Although it needs few external components and is easy to apply, there are several conditions that should be noted to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines. Since the SPT9689 comparator is a very high-frequency and high-gain device, certain layout rules must be followed to avoid oscillations. The comparator should be soldered to the board with component lead lengths kept as short as possible. A ground plane should be used while the input impedance to the part is kept as low as possible Figure 4 – SPT9689 Typical Interface Circuit with Hysteresis Figure 3 – SPT9689 Typical Interface Circuit +5.0 V 2 V +5.0 V 0 to 200 W ECL 10 µF 0.1 µF 100 pF +VCC VIN + VIN LE LE Q Output GND Q Output VEE VREF + VREF RL 100 pF 100 pF 0.1 µF 10 µF 100 W +VCC LE LE Q Output GND Q Output VEE 50 W 0.1 µF 1.3 V 10 µF 0.1 µF 100 pF RL 50 W 100 pF RL 10 µF 50 W 0.1 µF 10 µF 100 pF 0.1 µF 10 µF RL 50 W 10 F 10 µF 5.2 V 2 V 5.2 V NOTES: 2 V NOTES: Denotes ground plane. Ferrite bead. Fair Rite Part # 2643001501. Denotes ground plane. All resistors are chip type 1%. Ferrite bead. Fair Rite Part # 2643001501. 0.1 µF and 100 pF capacitors are chip type mounted as close All resistors are chip type 1%. to the pins as possible. 0.1 µF and 100 pF capacitors are chip type mounted 10 µF tant capacitors have lead lengths <0.25" long. as close to the pins as possible. Represents line termination. 10 µF tant capacitors have lead lengths <0.25" long. Represents line termination. SPT9689 6 2/20/01 PACKAGE OUTLINES 20-Contact Leadless Chip Carrier (LCC) H A INCHES SYMBOL A B C D E F G H G B Bottom View Pin 1 C F MIN MAX .040 typ .050 typ 0.045 0.345 0.054 0.055 0.360 0.066 .020 typ 0.022 0.028 0.075 MILLIMETERS MIN MAX 1.02 typ 1.27 typ 1.14 1.40 8.76 9.14 1.37 1.68 0.51 typ 0.56 0.71 1.91 D E 20-Lead Plastic Leadless Chip Carrier (PLCC) A G INCHES SYMBOL A B C D E F G H I J K L M N O B Pin 1 N TOP VIEW M O E F L C D H I J K Pin 1 MIN MAX .045 typ .045 typ 0.350 0.385 0.350 0.385 0.042 0.165 0.085 0.025 0.015 0.026 0.013 0.290 0.356 0.395 0.356 0.395 0.056 0.180 0.110 0.040 0.025 0.032 0.021 0.050 0.330 MILLIMETERS MIN MAX 1.14 typ 1.14 typ 8.89 9.04 9.78 10.03 8.89 9.04 9.78 10.03 1.07 1.42 4.19 4.57 2.16 2.79 0.64 1.02 0.38 0.64 0.66 0.81 0.33 0.53 1.27 7.37 8.38 BOTTOM VIEW SPT9689 7 2/20/01 PIN ASSIGNMENTS PIN FUNCTIONS QA QA N/C QB QB 3 2 1 20 FUNCTION QA Output A QA Inverted Output A 18 GNDB GNDA Ground A LEA Latch Enable A 17 LEB LEA Inverted Latch Enable A 16 N/C VEE Negative Supply Voltage –INA Inverting Input A 15 LEB +INA Noninverting Input A 14 VCC +INB Noninverting Input B –INB Inverting Input B VCC Positive Supply Voltage LEB Latch Enabled B LEB Inverted Latch Enable B GNDB Ground B QB Output B QB Inverted Output B 19 GNDA 4 LEA 5 TOP VIEW N/C 6 NAME LEA 7 VEE 8 9 10 11 12 13 INA +INA N/C +INB INB LCC/PLCC ORDERING INFORMATION PART NUMBER INPUT OFFSET TEMPERATURE RANGE PACKAGE TYPE SPT9689AIC 10 mV –40 to +85 °C 20C LCC SPT9689BIC 25 mV –40 to +85 °C 20C LCC SPT9689AIP 10 mV –40 to +85 °C 20L PLCC SPT9689BIP 25 mV –40 to +85 °C 20L PLCC SPT9689ACU +25 °C Die* SPT9689BCU +25 °C Die* *Please see the die specification for guaranteed electrical performance. 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A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com © Copyright 2002 Fairchild Semiconductor Corporation SPT9689 8 2/20/01