CADEKA SPT9691SCC

SPT9691
WIDE INPUT VOLTAGE, JFET COMPARATOR
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
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Common Mode Range -4.0 to +8.0 V
Low Input Bias Current <100 pA
Propagation Delay 2.5 ns (max)
Low Offset ±25 mV
Low Feedthrough and Crosstalk
Differential Latch Control
Automated Test Equipment
High-Speed Instrumentation
Window Comparators
High-Speed Timing
Line Receivers
High-Speed Triggers
Threshold Detection
Peak Detection
GENERAL DESCRIPTION
The SPT9691 is a high-speed, wide common mode voltage,
JFET input, dual comparator. It is designed for applications
that measure critical timing parameters in which wide common mode input voltages of -4.0 to +8.0 V are required.
Propagation delays are constant for overdrives greater than
200 mV.
JFET inputs reduce the input bias currents to the nanoamp
level, eliminating the need for input drivers and buffers in
most applications. The device has differential analog inputs
and complementary logic outputs compatible with ECL systems. Each comparator has a complementary latch enable
control that can be driven by standard ECL logic.
The SPT9691 is available in 20-lead PLCC, 20-lead plastic
DIP and 20-contact LCC packages over the commercial
temperature range. It is also available in die form.
BLOCK DIAGRAM
QA
QB
QA
QB
GNDA
GNDB
LEA
LE B
LEA
LE B
DVEE(A)
A
B
DV EE(B)
AVEE(A)
AV EE (B)
AVCC(A)
AVCC (B)
-INA
+INA
-IN B
+IN B
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltages (Measured to GND)
Positive Supply Voltage (AVCC) .............. -0.5 to +11.0 V
Negative Supply Voltage (AVEE) ............ -11.0 to +0.5 V
Negative Supply Voltage (DVEE) .............. -6.0 to +0.5 V
Input Voltages
Input Common Mode Voltage ........ DVEE-1 to +AVCC+1
Differential Input Voltage ...................... -12.0 to +12.0 V
Input Voltage, Latch Controls .................. DVEE to 0.5 V
VIN to AVCC Differential Voltage ................ -16 to +1.0 V
VIN to AVEE Differential Voltage ................ +4 to +21.0 V
Note:
Output
Output Current ....................................................... 30 mA
Temperature
Operating Temperature, ambient .................. 0 to +70 °C
junction ....................... +150 °C
Lead Temperature, (soldering 60 seconds) ........ +300 °C
Storage Temperature ................................ -65 to +150 °C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications. Application of multiple maximum rating conditions at the same time may damage
the device.
ELECTRICAL SPECIFICATIONS
T A = +25 °C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
-25
-25
0.0
0.0
+25
+25
mV
mV
V
I
50
±0.1
±10
µV/°C
nA
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage
VIN,CM=0
TMIN < TA<TMAX
I
IV
Offset Voltage Tempco
Input Bias Current
Input Bias Current
Input Offset Current
TMIN <TA<TMAX
IV
V
±2.0
±1.0
±100
Input Offset Current
Positive Supply Current (Dual)
TMIN <TA<TMAX
AVcc=10 V
V
I
±10
25
33
nA
mA
Negative Supply Current (Dual)
Negative Supply Current (Dual)
AVEE=-10.0 V
DVEE=-5.2 V
I
I
15
55
20
70
mA
mA
nA
nA
Positive Supply Voltage, AVCC
Negative Supply Voltage, AVEE
IV
IV
9.75
-9.75
10.0
-10.0
10.25
-10.25
V
V
Negative Supply Voltage, DVEE
Input Common Mode Range
IV
I
-4.95
-4.0
-5.2
-5.45
+8.0
V
V
Latch Enable
Common Mode Range
IV
-2.0
0
V
Differential Voltage Range
Open Loop Gain
I
V
Differential Input Resistance
Input Capacitance
±10
60
V
dB
LCC Package
2
1.0
GΩ
pF
PLCC Package
PDIP
1.0
2.9
pF
pF
V
Power Supply Sensitivity
Common Mode Rejection Ratio
TMIN < TA<TMAX
V
I
50
60
60
dB
dB
IV
45
55
dB
SPT9691
2
10/6/97
ELECTRICAL SPECIFICATIONS
T A = +25 °C, AVCC = +10 V, AVEE=-10.0 V, DVEE=-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
700
895
mW
DC ELECTRICAL CHARACTERISTICS
Power Dissipation
Dual
I
Output High Level
ECL 50 Ohms to -2V
I
-.98
-.70
V
Output Low Level
ECL 50 Ohms to -2V
I
-1.95
-1.65
V
AC ELECTRICAL CHARACTERISTICS
Propagation Delay1
150 mV O.D.
IV
1.5
2.0
2.5
ns
ps/ °C
Propagation Delay TEMPCO
V
2
Propagation Delay Skew (A vs B)
V
100
ps
V
200
ps
V
1.7
ns
V
0.8
ns
Latch Pulse Width
V
2
ns
Latch Hold Time
V
-1.9
ns
Propagation Delay Dispersion2
150 mV Overdrive Min.
Latch Set-up Time
Latch to Output Delay
150 mV O.D.
Rise Time
20% to 80%
V
0.4
ns
Fall Time
20% to 80%
V
0.4
ns
V
3
Slew Rate
V/ns
NOTES:
1 Valid for both high-to-low and low-to-high transitions.
2 Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
SPT9691
3
10/6/97
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q ). The input signal must be
maintained for a time ts (set-up time) before the LE falling
edge and LE rising edge and held for time tH after the falling
edge for the comparator to accept data. After tH , the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of tpL is needed for strobe operation, and the output transitions occur after a time of tpLOH or
tpLOL.
Figure 1 - Timing Diagram
Latch Enable
50%
Latch Enable
tpL
tH
tS
Differential
Input Voltage
VRef ± VOS
VOD
t pLOH
tpdL
Output Q
50%
50%
Output Q
tpLOL
tpdH
VIN +=300 mV, V
=150 mV
OD
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected
and held; those occurring after tH will not be detected. Changes between tS and tH may not be detected.
SWITCHING TERMS (Refer to figure 1)
tpdH INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output LOW to HIGH transition.
tpdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
tH
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
tpL
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
tS
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
VOD VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
SPT9691
4
10/6/97
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
(+25 °C)
INPUT OFFSET VOLTAGE VS COMMON MODE VOLTAGE
(T=+25 °C)
100
+10.0
10
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (mV)
+6.0
+2.0
-2.0
1.0
0.1
0.01
-6.0
0.001
-10.0
-4.0
-1.6
+0.8
+3.2
+5.6
+8.0
-4.0
-1.6
COMMON MODE VOLTAGE (V)
+0.8
+3.2
+5.6
+8.0
COMMON MODE VOLTAGE (V)
PROPOGATION DELAY TIME VS TEMPERATURE
PROPAGATION DELAY TIME VS OVERDRIVE (mV)
(V OD=150 mV)
3.0
PROPAGATION DELAY TIME (ns)
2.4
PROPAGATION DELAY TIME (ns)
2.2
2.0
1.8
2.8
2.6
2.4
2.2
2.0
1.6
1.8
1.4
0
0
+25
+50
+75
50
100
150
200
250
300
350
+100
OVERDRIVE (mV)
TEMPERATURE (°C)
HYSTERESIS VS ∆LATCH
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
-.90
20
-1.10
HYSTERESIS (mV)
OUTPUT RISE AND FALL (V)
15
-1.30
VIN (CM) = 0.0 V
10
-1.50
5
-1.70
0
-1.90
1.1
1.5
1.9
2.3
2.7
-20
3.5
0
20
40
60
∆LATCH = (VLE - VLE) mV
TIME (ns)
SPT9691
5
10/6/97
GENERAL INFORMATION
The SPT9691 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
The SPT9691 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL
logic levels.
A common mode voltage range of -4 V to +8 V is achieved by
a proprietary JFET input design which requires a separate
negative power supply (AVEE).
The dual comparators have separate AVCC, AVEE, DVEE, and
grounds for each comparator to achieve high crosstalk rejection. Single channel operation can be accomplished by floating all pins (including the ground and supply pins) of the
unused comparator. Power dissipation during single channel
operation is 50% of the dissipation during dual channel
operation.
Figure 2 - Internal Function Diagram
Q
+
+IN
-
- IN
PRE
AMP
LATCH
ECL
OUT
Q
REF
1
AV EE
DV EE
REF
2
VCC
CLK
BUF
GND
LE
LE
SPT9691
6
10/6/97
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several conditions that should be
noted to achieve optimal performance. The very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines.
Since the SPT9691 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid oscillations. The comparator should be soldered to the
board with component lead lengths kept as short as possible.
A ground plane should be used, while the input impedance to
the part is kept as low as possible, to decrease parasitic
feedback. If the output board traces are longer than approximately half an inch, microstripline techniques must be employed to prevent ringing on the output waveform. Also, the
microstriplines must be terminated at the far end with the
characteristic impedance of the line to prevent reflections. All
supply voltage pins should be decoupled with high frequency
capacitors as close to the device as possible. All ground pins
should be connected to the same ground plane to further
improve noise immunity and shielding. If using the SPT9691
as a single comparator, the outputs of the inactive comparator can be grounded, left open or terminated with 50 Ohms to
D1
.1 µF
Note: At no time should both inputs be allowed to float with
power applied to the device. At least one of the inputs should
be tied to a voltage within the common mode range (-4.0 to
+8.0 V) to prevent possible damage to the device. To prevent
possible latch-up during initial power up, the input voltages
should not exceed ±1 V. Additional protection diodes D3-D6
should be used on the inputs if there is the possibility of
exceeding the absolute maximum ratings of the inputs with
respect to AVCC and DVEE (1N914 or equivalent). NOTE: For
ease of implementation, all diodes (D1 - D6) can be 1N5817
(Schottky) or equivalent.
D1
D2
.1 µF
.1 µF
Inverting Input
DVEE
AVEE
.1 µF
D6
D4
+
-
D2
.1 µF
D3
D5
Noninverting Input
GND
AVCC
DVEE
Figure 4 - SPT9691 Typical Interface Circuit With
Hysteresis
D6
D4
VREF
Diode D1 connected between AVCC and GND is recommended to prevent possible damage to the device in case
the AVCC supply is disconnected. The diode should be a
1N914 or equivalent. If AVCC is disconnected with this diode
in place, there will be approximately a 6 mA current draw
from both AVEE and DVEE. Diode D2 connected between
AVEE and DVEE is necessary to avoid power supply sequence latch-up. This diode keeps AVEE (also the substrate)
less than a silicon diode drop away from the most negative
circuit potential if DVEE is powered up first. This diode should
be a 1N5817 (Schottky) or equivalent.
.1 µF
D3
VIN
AVEE
GND
AVCC
Figure 3 - SPT9691 Typical Interface Circuit
-2 V. All outputs on the active comparator, whether used or
unused, should have identical terminations to minimize
ground current switching transients.
LE
Q Output
VIN
Q Output
VREF
D5
Noninverting Input
Inverting Input
+
Q Output
-
Q Output
LE
LE
LE
RL
50 Ω
RL
50 Ω
RL
50 Ω
RL
50 Ω
-1.3 V
.1 µF
100 Ω
.1 µF
ECL
-2 V
-2 V
.1 µF
AVEE
DVEE AVCC
GND
= Represents line termination.
AVEE
DVEE AVCC
GND
-2 V
= Represents line termination.
SPT9691
7
10/6/97
PACKAGE OUTLINES
20-Lead Plastic DIP
INCHES
SYMBOL
A
B
MIN
0.014
C
D
20
F
G
H
1
0.300
0.026
MIN
0.36
.100 typ
.010 typ
E
G
MILLIMETERS
MAX
0.330
0.254
1.030
7.62
0.66
2.54
0.25
1.20 typ
0.290
0.246
1.010
MAX
30.48
7.37
6.25
25.65
8.38
6.45
26.16
H
F
E
A
D
B
C
20-Lead Plastic Leaded Chip Carrier (PLCC)
A
G
B
SYMBOL
Pin 1
N
TOP
VIEW
A
M O
F
E
L
C
D
INCHES
MIN
MAX
K
J
I
H
Pin 1
BOTTOM
VIEW
B
C
D
E
F
G
H
I
J
K
L
M
N
O
MILLIMETERS
MIN
MAX
.045 typ
0.350
0.385
0.350
0.385
0.042
0.165
0.085
0.025
0.015
0.026
0.013
0.290
0.356
0.395
0.356
0.395
0.056
0.180
0.110
0.040
0.025
0.032
0.021
0.050
0.330
1.14
8.89
9.78
8.89
9.78
1.07
4.19
2.16
0.64
0.38
0.66
0.33
7.37
9.04
10.03
9.04
10.03
1.42
4.57
2.79
1.02
0.64
0.81
0.53
1.27
8.38
SPT9691
8
10/6/97
PACKAGE OUTLINES
20-Contact Leadless Chip Carrier (LCC)
A
H
G
B
Bottom
View
SYMBOL
Pin 1
A
B
C
D
E
F
G
H
C
INCHES
MIN
MAX
0.045
0.345
0.054
0.022
.040 typ
.050 typ
0.055
0.360
0.066
.020 typ
0.028
0.075
MILLIMETERS
MIN
MAX
1.14
8.76
1.37
0.56
1.02
1.27
1.40
9.14
1.68
0.51
0.71
1.91
F
D
E
SPT9691
9
10/6/97
PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
FUNCTION
QA
Output A
QA
Inverted Output A
GNDA
Ground A
B
LE A
Inverted Latch Enable A
16 LE B
LEA
Latch Enable A
DVEE(A) 6
15 DV EE(B)
AVCC(A)
Positive Supply Voltage (+10 V)
AVEE(A) 7
14 AV EE(B)
AVEE(A)
Negative Supply Voltage (-10 V)
AVCC(A) 8
13 AVCC (B)
DVEE(A)
Negative Supply Voltage (-5.2 V)
QA 1
20 QB
QA 2
19 QB
GNDA 3
18 GNDB
LEA 4
17 LE
LEA 5
DIP/PDIP
AVCC(B)
Positive Supply Voltage (+10 V)
-INA 9
12 -IN
B
AVEE(B)
Negative Supply Voltage (-10 V)
+INA 10
11 +IN B
DVEE(B)
Negative Supply Voltage (-5.2 V)
-INA
Inverting Input A
+INA
Noninverting Input A
+INB
Noninverting Input B
-INB
Inverting Input B
LE B
Inverted Latch Enabled B
LEB
Latch Enable B
GNDB
Ground B
QB
Inverted Output B
QB
Output B
QA
3
GNDA
LEA
QA
2
QB
1
QB GNDB
20 19
18 LEB
4
17 LEB
5
TOP VIEW
LEA
6
16 DVEE(B)
LCC/PLCC
DVEE(A) 7
15 AVEE(B)
AVEE(A) 8
14 AVCC(B)
9
10
11
12
13
AVCC(A) -INA +INA +INB -INB
ORDERING INFORMATION
PART NUMBER
SPT9691SCC
SPT9691SCN
SPT9691SCP
SPT9691SCU
TEMPERATURE RANGE
0 to +70 °C
0 to +70 °C
0 to +70 °C
+25 °C
PACKAGE TYPE
20C LCC
20L Plastic DIP
20L Plastic Leaded Chip Carrier (PLCC)
Die*
*Please see the die specification for guaranteed electrical performance.
SPT9691
10
10/6/97