CMP100 HIGH-SPEED WINDOW COMPARATOR ATE PIN RECEIVER FEATURES APPLICATIONS ● PROPAGATION DELAY: 5ns max, 100mV Overdrive ● COMMON MODE INPUT RANGE: ±12V ● ATE PIN RECEIVER ● INPUT IMPEDANCE: 120kΩ || 2pF ● OUTPUTS: Latchable, 10k ECL Compatible ● COMPLETE: No External Parts Required ● TEMPERATURE RANGE: –25°C to +85°C ● PACKAGES: 16-Pin Plastic DIP, 16-Lead Plastic SOIC V REF 1 LE 1 10 11 LE 1 8 1 Q1 7 Analog In 12 V REF 2 14 6 1 2 3 15 1 ACOM 13 16 5 4 DCOM Q1 1 1 DESCRIPTION CMP100 is a high-speed dual comparator designed for use as an automatic test system pin receiver. It is also useful in a wide variety of analog threshold detector and window comparator applications. CMP100 has two reference inputs and one analog input which is common to both comparators. All inputs are attenuated by a voltage divider to provide high common mode voltage operation. The analog input attenuator is R-C tuned to optimize operation with high-speed input waveforms. The reference input attenuators are not R-C tuned. Each attenuator network is followed by a buffer amplifier ahead of the comparator circuits. V+ 9 ● WINDOW COMPARATOR ● THRESHOLD DETECTOR Q2 Q2 LE 2 LE 2 Complementary ECL output stages are capable of driving 50Ω terminated transmission lines to a –2V pull-down voltage. In addition, latch-enable inputs are provided for each comparator, allowing operation as a sampling comparator. CMP100 is available as an industrial temperature range device, –25°C to +85°C, and is packaged in a 16-pin plastic DIP and in a 16-lead plastic SOIC. V– PWR COM International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1990 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1075A Printed in U.S.A. March, 1992 SPECIFICATIONS ELECTRICAL TA = 25°C and at rated supplies: V+ = +5V, V– = –5.2V unless otherwise noted. CMP100AP, AU PARAMETER MIN TYP MAX UNITS ANALOG INPUTS Differential Input Voltage Range Common Mode Voltage Range Resistance Reference Inputs: VREF 1, VREF 2 Analog Input Capacitance, All Inputs 24 ±12 45 90 V V 60 120 2 75 150 kΩ kΩ pF 10 100 20 10 250 ±10 ±10 mV mV/V µV/°C µV/V µV/V 3.6 5 ns –1.5 50 5 V V µA µA TRANSFER CHARACTERISTICS ACCURACY Input Offset Voltage, VOS(1) Common Mode Error Voltage Offset Drift Power Supply Sensitivity of Offset: ∆VOS / ∆V+ ∆VOS / ∆V– RESPONSE TIME Propagation Delay, tPD(2, 3) 100mV Overdrive, Latch Disabled DIGITAL SIGNALS (4) (Over Specification Temperature Range) Inputs (Latch Controls) Logic Levels: VIH VIL IIH (VI = –1.1V) IIL (VI = –1.5V) Outputs (Balanced) Logic Levels: VOL (50Ω Load to –2V) VOH (50Ω Load to –2V) –1.1 –1.5 V V +5 –5.2 +5.25 –4.95 VDC VDC +30 –40 360 +40 –50 460 mA mA mW +85 +150 °C °C –1.1 POWER SUPPLY REQUIREMENTS Supply Voltage V+ V– Supply Current(5) V+ V– Power Dissipation(6) +4.75 –5.45 TEMPERATURE RANGE Specification Storage –25 –65 NOTES: (1) Defined as half the magnitude between low-to-high and high-to-low transition input voltages. (2) See section on “Measuring CMP100 Performance.” (3) See “Discussion of Specifications” for exact conditions. (4) 10k ECL compatible. (5) Maximum supply current is specified at typical supply voltages. (6) Maximum Power Dissipation is calculated with typical supply voltages and maximum currents. Note that dissipation in the output transistors from driving 50Ω ECL loads will increase the total power dissipation by about 50mW. ABSOLUTE MAXIMUM RATINGS PIN DEFINITIONS V+ to Digital Common and Power Common ....................................... +6V V– to Digital Common and Power Common ....................................... –6V (V+) – (V–) ........................................................................................... 12V Digital Inputs to Digital Common Differential ......................................................................................... ±4V Common Mode ......................................................................... V– to V+ Differential Analog Input Voltage ....................................................... ±25V Package Power Dissipation ........................................................... 750mW Storage Temperature ...................................................... –60°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C Stresses exceeding those listed above may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CMP100 2 PIN NAME DESCRIPTION 1, 15 2, 3 4 5 6, 7 8, 10 9 11 12 13 14 16 LE2, LE2 Q2, Q2 DCOM PWRCOM Q1, Q1 LE1, LE1 V+ VREF 1 Analog In ACOM VREF 2 V– LATCH or UNLATCH comparator 1 outputs ECL outputs of comparator 2 Return for comparator circuits Return for ECL output transistor currents ECL outputs of comparator 1 LATCH or UNLATCH comparator 2 outputs Positive Supply Voltage, +5V Reference Voltage for comparator 1 Analog Signal input Return for Analog In, VREF 1, VREF 2 Reference voltage for comparator 2 Negative Supply Voltage: (ECL Supply, –5.2V) MECHANICAL P Package — 16-Pin Plastic DIP A A1 B1 B P Pin 1 F L N C K H G M J D DIM A A1 B B1 C D F G H J K L M N P INCHES MIN MAX .740 .800 .725 .785 .230 .290 .200 .250 .120 .200 .015 .023 .030 .070 .100 BASIC 0.20 .050 .008 .015 .070 .150 .300 BASIC 0° 15° .010 .030 .025 .050 MILLIMETERS MIN MAX 18.80 20.32 18.42 19.94 5.85 7.38 5.09 6.36 3.05 5.09 0.38 0.59 0.76 1.78 2.54 BASIC 0.51 1.27 0.20 0.38 1.78 3.82 7.63 BASIC 0° 15° 0.25 0.76 0.64 1.27 NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. DIM A A1 B B1 C D G H J L M N INCHES MIN MAX .400 .416 .388 .412 .286 .302 .268 .286 .093 .109 .015 .020 .050 BASIC .022 .038 .008 .012 .391 .421 5° TYP .000 .012 MILLIMETERS MIN MAX 10.16 10.57 9.86 10.46 7.26 7.67 6.81 7.26 2.36 2.77 0.38 0.51 1.27 BASIC 0.56 0.97 0.20 0.30 9.93 10.69 5° TYP 0.00 0.30 NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. U Package — 16-Pin SOIC A A1 B1 B Pin 1 Identifier H C G D M J L N ORDERING INFORMATION MODEL CMP100AP CMP100AU PACKAGE 16-Pin DIP 16-Lead SOIC The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 CMP100 TYPICAL PERFORMANCE CURVES TA = 25°C and at rated supplies: V+ = +5V, V– = –5.2V unless otherwise noted. PROPAGATION DELAY vs OVERDRIVE PROPAGATION DELAY vs AMBIENT TEMPERATURE 5 21 V 15 50ns Propagation Delay (ns) Propagation Delay (ns) VOD 0V 18 150ns VREF 1 = V REF 2 = 0V 12 9 6 –1V → +VOD 3 4 3 2 200mV 1 50ns 150ns VREF 1 = V REF 2 = 0V –200mV → +VOD 0 0 0 100 200 300 400 500 –30 0 Overdrive (mV) POWER SUPPLY CURRENT vs AMBIENT TEMPERATURE Power Supply Current (mA) 60 40 –5.2V +5V 20 0 –30 –10 10 30 50 70 Ambient Temperature (°C) Digital Output (200mV/div) RESPONSE TO A 3ns ANALOG INPUT PULSE Q Q 400 200 0 Analog In 2.76ns –200 –400 Time (1ns/div) CMP100 30 Ambient Temperature (°C) NOTE: Propagation Delay vs Overdrive is shown for two amplitudes of input pulse: from –200mV → +VOD (0.2nV/ns slew rate) and –1V → +VOD (1V/ns slew rate). For an inverse input waveform: from +1V → –VOD and from +200mV → –VOD, propagation delays identical to those above are produced. Analog Input (mV) 100mV 0V 4 90 60 90 TYPICAL PERFORMANCE CURVES (CONT) TA = 25°C and at rated supplies: V+ = +5V, V– = –5.2V unless otherwise noted. Digital Output (200mV/div) RESPONSE TO A 2ns LATCH ENABLE PULSE Analog Input (mV) 400 Q Q t DLOL 200 Analog In 0 –200 LE –400 Time (5ns/div) Digital Output (200mV/div) SETUP TIME, t S Q Q Analog Input (mV) 400 200 Analog In 0 –200 tS LE –400 Time (2ns/div) Digital Output (200mV/div) CAPTURING A NARROW ANALOG PULSE 3.5ns Q Q Analog Input (mV) 400 200 0 Analog In –200 LE –400 Time (2ns/div) 5 CMP100 DISCUSSION OF SPECIFICATIONS The propagation delay of the CMP100 is virtually identical for negative going and positive going analog input edges. Differential Propagation Delay (Skew), tDIFF tDIFF is the difference in propagation delay from one comparator to another. The skew between each half of one CMP100 is no greater than 200ps. ANALOG INPUT Offset Voltage, VOS The value of the the comparison threshold for VREF 1 or VREF 2 = 0V. VOS and maximum drift vs temperature of VOS are guaranteed. Propagation Delay Dispersion Propagation Delay Dispersion is the variation in propagation delay versus input overdrive. Note that propagation delay may also be a function of input slew rate and of the previous level. Common Mode Error As VREF varies over its range, there is a small gain error which manifests itself as a change in the comparison level. Common mode error drifts typically –15µV/oC. The input waveform for the propagation delay specification is illustrated in the first typical performance curve, Propagation Delay vs Overdrive. The Propagation Delay listed in the Electrical Specifications table is specified using an input waveform with 100mV overdrive, a previous level of –200mV and a slew rate of 200V/µs. A typical propagation delay curve is also shown for a previous level of –1V. The outputs are not latched for this specification. DYNAMIC PERFORMANCE Figure 1 illustrates the following analog and logic performance definitions. Input to Output High Propagation Delay, tPDH tPDH is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (Q output) Low-to-High transition. Output logic is not latched for this definition. Overdrive Overdrive is the voltage by which the input exceeds VREF ±VOS. Input to Output Low Propagation Delay, tPDL tPDL is the propagation delay measured from the time the input signal crosses the input offset voltage to the 50% point of an output (Q output) High-to-Low transition. Output logic is not latched for this definition. Minimum Set-Up Time, tS tS is the minimum time before the positive transition of the Latch Enable (LE) that an analog input signal change must be present in order to be acquired and held at the outputs. t PW LE 1 LE 1 t LDOL Q1 Q1 t PDH V REF 1 tS tH Analog In 0V V REF 2 t PDL Q2 Q2 t LDOH LE 2 LE 2 FIGURE 1. Analog and Logic Timing Definitions. CMP100 6 The tS performance of CMP100 is illustrated in the Typical Performance Curves. THE LATCH FUNCTION The latch function is used for sampling the state of the outputs and holding them until the output can be processed. Minimum Hold Time, tH tH is the minimum time after the positive transition of the Latch Enable (LE) that an analog input signal must remain unchanged in order to be acquired and held at the outputs. tH = 0 for CMP100. Figure 1 shows a timing diagram for differential input latch enable controls, LE and LE. The latches of the CMP100 are transparent type latches. If LE is Low (LE is High), the Q outputs indicate the sign of the input difference voltage. When LE goes High (LE Low), the comparator outputs are held at the current state. LOGIC PERFORMANCE DEFINITIONS Latch Enable to Output High Delay, tDLOH tDLOH is the propagation delay of latch logic circuits measured from the 50% point of the Latch Enable signal (LE) Highto-Low transition to the 50% point of an output (Q) Low-toHigh transition. When the analog input signal passes through the reference level, the comparator output Q changes, after a time of tPDH or tPDL. However, if the output is to be latched, the input signal must have crossed the threshold for a time tS (set-up time) before the rising edge of LE occurs in order to capture the correct output state. On the other hand, in order to capture a correct output state just before it changes, it is necessary to maintain that output state for tH, (hold time) after the rising edge of LE. tH = 0 for CMP100. Latch Enable to Output Low Delay, tDLOL tDLOL is the propagation delay of latch logic circuits measured from the 50% point of the Latch Enable signal High-toLow transition to the 50% point of an output (Q) High-toLow transition. A minimum latch pulse width of tPW is needed to capture the state of narrow pulses. See the Typical Performance Curves for an example of sampling a narrow pulse. Minimum Latch Enable Pulse Width, tPW tPW is the minimum time that the Latch Enable (LE) must be High in order to acquire and hold an input signal change. 10k ECL LOGIC If the latching function is not used, the Latch Enable inputs (LE1 and LE2) should be returned to an ECL High voltage (–0.8V) or to Digital Common (0V). LE1 and LE2 should be returned to an ECL Low level (–1.8V), to an ECL bias voltage (–1.3V) or to the –2V 50Ω load pull-down power supply. Connecting an ECL input to –5.2V may create a marginal transistor emitter-base breakdown situation over the ambient temperature range and is not recommended. The actual timing performance of CMP100 is illustrated in the Typical Performance Curves. OPERATING CONSIDERATIONS INPUT VOLTAGE Input reference voltages VREF 1 and VREF 2 may vary from –12V to +12V. The frequency-compensated analog input network can also swing from –12V to +12V. If a single (non-differential) ECL logic input is used, connect the complementary input to an ECL bias voltage (–1.3V). Care must be taken to be sure that the Maximum Differential Input Voltage is not exceeded. That is, the voltage between Analog In and VREF 1 or between Analog In and VREF 2 must not exceed ±25V. If this voltage is exceeded by 1 or 2 volts, even momentarily, emitter-base voltage breakdown of the input transistors will occur and cause a permanent shift of the offset voltage, VOS, to an out-of-spec value. However, the CMP100 will continue to function and will not be destroyed. 100k ECL LOGIC The negative power supply, V–, of the CMP100 can be operated at –4.5V. The common mode input range of the analog and reference inputs will be reduced to +12V to –7.5V. Output levels are not affected by changing the V– power supply voltage to –4.5V. Input voltages to the CMP100 of uncontrolled magnitude may occur during system power-up. Take care to assure that the Absolute Maximum Differential Input Voltage is not exceeded during power-up. TTL INPUTS The operating common mode range of a logic input is –2V to +2V. Thus one can bias the logic inputs to use them with TTL inputs if the High input level is maintained below +2V. In this case, the complementary logic input should be biased at the TTL threshold of +1.4V. DRIVING SOURCE IMPEDANCE An apparent slow response of the CMP100 may be due a combination of high source impedance and stray capacitance to ground at the analog input. An R-C combination of 1kΩ source resistance and 10pF to ground results in a 10ns time constant—more than double the typical response time of the CMP100. LEVEL SHIFTING ECL to TTL The ECL outputs can be translated to TTL using a Motorola MC10125 Quad ECL-TTL translator. The logic delay tDLOH and tDLOL and the propagation delay tPDL and tPDH will be increased by the delay of the translator. 7 CMP100 INSTALLATION solution for preserving dynamic performance and reducing noise coupling into sensitive circuits. TERMINATING ECL OUTPUTS The best performance will be achieved with the use of proper ECL terminations. Such a configuration is illustrated in Figure 3. The open-emitter outputs of the CMP100 are designed to be terminated through 50Ω resistors to –2V or any other equivalent termination. If high-speed ECL signals must be routed more than a few centimeters, MicroStrip or StripLine techniques may be required to insure proper transition times and prevent output ringing. When passing power through a connector, use every available spare pin for making power supply return connections, and use some of the pins as a Faraday shield to separate the Analog and Digital Common lines. Power Supply Returns (ACOM, DCOM and PWRCOM) For best performance, connect ACOM (pin 13) and DCOM (pin 4) to the ground plane under the comparator. PWRCOM (pin 5), which is connected to the collectors of the ECL outputs, can be returned by separate printed circuit trace but its inductance should be kept low to avoid ringing. Do not connect ACOM and DCOM together at the end of a long printed circuit trace and then run a single wire to the power supply. To use separate ACOM and DCOM return printed circuit traces, connect a 1µF to 47µF tantalum capacitor between DCOM and ACOM pins as close to the package as possible. POWER SUPPLY SELECTION Linear power supplies are preferred. Although switching power supply rms specifications may appear to indicate low noise output, voltage spikes generated by switchers may be hard to filter. Their high-frequency components may be extremely difficult to keep out of the power supply return system. If switchers must be used, their outputs must be carefully filtered and the power supply itself should be shielded and located as far away as possible from precision analog circuits. Power Supply Bypassing Every power supply line leading into the comparator must be bypassed to the Common pins. The bypass capacitor should be located as close to the comparator package as possible and tied to a solid return, preferably to the ground plane under the device. If the capacitors are not close enough to the package, DC resistance and inductance may be above acceptable levels. Use tantalum capacitors with values of from 1µF to 10µF. Parallel them with smaller ceramic PRINTED CIRCUIT LAYOUT CONSIDERATIONS Power Supply Wiring Use heavy power supply and power supply common (ground) wiring. A ground plane under the part is usually the best +5V 0.1µF V REF 1 V+ 11 From 50Ω Generator 16.6Ω LE 1 Analog In 16.6Ω 8 12 To 50Ω Scope Q1 7 6 CMP100 2 V REF 2 3 14 15 16.6Ω 1 ACOM 16 4 DCOM Q2 66.5Ω Q2 100Ω V– 100Ω PWR COM –4V 0.1µF –5.2V 0.1µF 1µF FIGURE 2. Circuit for Evaluating Analog Propagation Delay, tPDH, tPDL. CMP100 66.5Ω LE 2 LE 2 13 5 16.6Ω Q1 16.6Ω 49.9Ω 16.6Ω LE 1 9 10 16.6Ω 1µF 8 1µF To 50 Ω Scope capacitors for high frequency filtering if necessary. Electrolytic capacitors are not recommended because their high frequency response is poor. if overcompensated. If the probe ground lead is too long, the output may appear distorted and oscillatory. Use probes with short (less than one inch) ground straps or use a coaxial cable connection instead of a probe. Do not use X1 or “straight” probes. Their bandwidth is 20MHz or less and capacitive loading is high. The best method is to use 50Ω matched terminations as shown in Figures 2 and 3. Separate the Analog and Digital Signals Digital signal paths entering or leaving the layout should have minimum length to minimize crosstalk to analog wiring. Stray capacitive feedback from digital outputs to the analog input may cause the outputs to appear fuzzy well after the outputs have changed. Keep analog signals as far away as possible from digital signals. If they must cross, cross them at right angles. Coaxial cable may be necessary for analog inputs in some situations. MEASURING PROPAGATION DELAY Figure 2 shows a circuit configuration used for evaluating propagation delay. It uses 50Ω matched terminations between the instruments and the CMP100 for best signal integrity. An HP8130A Pulse Generator is used for the analog input and for the latching signals. The oscilloscope is an HP54503A 500MHz Digitizing Oscilloscope. This setup was used to generate the dynamic performance waveforms in the Typical Performance Curves section. MEASURING CMP100 PERFORMANCE USING AN OSCILLOSCOPE Oscilloscope probes should be matched to the oscilloscope. Use an oscilloscope with at least 400MHz bandwidth. MEASURING LOGIC TIMING Figure 3 shows the circuit configuration used for evaluating logic propagation delay. The logic input LE1 has been added to the circuit of Figure 2. Be sure the probe compensation is adjusted properly. Improper compensation will result in apparent overshoot and/ or ringing if undercompensated, and an apparent slow edge +5V From 50Ω Generator 0.1µF 16.6Ω 1µF 16.6Ω V REF 1 V+ 11 From 50Ω Generator 16.6Ω 16.6Ω 49.9Ω 16.6Ω LE 1 9 LE 1 10 16.6Ω To 50Ω Scope Analog In 16.6Ω 8 16.6Ω Q1 12 Q1 7 16.6Ω To 50Ω Scope 6 CMP100 49.9Ω 2 V REF 2 3 14 15 1 16 5 4 DCOM 66.5Ω LE 2 LE 2 13 66.5Ω Q2 16.6Ω ACOM Q2 100Ω V– 100Ω PWR COM –4V 0.1µF 1µF –5.2V 0.1µF 1µF FIGURE 3. Circuit for Evaluating Logic Timing. 9 CMP100 To 50 Ω Scope CMP100 APPLICATIONS WINDOW COMPARATOR Because of its high speed, the CMP100 can be used to make timing measurements on modest-speed digital or high-speed analog waveforms. When the outputs of the CMP100 are combined with a NOR gate, a true window comparator function is implemented. Refer to gate G3 of Figure 6. The output pulse width generated by an input signal passing through the reference levels can be measured. This could be for a rise-time/fall-time measurement (setting the reference levels at 10% and 90% of the signal height) of a modest speed digital waveform, or for the width (and hence the value) of an analog ramp moving between two values from an integrating type signal detector. ATE PIN RECEIVER A typical ATE pin receiver application using CMP100 is illustrated in Figure 4. The reference inputs, VREF 1 and VREF 2 are driven by D/A converters (Figure 5) while analog input is driven directly from the device under test (DUT). D/A Active Load D/A PULSE RECOVERY The window comparator function can also be used to reconstruct pulses that have been degraded. Positive and/or negative reference levels can be set up to detect both High and Low levels of the pulse. D/A Driver ATE Computer D/A A plot of the response of CMP100 to a narrow pulse with VREF1 = 0V is shown in the Typical Performance Curves section. D/A CMP100 Receiver Device Under Test DETECTING TRANSIENTS CMP100 can be connected to Detect and Hold transient occurrences above and below threshold voltages set by VREF 1 and VREF 2 as illustrated in Figure 6. The outputs of comparator 1 and comparator 2 are fed back to their LE inputs in order to self-latch their outputs. The Reset control is used to “unlock” the outputs after the transient occurrence has been read. The output NOR gate G3 combines CMP100 outputs into a single-output window comparator function. D/A Parametric Measurement Unit FIGURE 4. Typical ATE Pin Receiver Application. +VCC 2 6 +10V REF102 INA105 4 To VREFA and/or VREFB 2 5 6 3 VDD V REFA +5V +5V CD 21 4 3 1 E0 = E1 /E2 , ±0.01% DB11 18 Data Inputs DB0 DAC A DAC7802 6 2 1 23 DAC B 24 R FBA I OUTA LE 1 LE 1 10pF A1 AGND R FBB I OUTB D/A control circuitry omitted for clarity. DGND 10 8 7 11 Analog In CMP100 2 3 V REF2 14 Q1 6 12 10pF A2 12 V REF1 1 Q1 Q2 Q2 15 22 V REFB LE 2 LE 2 A 1 , A 2 are 1/2 OPA2107. FIGURE 5. Dual DAC7802 (12-bit port), DAC7801 (8-bit port) or DAC7800 (serial port) D/A Converters Supply Reference Inputs to the CMP100. For higher resolution use DAC725, dual 16-bit D/A converter. CMP100 10 WIDE-BAND AMPLIFIERS FOR ANALOG INPUT SIGNAL CONDITIONING Note that the transient being detected must remain above VREF 1 (or below VREF 2) longer than the propagation delay of the CMP100 plus the propagation delay of gates G1 and G2. In a component test application the analog input of the CMP100 is usually driven directly from the DUT output. Other applications may require a high-speed buffer or voltage gain ahead of the CMP100. Recommended wide-bandwidth amplifiers are Burr-Brown OPA603 for up to ±10V signals, or OPA620/OPA621 for very wide-band ±3V signals. A high speed instrumentation amplifier such as the Burr-Brown INA110 can be used for common mode rejection. In an application where only one polarity of transient needs to be captured, comparator 2 (not latched) can be used as the source of the Reset control signal to unlock comparator 1 based on a different threshold condition (defined by VREF 2) on the analog input signal. This connection will stretch the transient occurrence for the time the VREF 2 condition is present. +5V VREF 1 VREF 2 0.1µF V REF 1 V+ 11 1µF LE 1 9 LE 1 10 Q1 8 Analog In 12 7 G1 Q1 6 49.9Ω CMP100 3 14 G3 Q2 2 V REF 2 G2 Q2 15 ACOM 16 13 5 4 DCOM V– MC10102 LE 2 1 LE 2 133Ω –1.2V PWR COM All 49.9Ω 249Ω 0.1µF 0.1µF “1” = Reset “0” = Ready 1µF –5.2V –2V Reset FIGURE 6. CMP100 Used to Detect and Hold Transient Occurrences on the Output Pulse of a Device Under Test, or Out-ofLimits Conditions in a Process-Variable Monitoring Application. 11 CMP100