CADEKA SPT9687SIP

SPT9687
DUAL ULTRAFAST VOLTAGE COMPARATOR
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
Propagation Delay <2.3 ns
Propagation Delay Skew <300 ps
Low Power: 185 mW
Low Offset ±3 mV
Low Feedthrough and Crosstalk
Differential Latch Control
High-Speed Instrumentation, ATE
High-Speed Timing
Window Comparators
Line Receivers
A/D Conversion
Threshold Detection
GENERAL DESCRIPTION
Improvements over other sources include reduced power
consumption, reduced propagation delays, and higher input
impedance.
The SPT9687 is a dual, very high-speed monolithic comparator. It is pin compatible with, and has improved performance over Analog Device's AD9687. The SPT9687 is
designed for use in Automatic Test Equipment (ATE), highspeed instrumentation, and other high-speed comparator
applications.
The SPT9687 is available in 16-lead SOIC, 16-lead plastic
DIP, 20-lead PLCC and 20-contact LCC packages over the
industrial temperature range. It is also available in die form.
BLOCK DIAGRAM
Inverting Input
Latch Enable
Noninverting Input
+
-
Latch Enable
A
Q Output
Q Output
VEE
GNDB
VCC
GNDA
Q Output
Q Output
B
Latch Enable
Inverting Input
-
B
+
Latch Enable
Noninverting Input
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Positive Supply (VCC to GND) .................. -0.5 to +6.0 V
Negative Supply (VEE to GND) ................ -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
Output
Output Current ...................................................... 30 mA
Temperature
Operating Temperature, ambient .............. -25 to +85 °C
junction ....................... +150 °C
Lead Temperature, (soldering 60 seconds) ...... +300 °C
Storage Temperature .............................. -65 to +150 °C
Input Voltages
Input Voltage ............................................ -4.0 to +4.0 V
Differential Input Voltage .......................... -5.0 to +5.0 V
Input Voltage, Latch Controls ..................... V EE to 0.5 V
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT9687
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage
RS = 0 Ohms1
Input Offset Voltage
RS = 0 Ohms1
TMIN <TA<TMAX
Offset Voltage Tempco
Input Bias Current
Input Bias Current
TMIN <TA<TMAX
III
-3
IV
-3.5
±.5
+3
mV
+3.5
mV
µV/°C
V
4
I
6
±20
µA
IV
7
±38
µA
I
-1.0
+1.0
µA
IV
-1.5
+1.5
µA
I
-2.5
+2.5
V
Common Mode Range
IV
-2.0
0
V
Open Loop Gain
V
4000
Input Resistance
V
60
kΩ
Input Capacitance
V
3
pF
Input Offset Current
Input Offset Current
TMIN <TA<TMAX
Input Common Mode Range
Latch Enable
V/V
Input Capacitance
(LCC Package)
V
1
pF
Power Supply Sensitivity
VCC and VEE
IV
50
100
dB
IV
50
85
dB
Common Mode Rejection Ratio
Positive Supply Current
I
7
11
mA
Negative Supply Current
I
27
37
mA
Positive Supply Voltage
IV
4.75
5.0
5.25
V
Negative Supply Voltage
IV
-4.95
-5.2
-5.45
V
185
250
mW
Power Dissipation
I OUTPUT = 0 mA
I
OUTPUT LOGIC LEVELS (ECL 10 KH Compatible)
Output High
50 Ohms to -2 V
I
-.98
-.81
V
Output Low
50 Ohms to -2 V
I
-1.95
-1.63
V
AC ELECTRICAL CHARACTERISTICS2
Propagation Delay
10 mV OD
Latch Set-up Time
III
2.0
2.3
ns
IV
0.6
1
ns
SPT9687
2
3/21/97
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified.
TEST
CONDITIONS
PARAMETERS
TEST
LEVEL
MIN
SPT9687
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS2
Latch to Output Delay
50 mV OD
IV
Latch Pulse Width
V
Latch Hold Time
IV
3
ns
2
ns
0.5
ns
Rise Time
20% to 80%
V
1.2
ns
Fall Time
20% to 80%
V
1.2
ns
1RS = Source impedance.
2100 mV input step.
TEST LEVEL
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
Unless otherwise noted, all tests are pulsed
tests; therefore, TJ = TC = TA.
Figure 1 - Timing Diagram
LATCH ENABLE
50%
LATCH ENABLE
tH
tpL
tS
DIFFERENTIAL
INPUT VOLTAGE
VREF ± VOS
VOD
t pLOH
tpdL
OUTPUT Q
50%
50%
OUTPUT Q
t pdH
t pLOL
VIN+ = 100 mV (p-p), VOD = 50 mV
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected
and held; those occurring after tH will not be detected. Changes between ts and tH may not be detected.
SPT9687
3
3/21/97
SWITCHING TERMS (Refer to figure 1)
GENERAL INFORMATION
tpdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal
crosses the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.
The SPT9687 is an ultrahigh-speed dual voltage comparator. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
tpdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
The SPT9687 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL logic
levels.
The dual comparator shares the same VCC and VEE connections but have separate grounds for each comparator to
achieve high crosstalk rejection.
tpLOH LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.
Figure 2 - Internal Functional Diagram
VOD VOLTAGE OVERDRIVE - The difference between
the differential input and the reference voltages.
Q
+
VIN
tpLOL LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW transition.
tH
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
tS
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
ECL
OUT
LATCH
Q
REF
1
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
tpL
-
VIN
PRE
AMP
VEE
REF
2
VCC
CLK
BUF
GND1
LE
LE
GND2
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be met to achieve optimal performance. The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of transmission lines.
Since the SPT9687 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid spurious oscillations. The comparator should be soldered to the board with component lead lengths kept as short
as possible. A ground plane should be used, and the input
impedance to the part should be kept as low as possible to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline techniques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All supply voltage pins should be decoupled with high frequency capacitors as close to the
device as possible. All ground and N/C pins should be
connected to the same ground plane to further improve noise
immunity and shielding. If using the SPT9687 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 Ohms to -2 V. All
outputs on the active comparator, whether used or unused,
should have identical terminations to minimize ground current switching transients.
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
and LE low in the SPT9687, the comparator tracks the
input difference voltage. When LE is driven low and LE
high, the comparator outputs are latched into their existing
logic states.
The leading edge of the input signal (which consists of a
50 mV overdrive voltage) changes the comparator output
after a time of tpdL or tpdH (Q or Q ). The input signal must be
maintained for a time ts (set-up time) before the LE falling
edge and LE rising edge and held for time tH after the falling
edge for the comparator to accept data. After tH, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of tpL is needed for strobe
operation, and the output transitions occur after a time of
tpLOH or tpLOL.
Note: To ensure proper power up of the device, the input
should be kept below +1.5 V during power up.
SPT9687
4
3/21/97
Figure 3 - Typical Interface Circuit
Figure 4 - Typical Interface With Hysteresis
VCC GND VEE
VCC
GND
VEE
VO
.1 µF
VIN
Noninverting
Input
.1 µF
VIN
VIN
+
Q Output
-
Q Output
Inverting
Input
Q OUTPUT
AAA
A
AA
-
VREF
Noninverting
Input
VRef
+
Inverting
Input
LE
Q OUTPUT
RL
50 Ω
RL
50 Ω
LE
.1 µF
-2 V
RL
50 Ω
RL
50 Ω
LE
LE
300 Ω
VLE
VLE
300 Ω
-5.2 V
-5.2 V
.1 µF
0.1 µF
100 Ω
-2 V
100 Ω
ECL
= Represents line termination.
Hysteresis is obtained by applying a DC bias to the LE pin.
VLE = -1.3 V ±100 mV, VLE = -1.3 V.
Represents line termination.
Figure 5 - Equivalent Input Circuit
Figure 6 - AC Test Fixture
V +
VCC
(+5.0 V)
IN
MONITOR
GND
VCC
L1
6
SEMI
RIGID
15 µF
Q3
L3
R
C
IN
1 pF
0.1 µF
R 2
1
50
Q9
C
IN
1 pF
V +
IN
V IN
R
L2
SEMIRIGID
SEMIRIGID
-
V-
100 Ω
SEMI
RIGID
100
0.1 µF
50
0.1 µF
100
IN
V
VIN
VOUT-
50
SAMPLING
SCOPE
L2
PRE
+
OUT
0.1 µF
V
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
V
6
50
LE
7
Q5
Q4
SEMI
RIGID
100
Q
LE
Q
Q1
R
Q
DUT 4
IN
IN
6
V+
+
100
6
Q11
V
50
6
100
PRE
100 Ω
50
50
Q
2
Q
6
Q
10
8
Q
12
6
SEMI
RIGID
Q
VR1
6
SEMI
RIGID
6
SEMI
RIGID
L1
L1
6
SEMI
RIGID
V
R2
15 µF
15 µF
TANT
-
R3
V
R4
R5
R6
+
-
R7
LE
MONITOR
EE
Figure 7 - Output Circuit
R7
240 Ω
+
LE
LE
LE
MONITOR
VEE
(-5.2 V)
V pD
(-4.0 V)
Figure 8 - Test Load
Rz
R8
240 Ω
50 Ω Coax
50 Ω
Q23
Q24
Q Output
RL
100 Ω
Q Output
V1
Q21
Q22
V2
4.5 mA
RZ
100 Ω
Vpd
(-4.0 V)
SPT9687
5
3/21/97
PACKAGE OUTLINES
16-Lead Plastic DIP
SYMBOL
MIN
INCHES
MAX
A
0.300
B
C
16
G
MILLIMETERS
MIN
MAX
0.014
0.026
.100 typ
7.62
0.36
0.66
2.54
D
E
1.150
.010 typ
1.950
29.21
0.25
49.53
F
G
H
0.290
0.246
0.740
0.330
0.254
0.760
7.37
6.25
18.80
8.38
6.45
19.30
1
H
F
E
A
D
C
B
20-Contact Leadless Chip Carrier (LCC)
A
H
G
B
Bottom
View
C
SYMBOL
Pin 1
D
INCHES
MAX
A
.040 typ
B
C
D
.050 typ
0.055
0.360
E
F
G
H
F
MIN
0.045
0.345
0.054
0.022
0.066
.020 typ
0.028
0.075
MILLIMETERS
MIN
MAX
1.02
1.14
8.76
1.37
0.56
1.27
1.40
9.14
1.68
0.51
0.71
1.91
E
SPT9687
6
3/21/97
PACKAGE OUTLINES
20-Lead Plastic Leaded Chip Carrier (PLCC)
A
G
B
Pin 1
N
TOP
VIEW
M O
F
INCHES
E
SYMBOL
L
MIN
MILLIMETERS
MAX
A
MIN
.045 typ
MAX
1.14
B
K
C
D
J
I
H
Pin 1
BOTTOM
VIEW
C
D
0.350
0.385
0.356
0.395
8.89
9.78
9.04
10.03
E
0.350
0.356
8.89
9.04
F
0.385
0.395
9.78
10.03
G
H
0.042
0.165
0.056
0.180
1.07
4.19
1.42
4.57
I
0.085
0.110
2.16
2.79
J
K
L
0.025
0.015
0.026
0.040
0.025
0.032
0.64
0.38
0.66
1.02
0.64
0.81
M
N
O
0.013
0.021
0.050
0.330
0.33
0.53
1.27
8.38
0.290
7.37
16-Lead Small Outline Integrated Circuit (SOIC)
SYMBOL
MIN
INCHES
MAX
MILLIMETERS
MIN
MAX
A
0.150
0.157
3.81
3.99
0.230
0.386
.050 Typ
0.244
0.393
5.84
9.80
1.27 Typ
6.20
9.98
16
B
C
D
1
E
F
G
H
I
0.0138
0.004
0.061
0.0075
0.055
0.0192
0.0098
0.068
0.0098
0.061
0.35
0.127
1.55
0.19
1.40
0.49
0.25
1.73
0.25
1.55
A B
C
G
F
I
H
D
E
SPT9687
7
3/21/97
PIN ASSIGNMENTS
PIN FUNCTIONS
QA 1
16 QB
QA 2
15 QB
14 GNDB
GNDA 3
NAME
FUNCTION
QA
Output A
QA
Inverted Output A
LE A 4
13 LE B
LE A 5
12 LEB
GNDA
Ground A
VEE 6
11 VCC
LEA
Latch Enable A
-IN A 7
10 -INB
LE A
Inverted Latch Enable A
+IN A 8
9
+INB
VEE
Negative Supply Voltage
-INA
Inverting Input A
+INA
Non-Inverting Input A
+INB
Non-Inverting Input B
-INB
Inverting Input B
17 LE B
VCC
Positive Supply Voltage
16 N/C
LEB
Latch Enabled B
LE A 7
15 LE B
LE B
Inverted Latch Enable B
VEE 8
14 VCC
GNDB
Ground B
QB
Output B
QB
Inverted Output B
PDIP/SOIC
QA QA N/C QB Q B
3
2
1
20
19
GNDA 4
18 GND B
LE A 5
N/C
6
TOP VIEW
9
10
11
12
13
-IN A +INA N/C +IN B -IN B
LCC/PLCC
ORDERING INFORMATION
PART NUMBER
Temperature Range
PACKAGE TYPE
SPT9687SIN
-25 to +85 °C
16L PDIP
SPT9687SIP
-25 to +85 °C
20L PLCC
SPT9687SIC
-25 to +85 °C
20C LCC
SPT9687SIS
-25 to +85 °C
16L SOIC
SPT9687SCU
+25 °C
Die*
*Please see the die specification for guaranteed electrical performance.
SPT9687
8
3/21/97