Si9166 New Product Vishay Siliconix Si9166 High Frequency Programmable Topology Controller FEATURES • • • • Buck or Boost Configuration Voltage Mode Control 2.7-V to 6-V Input Voltage Range for VDD and VS Programmable PWM/PSM Control – Up to 2-MHz Switching Frequency in PWM – Synchronous Rectification in PWM – Less than 200-µA IDD in PSM • • • • Integrated UVLO and POR Integrated Soft-Start Synchronization Shutdown Current <1 µA DESCRIPTION The Si9166 is a programmable topology controller for today’s continuous changing portable electronic market. Si9166 provides flexibility of utilizing various battery configurations and chemistries such as NiCd, NiMhy, or Li+ with input voltage range of 2.7 V to 6 V. An additional flexibility is provided with topology programmability to power multiple loads such as power amplifiers, microcontrollers, or baseband logic IC’s. The converters can be programmed to be synchronous Buck or Boost topology. For ultra-high efficiency, converters are designed to operate in synchronous rectified PWM mode under full load while transforming into externally controlled pulse skipping mode (PSM) under light load. All these features are provided by the Si9166 without sacrificing system integration requirements of fitting these circuits into ever demanding smaller and smaller space. The Si9166 is capable of switching up to 2 MHz to minimize the output inductor and capacitor size in order to decrease the overall converter size. The Si9166 is available in TSSOP-16 pin package and specified to operate over the industrial temperature range of -25°C to 85°C. TYPICAL APPLICATION CIRCUIT FaxBack 408-970-5600, request 70847 www.siliconix.com S-60752—Rev. B, 05-Apr-99 1 Si9166 Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS Voltages Referenced to GND Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to 150°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C MODE, PWM/PSM, SYNC, SD, VREF, ROSC COMP, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VS + 0.3 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V Thermal Impedance (θJA) 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135°C/W Voltages Referenced to PGND Notes VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V a. Device mounted with all leads soldered or welded to PC board. DH, DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VS + 0.3 V b. Derate 7.4 mW/°C above 25°C. Peak Output Current (DH, DL) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Voltages Referenced to AGND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V Fosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 kHz to 2 MHz MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . 0 V to VDD Rosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kΩ to 300 kΩ Voltages Referenced to PGND VREF Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 µF VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V SPECIFICATIONS Limits Test Conditions Unless Otherwise Specified Parameter Symbol -25°C to 85°C 2.7 V ≤ VDD , VS ≤ 6 V Mina Typb Maxa IREF = 0A 1.268 1.3 1.332 IREF = 0, TA = 25°C 1.280 1.3 1.320 Unit Reference Output Voltage VREF Load Regulation ∆VREF Power Supply Rejection PSRR VDD = 3.3 V, -500 µA < IREF <0 V 3 mV 60 dB UVLO Under Voltage Lockout (turn-on) Hysteresis 2.3 VUVLOLH VHYS VUVLOLH - VUVLOHL 2.4 2.5 V 0.1 Soft-start Time SS time tss 6 mS Mode Logic High VIH Logic Low VIL Input Current 0.7 VDD 0.3 VDD IL -1.0 Logic High VIH 2.4 Logic Low VIL 1.0 V µA SD, SYNC, PWM/PSM Input Current S-60752—Rev. B, 05-Apr-99 2 IL 0.8 -1.0 1.0 V µA FaxBack 408-970-5600, request 70847 www.siliconix.com Si9166 Vishay Siliconix New Product SPECIFICATIONS Limits Test Conditions Unless Otherwise Specified Parameter Symbol 2.7 V ≤ VDD , VS ≤ 6 V -25°C to 85°C Mina Typb Maxa Unit Oscillator Maximum Frequency FOSC Accuracy Maximum Duty Cycle— Buck Maximum Duty Cycle— Boost SYNC Range 2 MHz Nominal 1.60 MHz, ROSC = 30 kΩ -20 20 Fsw = 2 MHz (non LDO mode) 75 85 Fsw = 2 MHz 52 65 % DMAX FSYNC/FOSC 1.2 SYNC Low Pulse Width 50 SYNC High Pulse Width 50 1.5 ns SYNC tr, tf 50 Error Amplifier Input Bias Current IBIAS Open Loop Voltage Gain AVOL FB Threshold VFB Unity Gain BW BW Output Current IEA VFB = 1.4 V -1 50 60 TA = 25°C 1.270 1.30 1.330 1.258 1.30 1.342 Source (VFB = 1.05 V), VCOMP = 0.75 V -3 1 PSRR µA dB 2 Sink (VFB = 1.55 V), VCOMP = 0.75 V Power Supply Rejection 1 V MHz -1 mA 3 60 dB Output Drive (DH and DL) Output High Voltage VOH VS = 3.3 V, IOUT = -20 mA Output Low Voltage VOL VS = 3.3 V, IOUT = 20 mA Peak Output Source ISOURCE Peak Output Sink ISINK Break-Before-Make tBBM VS = 3.3 V, DH = DL = VS/2 VS = VDD = 3.3 V 3.18 500 3.24 0.06 0.12 -750 -500 750 30 V mA ns Supply Normal Mode PSM Mode IDD Shutdown Mode VDD = 3.3 V, FOSC = 2 MHz 500 750 VDD = 3.3 V 180 250 VDD = 3.3 V, SD = 0 V µA 1 Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. FaxBack 408-970-5600, request 70847 www.siliconix.com S-60752—Rev. B, 05-Apr-99 3 Si9166 Vishay Siliconix New Product TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED) S-60752—Rev. B, 05-Apr-99 4 FaxBack 408-970-5600, request 70847 www.siliconix.com Si9166 Vishay Siliconix New Product TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED) PIN CONFIGURATION ORDERING INFORMATION Part Number Temperature Range Package Si9166BQ-T1 -25 to 85°C Tape and Reel Eval Kit Temperature Range Board Type Si9166DB -25 to 85°C Surface Mount PIN DESCRIPTION Pin Symbol 1 VS Input supply voltage for the output driver section. Input voltage range is 2.7 V to 6V Description 2 N/C Not Used 3 DH The gate drive output for the high-side p-channel MOSFET. The p-channel MOSFET is the main switch for buck topology and the synchronous rectifier for the boost topology. 4 PWM/PSM 5 SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD, or logic high. 6 GND Low power controller ground 7 VREF 1.3-V reference. Decoupled with 0.1-µF capacitor Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled. 8 FB 9 COMP Error amplifier output for external compensation network. Output voltage feedback connected to the inverting input of an error amplifier. 10 ROSC External resistor to determine the switching frequency. 11 VDD Input supply voltage for the analog circuit. Input voltage range is 2.7 V to 6 V. 12 VO Direct output voltage sense 13 PGND Power ground for output drive stage DL The gate drive output for the low-side n-channel MOSFET. The n-channel MOSFET is the synchronous rectifier for the buck topology and the main switch for the boost topology. 15 SD Shuts down the IC completely and decreases current consumed by the IC to < 1 µA. 16 MODE 14 Determines the converter topology. Connect to AGND for Buck or VDD for Boost. FaxBack 408-970-5600, request 70847 www.siliconix.com S-60752—Rev. B, 05-Apr-99 5 Si9166 Vishay Siliconix New Product FUNCTIONAL BLOCK DIAGRAM DETAIL OPERATIONAL DESCRIPTION Start-Up The UVLO circuit prevents the controller output driver and oscillator circuit from turning on, if the voltage on VDD pin is less than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is continuously powered on until the VDD voltage drops below 2.4 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal power-on-reset timer is activated while most circuitry, except the output driver, are turned on. After the POR time-out of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging the soft-start capacitor will force the converter output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchronous switch is tri-stated until the duty cycle reaches about 10%. In tri-state, the high-side p-channel MOSFET is turned off by pulling up the gate voltage (DH) to VS potential. The low-side n-channel MOSFET is turned off by pulling down the gate voltage (DL) to PGND potential. S-60752—Rev. B, 05-Apr-99 6 Note that the Si9166 will always soft start in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown The Si9166 is designed to conserve battery life by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low-level on the SD pin, current consumption of the Si9166 decreases to less than 1 µA by shutting off most of the circuits. The logic high enables the controller and starts up as described in Start-Up section above. MODE Selection The Si9166 can be programmed to operate as Buck or Boost converter. If the MODE pin is connected to AGND, it operates in buck mode. If the MODE pin is connected to VDD, it operates in boost mode. The DH gate drive output is designed to drive high-side p-channel MOSFET, acting as the main switch in buck topology and the synchronous rectifier in boost topology. The DL gate drive output is designed to drive low-side n-channel MOSFET, acting as the synchronous rectifier in buck topology and the main switch in boost topology. FaxBack 408-970-5600, request 70847 www.siliconix.com Si9166 New Product Vishay Siliconix PWM Mode Pulse Skipping Mode With PWM/PSM mode pin in logic high condition, the Si9166 operates in constant frequency (PWM) mode. As the load and line varies, switching frequency remain constant. The switching frequency is programmed by the ROSC value. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A. Therefore, the converter always operates in continuous conduction mode (CCM) if a synchronous switch is used. In CCM, transfer function of the converter remains almost constant, providing fast transient response. If the converter operates in discontinuous conduction mode (DCM), overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc/dc converter to meet the transient voltage regulation. The PWM/PSM pin is available to dynamically program the controller. If the synchronous rectifier switch is not used, the converter will operate in DCM at light load. The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter during light load (i.e. < 10 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9166 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 µA, instead of 500 µA during the PWM mode. This is accomplished by turning off most of internal control circuitry and utilizing a simple constant ontime control with feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on inductor used (1.5-µH typical), MODE pin selection and maximum load current. Therefore, with this control method, duty cycle ranging from 0 to near 100% is possible depending on whether buck or boost is chosen. In pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss and increase overall converter efficiency. The maximum duty cycle of the Si9166 can reach 100% in buck mode. The duty cycle will continue to increase as the input voltage decreases until it reaches 100%. This allows the system designers to extract the maximum stored energy from the battery. Once the controller delivers 100% duty cycle, the converter operates like a saturated linear regulator. At 100% duty cycle, synchronous rectification is completely turned off. Up to 80% maximum duty cycle at 2-MHz switching frequency, the controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80% duty cycle, the controller will deliver 100% duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time, MOSFET delay/ rise/fall time, and the internal propagational delays. In order to maintain regulation, controller might fluctuate its duty cycle back and forth from 100% to something lower than 80% while the converter is operating in this input voltage range. If the input voltage drops further, controller will remain on 100%. If the input voltage increases to a point where it’s requiring less than 80% duty cycle, synchronous rectification is once again activated. The maximum duty cycle under boost mode is internally limited to 70% to prevent inductor saturation. If the converter is turned on for 100% duty cycle, inductor never gets a chance to discharge its energy and eventually saturate. In boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. The controller will deliver 0% duty cycle, if the input voltage is greater than the programmed output voltage. Because of signal propagation time and MOSFET delay/rise/fall time, controller will not transition smoothly from minimum controllable duty cycle to 0% duty cycle. For example, controller may decrease its duty cycle from 5% to 0% abruptly, instead of gradual decrease you see from 70% to 5%. FaxBack 408-970-5600, request 70847 www.siliconix.com Reference The reference voltage for the Si9166 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The reference pin requires 0.1-µF decoupling capacitor. Error Amplifier The error amplifier gain-bandwidth product and slew rate are critical parameters which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, error amplifier determines the converter response time. In order to minimize the response time, the Si9166 is designed with 2-MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 V/µsec slew rate for ultra-fast large signal response. S-60752—Rev. B, 05-Apr-99 7 Si9166 Vishay Siliconix New Product Oscillator Break-Before-Make Timing The oscillator is designed to operate up to 2-MHz minimal. The 2-MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with 2-MHz switching frequency, quiescent current is only 500 µA with unique power saving circuit design. The switching frequency is easily programmed by attaching resistor to ROSC pin. See oscillator frequency versus ROSC curve to select the proper timing values for desired operating frequency. The tolerance on the operating frequency is (20% with 1% tolerance resistor). A proper BBM time is essential in order to prevent shootthrough current and to maintain high efficiency. The breakbefore-make time is set internally at 20 to 60 ns @ VS = 3.6 V. The high- and low-side gate drive voltages are monitored and when the gate to source voltage reaches 1.75 V above or below the initial starting voltage, 20 to 60 ns BBM time is set before the other gate drive transitions to its proper state. The maximum and minimum duty cycle is limited by the BBM time. Since the BBM time is fixed, controllable maximum duty cycle will vary depending on the switching frequency. Synchronization Output Driver Stage The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. The logic high-to-low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. The DH pin is designed to drive the high-side p-channel MOSFET, independent of topology. The DL pin is designed to drive the low-side n-channel MOSFET, independent of topology. The driver stage is sized to sink and source peak currents up to 450 mA with VS = 3.3 V. The ringing from the gate drive output trace inductance can produce negative voltage on the DH and DL respect to PGND. The gate drive circuit is capable of withstanding these negative voltages without any functional defects. S-60752—Rev. B, 05-Apr-99 8 FaxBack 408-970-5600, request 70847 www.siliconix.com