Si9118/Si9119 New Product Vishay Siliconix Programmable Duty Cycle Controller 10- to 200-V Input Range Current-Mode Control Internal Start-Up Circuit Buffer Slope Compensation Voltage Low Quiescent Current Programmable Maximum Duty Cycle, with 80% as Default Soft-Start 2.7-MHz Error Amp 500-mA Output Drive Current Light Load Frequency Fold-Back The Si9118/Si9119 are a BiC/DMOS current-mode pulse width modulation (PWM) controller ICs for high-frequency dc/dc converters. Single-ended topologies (forward and flyback) can be implemented at frequencies up to 1 MHz. The controller operates in constant frequency mode during the full load and automatically switches to pulse skipping mode under light load to maintain high efficiency throughout the full load range. The maximum duty cycle is easily programmed with a resistor divider for optimum control. stage is almost eliminated to minimize quiescent supply current. The push-pull output driver provides high-speed switching to external MOSPOWER devices large enough to supply 50 W of output power. Shoot-through current for internal push-pull The Si9118/Si9119 are available in a 16-pin SOIC package and is specified over the industrial, D suffix (–40C to 85C) temperature range. The high-voltage DMOS transistor permits direct operation from bus voltages of up to 200 V. Other features include a 1.5% accurate voltage reference, 2.7-MHz bandwidth error amplifier, standby mode, soft-start and undervoltage lockout circuits. FB COMP 5 6 Error Amplifier NI 4 3 VREF ILIMIT 10 2 100 mV 9 PWM Pulse Skip + EN – IMAX 7 600 mV OSC 8 ROSC COSC R 15 Q DR S + – 14 –VIN +VIN 13 Ref Gen 23 A VCC DMAX – + 4.6 V SS/EN 11 1.0 – 2.0 V + – – + VSC (Si9118) SYNC (Si9119) 12 ICS PWM/PSM –VIN Substrate 16 1 – – + Document Number: 70815 S-60752—Rev. B, 05 Apr-99 + – + 8.6 V 9.3 V (VREG) Undervoltage Lockout www.Vishay Siliconix.com FaxBack 408-970-5600 1 Si9118/Si9119 New Product Vishay Siliconix Voltages Referenced to –VIN DMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C +VIN (Note: VCC < +VIN + 0.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Logic Input (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Power Dissipation (Package)a 16-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Linear Inputs (FB, ICS, ILIMIT, SS/EN) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Thermal Impedance (QJA) 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 85C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/C above 25C. * . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 kW to 1 MW Voltages Referenced to –VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 16.5 V COSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pF to 200 pF +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 200 V Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC – 4 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Test Conditions Unless Specified Parameter Symbol Limits D Suffix –40 to 85C O ill t Di Oscillator Disabled bl d –VIN = 0 V, VCC = 10 V Tempa Min Typb Max OSC Disabled, TA = 25C Room 3.94 4.0 4.06 OSC Disabled, Over Voltage and Temperature Rangesc Full 3.88 4.0 4.12 Unit Reference O t t Voltage V lt Output Short Circuit Current Load Regulation VREF V ISREF VREF = –VIN –30 –5 mA DVR/DIR IREF = 0 to –1 mA 10 40 mV Oscillator Initial Accuracyd Voltage Stabilityc Temperature Coefficientc fOSC ROSC = 374 kW, COSC = 200 pF 90 100 110 fOSCc ROSC = 70 kW, COSC = 200 pF 450 500 550 Df/f ROSC = 70 kW, COSC = 200 pF Df/f = [f(16.5 V) – f(9.5 V)] / f(9.5 V) 1 2 % OSC TC –40 TA 85C, fOSC = 100 kHz 200 500 ppm/C Sync High Pulse Width (Si9119) 200 Sync Low Pulse Width (Si9119) 200 kHz ns Sync Rise/Fall Time (Si9119) 200 Sync Logic Low (Si9119) VIL Sync Logic High (Si9119) VIH 4 0.8 Sync Rangec (Si9119) fEXT 1.05 x fOSC PWM/PSM Logic High VIH 4 PWM/PSM Logic Low VIL V kHz PWM/PSM 0.8 V DMAX Accuracy www.Vishay Siliconix.com FaxBack 408-970-5600 2 fOSC = 100 kHz with 1% Resistor 10 % Document Number: 70815 S-60752—Rev. B, 05 Apr-99 Si9118/Si9119 New Product Vishay Siliconix Test Conditions Unless Specified Parameter Symbol O ill t Di bl d Oscillator Disabled –VIN = 0 V, VCC = 10 V Limits D Suffix –40 to 85C Tempa Min Typb Max Unit t1.0 "200 nA "5 "25 mV Error Amplifier (OSC Disabled) Input BIAS Current IFB VFB = 5 V, NI = VREF Input OFFSET Voltage VOS2 Open Loop Voltage Gainc AVOL 65 80 dB Unity Gain Bandwidthc BW 1.8 2.7 MHz Output Current IOUT Source (VFB = 3.5 V, NI = VREF) –1.0 –2.7 Sink (VFB = 4.5 V, NI = VREF) 1.0 2.4 10 V v VCC v 16.5 V 50 80 Power Supply Rejection PSRR mA dB Pre-Regulator/Start-up Input Voltagec +VIN IIN = 10 mA Room Input Leakage Current +IIN VCC w 10 V Room Pre-Regulator Start-Up Current ISTART Pulse Width v 300 ms VCC = VULVO Room 8 15 VCC Pre-Regulator Turn-Off Threshold Voltage VREG IPRE-REGULATOR = 15 mA Room 8.7 9.3 9.8 Undervoltage Lockout VUVLO Room 8.0 8.6 9.3 V VREG –VUVLO VDELTA Room 0.3 0.7 2.5 mA 200 V 10 mA mA Supply Supply Current ICC CLOAD v 50 pF, fOSC = 100 kHz 1.9 Protection Current Limit Threshold Voltage Current Limit Delay to Outputc Soft-Start Current Output Inhibit Voltage Pulse Skipping Threshold Voltage VI(Limit) VFB = 0 V, NI = VREF td VSENSE = 0.85 V, See Figure 1 0.5 ISS VSS(off) Soft-Start Voltage to Disable Driver Output VPS 0.6 0.7 V 77 100 ns –12 –23 –30 mA 0.5 1.26 80 100 120 mV V Mosfet Driver Output High Voltage VOH IOUT = –10 mA Room Full Output Low Voltage VOL IOUT = 10 mA Room Full Output Resistancec ROUT IOUT = 10 mA, Source or Sink Room Full 20 25 30 50 Room 40 75 Room 40 75 Rise Timec tr Fall Timec tf CL = 500 pF VCC – 0.3 VCC – 0.5 0.3 0.5 V W ns Notes a. Room = 25C, Full = as determined by the operating temperature suffix. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Guaranteed by design, not subject to production test. d. CSTRAY v 5 pF on COSC. Document Number: 70815 S-60752—Rev. B, 05 Apr-99 www.Vishay Siliconix.com FaxBack 408-970-5600 3 Si9118/Si9119 New Product Vishay Siliconix TYPICAL CHARACTERISTICS (25C UNLESS NOTED) MOSFET Oscillator Frequency Output Driver Rise and Fall Time 200 2 x 1000 47 pF tr for CL = 2500 pF Output Rise and Fall Time (ns) f OUT (kHz) 100 pF 150 pF 200 pF 2 x 100 Note: These curves were measured in a board with 3.5 pF of external parasitic capacitance. 150 tf for CL = 2500 pF 100 tr for CL = 1000 pF tf for CL = 1000 pF 50 tr 10% to 90% tf 90% to 10% 2 x 10 0 10 100 rOSC – Oscillator Resistance (kW) 9 1000 Supply Current vs. Output Frequency 11 12 13 14 15 VCC – Supply Voltage (V) 16 17 Supply Current vs. Supply Voltage 12 36 VCC = 12 V COSC = 47 pF 32 ROSC = 127 kW COSC = 47 pF fs = 500 kHz I CC – Supply Current (mA) 28 I CC – Supply Current (mA) 10 24 CL = 2500 pF 20 16 CL = 1000 pF 12 8 9 CL = 1000 pF 6 3 CL = 0 pF CL = 0 pF 4 0 0 0 200 400 600 800 fOUT – Output Frequency (kHz) 1000 9 10 11 12 13 14 15 VCC – Supply Voltage (V) 16 17 Switching Frequency vs. Supply Voltage 1.05 ROSC = 56 kW COSC = 100 pF Switching Frequency (MHz) 1.00 0.95 0.90 0.85 8 www.Vishay Siliconix.com FaxBack 408-970-5600 4 9 10 11 12 13 14 15 VCC – Supply Voltage (V) 16 17 Document Number: 70815 S-60752—Rev. B, 05 Apr-99 Si9118/Si9119 New Product Vishay Siliconix tr 10 ns 0.85 Current Sense 50% 0 td Output VCC 90% 0 FIGURE 1. +VIN PWM/PSM VREF 16 VCC 2 15 DR 3 14 –VIN 1 +VIN 1 16 VCC PWM/PSM 2 15 DR VREF 3 14 –VIN Order Number 13 DMAX SOIC: Si9118DY Si9119DY 12 SYNC 11 ICS NI 4 DMAX NI 4 5 SOIC Si9118DY 13 FB 12 VSC FB 5 SOIC Si9119DY COMP 6 Top View 11 ICS 6 Top View SS/EN 7 10 ILIMIT COSC 8 9 ROSC SS/EN 7 10 ILIMIT COSC 8 9 ROSC COMP Pin Number Symbol Description 1 +VIN 2 PWM/PSM 3 VREF 4 NI Non-inverting input of an error amplifier. 5 FB Inverting input of an error amplifier. 6 COMP Error amplifier output for external compensation network. 7 SS/EN Programmable soft-start with external capacitor or externally controlled disable mode. 8 COSC External capacitor to determine the switching frequency. 9 ROSC External resistor to determine the switching frequency. 10 ILIMIT Pulse by pulse peak current limiting pin. When the current sense voltage exceeds the current limit threshold, the gate drive signal is terminated. ILIMIT is also used to sense the current in pulse skipping mode. 11 ICS 12 SYNC or VSC 13 DMAX Sets the maximum duty cycle. Internally, the maximum duty cycle is clamped to 80%. 14 –VIN Single point ground. 15 DR Gate drive for the external MOSFET switch. 16 VCC Supply voltage for the IC after the startup transition. Document Number: 70815 S-60752—Rev. B, 05 Apr-99 Input bus voltage ranging from 10 V to 200 V. Connected to VREF forces the converter into PWM mode. Connected to –VIN forces the converter into PSM mode. 4-V reference voltage. Decouple with 0.1-F ceramic capacitor. Current sense input to control feedback response. Si9118: slope compensation pin. Si9119: clock synchronization pin. Logic high to low transition from external signal synchronizes the internal clock frequency. www.Vishay Siliconix.com FaxBack 408-970-5600 5 Si9118/Si9119 New Product Vishay Siliconix VO +VIN VCC PWM/PSM ICS VREF DR NI –VIN DMAX FB VSC COMP COSC SS/EN ILIMIT ROSC Si9420DY TL431 –48 V (–42 to –56 V) FIGURE 2. Si9118 15-W Forward Converter Schematic VO +VIN VCC PWM/PSM ICS VREF DR NI –VIN DMAX FB SYNC COMP COSC SS/EN ILIMIT ROSC Si9420DY TL431 –48 V (–42 to –56 V) FIGURE 3. Si9119 Forward Converter With External Slope Compensation www.Vishay Siliconix.com FaxBack 408-970-5600 6 Document Number: 70815 S-60752—Rev. B, 05 Apr-99 Si9118/Si9119 New Product Vishay Siliconix Start-Up Si9118/Si9119 are designed with internal depletion mode MOSFET capable of powering directly from the high input bus voltage. This feature eliminates the typical external start-up circuit saving valuable space and cost. But, most of all, this feature improves the converter efficiency during full load and has an even greater impact on light load. With an input bus voltage applied to the +VIN pin, the VCC voltage is regulated to 9.3 V. The UVLO circuit prevents the controller output driver section from turning on, until VCC voltage exceeds 8.7 V. In order to maximize converter efficiency, the designer should provide an external bootstrap winding to override the internal VCC regulator. If external VCC voltage is greater than 9.3 V, the internal depletion mode MOSFET regulator is disabled and power is derived from the external VCC supply. The VCC supply provides power to the internal circuity as well as providing supply voltage to the gate drive circuit. inductance value, the error amplifier gain-bandwidth determines the converter response time. In order to minimize the response time, Si9118/Si9119 is designed with a 2.7-MHz error amplifier gain-bandwidth product to provide the widest converter bandwidth possible. PWM Mode The converter operates in PWM mode if the PWM/PSM pin is connected to VREF pin or logic high. As the load current and line voltage vary, the Si9118/Si9119 maintain constant switching frequency until they reach minimum duty cycle. Once the output voltage regulation is exceeded with minimum duty cycle, the switching frequency will continue to decrease until regulation is achieved. The switching frequency is controlled by the external Rosc and Cosc as shown by the typical oscillator frequency curve. In PWM mode, output ripple noise is constant reducing EMI concerns as well as simplifying the filter to minimize the system noise. Soft-Start/Enable The soft-start time is externally programmable with capacitor connected to the SS/EN pin. A constant current source provides the current to the SS/EN pin to generate a linear start-up time versus the capacitance value. The SS/EN pin clamps the error amplifier output voltage, limiting the rate of increase in duty cycle. By controlling the rate of rise in duty cycle gradually, the output voltage rises gradually preventing the output voltage from overshooting. The SS/EN pin can also be used to enable or disable the output driver section with an external logic signal. Pulse Skipping Mode The reference voltage for the Si9118/Si9119 are set at 4.0 V. The reference voltage is not connected to the non-inverting inputs of the error amplifier, therefore, the minimum output voltage is not limited to reference voltage. The VREF pin requires a 0.1-F decoupling capacitor. If the PWM/PSM pin is connected to –VIN pin (logic low), the converter can operate in either PWM or PSM mode depending on the load current. The converter automatically transitions from PWM to PSM or vise versa to maintain output voltage regulation. In PSM mode, the MOSFET switch is turned on until the peak current sensed voltage reaches 100 mV and the output voltage meets or exceeds its regulation voltage. The converter is operating in pulse skipping mode because each pulse delivers excess energy into the output capacitor forcing the output voltage to exceed its regulation voltage. By forcing the output voltage to exceed the regulation voltage, succeeding pulses are skipped until the output voltage drops below the regulation point. Therefore, switching frequency will continue to reduce during PSM control as the demand for output current decreases. The pulse skipping mode cuts down the switching losses, the dominant power consumed during low output current, thereby maintaining high efficiency throughout the entire load range. With PWM/PSM pin in logic low state, the converter transitions back into PWM mode, if the peak current sensed voltage of 100 mV does not generate the required output voltage. In the region between pulse skipping mode and PWM mode, the controller may transition between the two modes, delivering spurts of pulses. This may cause the current waveform to look irregular, but this will not overly affect the ripple voltage. Even in this transitional mode, efficiency remains high. Error Amplifier Programmable Duty Cycle Control The error amplifier gain-bandwidth product is critical parameter which determines the transient response of converter. The transient response is function of both small and large signal responses. The small signal response is determined by the feedback compensation network while the large signal response is determined by the inductor di/dt slew rate. Besides the The maximum duty cycle limit is controlled by the voltage on DMAX pin. A DMAX voltage of 3.2 V generates 80% duty cycle while 0.0 V generates 0% duty cycle. The 80% duty cycle is maximum default condition at 1-MHz switching frequency. The DMAX voltage can be easily generated using resistor divider from the reference voltage. Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin (Si9119 only). The logic high to low transition synchronizes the clock. The external clock frequency must be at least 5% faster than the internal clock frequency. Reference Voltage Document Number: 70815 S-60752—Rev. B, 05 Apr-99 www.Vishay Siliconix.com FaxBack 408-970-5600 7 Si9118/Si9119 Vishay Siliconix New Product The maximum duty cycle limitation will be different when the converter is synchronized by an external frequency. If the internal free running frequency is much slower than the external SYNC signal (SYNC signal causes the internal clock to reset before the Cosc voltage ramps to 3.2 V) , duty cycle is determined by the one shot discharge time of the oscillator capacitor (100 ns). Therefore, with 1-MHz SYNC signal, maximum duty cycle of 90% can be achieved (100 ns is 10% of 1 MHz). If the internal free running frequency is very close to the external SYNC frequency (SYNC signal causes the internal clock to reset somewhere between 3.2 V to 4 V), duty cycle is determined by the ratio of Cosc voltage at the SYNC point and the 3.2 V. At this condition, the maximum duty cycle can be greater than 90%. Therefore, DMAX voltage must be modified in order to maintain desired maximum duty cycle. Slope Compensation Slope compensation is necessary for duty cycles greater than 50% to stabilize the inner current loop and maintain overall loop stability. In order to simplify the slope compensation circuitry, the Si9118 provides the buffered oscillator ramp signal, VSC to be used for external slope compensation. VSC is only available when DR is high. The VSC signal super-imposed with actual current sense signal should be used by the PWM comparator to determine the duty cycle. The summation of this signal should be fed into ICS pin. For optimum performance, proper slope compensation is required. The amount of slope compensation is determined by www.Vishay Siliconix.com FaxBack 408-970-5600 8 the resistors connected to the ICS pin. The amplitude of the VSC signal is same as the COSC pin voltage (4 V). For designs which use with SYNC pin, instead of VSC pin, the converter can still operate at duty cycles greater than 50% by generating an external slope compensation ramp using a simple RC circuit from the MOSFET driver output pin as shown on the application circuit. Over Current Protection Si9118/Si9119 are designed with a pulse-to-pulse peak current limiting protection circuit to protect itself, and the load in case of a failure. The voltage across the sense resistor is monitored continuously and if the voltage reaches its trigger level, the duty cycle is terminated. This limits the maximum current delivered to the load. In order to improve the accuracy of over current protection from traditional controllers, Si9118/Si9119 are designed with separate ILIMIT and ICS pins. Voltage on the ILIMIT pin does not sum in the traditional slope compensation voltage, which adds error into the detection level. ICS pin is used to sum the current sense signal and the slope compensation for loop stability. Output Driver Stage The DR pin is designed to drive a low-side n-channel MOSFET. The driver stage is sized to sink and source peak currents up to 500 mA with VCC = 12 V. This provides ample drive capability for 50 W of output power. Document Number: 70815 S-60752—Rev. B, 05 Apr-99