N-Channel Enhancement Mode Dual DMOS FET CORPORATION SD411 FEATURES • Normally "OFF" Configuration • High Speed Switching. . . . . . . . . . under 1 ns (typically) Low Capacitance . . . . . . . . . ciss <3.5 pf (typically) • Ultra • Tight Matching Characteristics • Pin Compatible to Industry Standard DESCRIPTION The SD411 is constructed utilizing Calogic’s high speed lateral DMOS techniques featuring tight matching characteristics between each FET. This device is an excellent choice for instrumentation, communication, RF and Video designs. Dual JFETs with Addition of Substrate Bias Pin ORDERING INFOMATION Part APPLICATIONS • Wideband Differential Amplifiers Amplifiers • Cascode • High Intercept Point Balanced Mixers • Oscillators • High Speed Analog Comparators Package Temperature Range -55oC to +150oC -55oC to +150oC SD411 TO-78 Hermetic Package XSD411 Sorted Chips in Carriers PIN CONFIGURATION TO-78 1 2 3 4 5 6 7 SOURCE 1 DRAIN 1 GATE 1 CASE/BODY SOURCE 2 DRAIN 2 GATE 2 4 5 3 2 6 7 1 BOTTOM VIEW CD2 C G2 D2 S2 G1 D1 S1 SD411 CORPORATION ABSOLUTE MAXIMUM RATINGS (TA = 25oC unless otherwise noted) VDS VSD VDB VSB VGD VGS VGB VG1G2 VD1D2 VS1S2 ID Drain-Source Voltage . . . . . . . . . . . . . . . . . . . . . . +20V Source-Drain Voltage . . . . . . . . . . . . . . . . . . . . . . +10V Drain-Body voltage. . . . . . . . . . . . . . . . . . . . . . . . +25V Source-Body Voltage . . . . . . . . . . . . . . . . . . . . . . +15V Gate-Drain Voltage. . . . . . . . . . . . . . . . . . . . . . . . +25V Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . +25V Gate-Body Voltage . . . . . . . . . . . . . . . . . . . . . . . . +25V Gate-to-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . +25V Drain-to-Drain Voltage . . . . . . . . . . . . . . . . . . . . . +20V Source-to-Source Voltage . . . . . . . . . . . . . . . . . . +15V Continuous Drain Current . . . . . . . . . . . . . . . . +50 mA PD PD Tj TS TL Device Dissipation (each side). . . . . . . . . . . . 360 mW Derating Factor . . . . . . . . . . . . . . . . . . . . 2.88 mW/ oC Total Device Dissipation . . . . . . . . . . . . . . . . 500 mW Derating Factor . . . . . . . . . . . . . . . . . . . . . . . 4 mW/oC Operating Junction Temperature Range . . . . . . . . . . . . . . . . -55 to +125oC Storage Temperature Range . . . . . . . . . -55 to +150oC Lead Temperature (1/16’ from mounting surface for 10 sec.). . . . . . . . . . . . . . . . . . . . . . +260oC ELECTRICAL CHARACTERISTICS(TA = +25oC per side unless otherwise noted) SYMBOL CHARACTERISTIC MIN TYP MAX UNITS TEST CONDITIONS STATIC BVDS Drain Source Breakdown Voltage 20 BVSD Source-Drain Breakdown Voltage 10 ID = 10 nA, VGS = VBS = -5V IS = 10 nA, VGD = VBD = -5V V BVDB Drain-Body Breakdown Voltage 25 ID = 10 nA, VGB = 0 Source Open BVSB Source-Body Breakdown Voltage 15 IS = 10µA, VGB = 0 Drain Open IDSX Drain-Source Leakage Current IGBS Gate-Body Leakage Current VGS(th) Gate-Source Threshold Voltage rDS(ON) Drain-Source ON Resistance (1) 0.7 0.5 1.0 10 nA VDS = 20V, VGS = VBS = -5V 1.0 µA VGS = 25V, VDB = VSB = 0 2.0 V ID = 1.0µA, VDS = VGS, VSB = 0 70 ohms ID = 1.0mA, VGS = 5.0V, VSB = 0 DYNAMIC mS VDS = 10V, ID = 20mA, VSB = 0 f = 1KHZ pF VDS = 10V, VGS = VBS = 0 f = 1MHZ gfs Common-Source Forward Transconductance(1) Ciss Common-Source Input Capacitance 3.5 Coss Common-Source Output Capacitance 1.2 Crss Common Source Reverse Transfer Capacitance 0.3 C(gs + sb) Source Node Capacitance 4.5 Differential Gate Source Voltage 25 mV 25 o 10 12 MATCH | VGS1 - VGS2 | ∆| VGS1 - VDS2 | ∆T Differential Drift NOTE 1: Pulse Test, 80sec, 1% Duty Cycle µV/ C VDS = 10V ID = 5.0mA TA = -55oC to VSB = 0 +125Co