DISCRETE SEMICONDUCTORS DATA SHEET PHP212L Dual P-channel enhancement mode MOS transistor Objective specification File under Discrete Semiconductors, SC13b 1997 Jun 20 Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L FEATURES PINNING - SOT96-1 (SO8) • High-speed switching PIN SYMBOL DESCRIPTION • No secondary breakdown 1 s1 source 1 • Very low on-state resistance 2 g1 gate 1 • Low threshold. 3 s2 source 2 4 g2 gate 2 APPLICATIONS 5 d2 drain 2 • Motor and actuator driver 6 d2 drain 2 • Power management 7 d1 drain 1 • Synchronized rectification. 8 d1 drain 1 DESCRIPTION Two P-channel enhancement mode MOS transistors in an 8-pin plastic SOT96-1 (SO8) package. d2 d2 d1 d1 handbook, halfpage 8 5 1 4 CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. MAM119 s1 g 1 s2 g 2 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER VDS drain-source voltage (DC) VSD source-drain diode forward voltage CONDITIONS IS = −1.25 A MIN. MAX. UNIT − −30 V − −1.3 V VGS gate-source voltage (DC) − ±12 V VGSth gate-source threshold voltage ID = −1 mA; VDS = VGS −0.5 −1.1 V ID drain current (DC) Ts = 80 °C − −4 A RDSon drain-source on-state resistance ID = −2 A; VGS = −4.5 V − 0.12 Ω Ptot total power dissipation Ts = 80 °C − 3.5 W 1997 Jun 20 2 Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per P-channel VDS drain-source voltage (DC) − −30 V VGS gate-source voltage (DC) − ±12 V ID drain current (DC) Ts = 80 °C; note 1 − −4 A IDM peak drain current note 2 − −16 A Ptot total power dissipation Ts = 80 °C; note 3 − 3.5 W Tamb = 25 °C; note 4 − 2.6 W Tamb = 25 °C; note 5 − 1.1 W Tamb = 25 °C; note 6 − 1.5 W Tstg storage temperature −55 +150 °C Tj operating junction temperature −55 +150 °C Source-drain diode IS source current (DC) Ts = 80 °C − −2.6 A ISM peak pulsed source current note 2 − −10 A Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. THERMAL CHARACTERISTICS SYMBOL Rth j-s 1997 Jun 20 PARAMETER thermal resistance from junction to soldering point 3 VALUE UNIT 20 K/W Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per P-channel V(BR)DSS drain-source breakdown voltage VGS = 0; ID = −10 µA −30 − − V VGSth gate-source threshold voltage VGS = VDS ; ID = −1 mA −0.5 − −1.1 V IDSS drain-source leakage current VGS = 0; VDS = −24 V − − −100 nA IGSS gate leakage current VGS = ±12 V; VDS = 0 − − ±100 nA RDSon drain-source on-state resistance VGS = −2.5 V; ID = −1 A − − 0.25 Ω VGS = −4.5 V; ID = −2 A − − 0.12 Ω Ciss input capacitance VGS = 0; VDS = −24 V; f = 1 MHz − 450 − pF Coss output capacitance VGS = 0; VDS = −24 V; f = 1 MHz − 200 − pF Crss reverse transfer capacitance VGS = 0; VDS = −24 V; f = 1 MHz − 100 − pF QG total gate charge VGS = −6 V; VDD = −15 V; ID = −1 A − 13 − nC QGS gate-source charge VGS = −6 V; VDD = −15 V; ID = −1 A − 1 − nC QGD gate-drain charge VGS = −6 V; VDD = −15 V; ID = −1 A − 4 − nC Switching times td(on) turn-on delay time VGS = 0 to −6 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 6 − ns tr rise time VGS = 0 to −6 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 4 − ns ton turn-on switching time VGS = 0 to −6 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 10 − ns td(off) turn-off delay time VGS = −6 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 29 − ns tf fall time VGS = −6 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 16 − ns toff turn-off switching time VGS = −6 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 45 − ns Source-drain diode VSD source-drain diode forward voltage VGD = 0; IS = −1.25 A − − −1.3 V trr reverse recovery time IS = −1.25 A; di/dt = 100 A/µs − 75 − ns 1997 Jun 20 4 Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Jun 20 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 5 o 8 0o Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jun 20 6 Philips Semiconductors Objective specification Dual P-channel enhancement mode MOS transistor PHP212L NOTES 1997 Jun 20 7 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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