DISCRETE SEMICONDUCTORS DATA SHEET BSS92 P-channel enhancement mode vertical D-MOS transistor Product specification Supersedes data of April 1995 File under Discrete Semiconductors, SC13b 1997 Jun 19 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS92 FEATURES PINNING - TO-92 (SOT54) variant • Direct interface to C-MOS, TTL, etc. PIN SYMBOL • High-speed switching DESCRIPTION 1 g gate • No secondary breakdown. 2 d drain 3 s source APPLICATIONS • Line current interrupter in telephony applications • Relay, high speed and line transformer drivers. d handbook, halfpage 1 DESCRIPTION 2 3 g P-channel enhancement mode vertical D-MOS transistor in a TO-92 (SOT54) variant package. s MAM144 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER VDS drain-source voltage (DC) VGSO gate-source voltage (DC) ID drain current (DC) RDSon drain-source on-state resistance Ptot total power dissipation yfs forward transfer admittance 1997 Jun 19 CONDITIONS MIN. TYP. MAX. UNIT − − −240 V − − ±20 V − − −150 mA ID = −100 mA; VGS = −10 V − 10 20 Ω Tamb ≤ 25 °C − − 1 W VDS = −25 V; ID = −100 mA 60 200 − mS open drain 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS92 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDS drain-source voltage (DC) VGSO gate-source voltage (DC) ID drain current (DC) IDM peak drain current Ptot total power dissipation Tstg Tj CONDITIONS open drain MIN. MAX. UNIT − −240 V − ±20 V − −150 mA − −600 mA − 1 W storage temperature −55 +150 °C operating junction temperature − 150 °C Tamb ≤ 25 °C; note 1 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 125 K/W note 1 Note to the Limiting values and Thermal characteristics 1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for drain lead minimum 10 mm × 10 mm. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS drain-source breakdown voltage VGS = 0; ID = −250 µA −240 − − V VGSth gate-source threshold voltage VDS = VGS ; ID = −1 mA −0.8 − −2.8 V IDSS drain-source leakage current VGS = 0; VDS = −60 V − − −200 nA VGS = 0; VDS = −200 V − − −60 µA IGSS gate leakage current VDS = 0; VGS = ±20 V − − ±100 nA RDSon drain-source on-state resistance VGS = −10 V; ID = −100 mA − 10 20 Ω yfs forward transfer admittance VDS = −25 V; ID = −100 mA 60 200 − mS Ciss input capacitance VGS = 0; VDS = −25 V; f = 1 MHz − 65 − pF Coss output capacitance VGS = 0; VDS = −25 V; f = 1 MHz − 20 − pF Crss reverse transfer capacitance VGS = 0; VDS = −25 V; f = 1 MHz − 6 − pF Switching times (see Figs 2 and 3) ton turn-on time VGS = 0 to −10 V; VDD = −50 V; ID = −250 mA − 5 − ns toff turn-off time VGS = −10 to 0 V; VDD = −50 V; ID = −250 mA − 20 − ns 1997 Jun 19 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS92 handbook, halfpage 10 % VDD = −50 V handbook, halfpage INPUT 90 % −10 V 10 % ID 0 OUTPUT 50 Ω 90 % MBB689 t on Fig.2 Switching times test circuit. 1997 Jun 19 t off MBB690 Fig.3 Input and output waveforms. 4 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS92 PACKAGE OUTLINE Plastic single-ended leaded (through hole) package; 3 leads (on-circle) SOT54 variant c L2 E d A L b 1 e1 2 e D 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) max L2 max mm 5.2 5.0 0.48 0.40 0.66 0.56 0.45 0.40 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant 1997 Jun 19 REFERENCES IEC JEDEC EIAJ TO-92 SC-43 5 EUROPEAN PROJECTION ISSUE DATE 97-04-14 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS92 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Jun 19 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES 1997 Jun 19 7 BSS92 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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