DISCRETE SEMICONDUCTORS DATA SHEET PHN205 Dual N-channel enhancement mode MOS transistor Product specification Supersedes data of 1997 Jun 18 File under Discrete Semiconductors, SC13b 1997 Oct 22 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor FEATURES PHN205 PINNING - SOT96-1 (SO8) • High-speed switching PIN SYMBOL DESCRIPTION • No secondary breakdown 1 s1 source 1 • Very low on-state resistance. 2 g1 gate 1 3 s2 source 2 APPLICATIONS 4 g2 gate 2 • Motor and actuator driver 5 d2 drain 2 • Power management 6 d2 drain 2 • Synchronized rectification. 7 d1 drain 1 8 d1 drain 1 DESCRIPTION Two N-channel enhancement mode MOS transistors in an 8-pin plastic SOT96-1 (SO8) package. d2 d2 d1 d1 handbook, halfpage 8 5 1 4 CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. MAM117 s1 g 1 s2 g 2 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per N-channel VDS drain-source voltage (DC) VSD source-drain diode forward voltage VGS gate-source voltage (DC) VGSth gate-source threshold voltage − 30 V − 1 V − ±20 V ID = 1 mA; VDS = VGS 1 2.8 V IS = 1.25 A ID drain current (DC) Ts = 80 °C − 6.4 A RDSon drain-source on-state resistance ID = 3.2 A; VGS = 10 V − 50 mΩ Ptot total power dissipation Ts = 80 °C − 3.5 W 1997 Oct 22 2 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per N-channel VDS drain-source voltage (DC) − 30 V VGS gate-source voltage (DC) − ±20 V ID drain current (DC) Ts = 80 °C; note 1 − 6.4 A IDM peak drain current note 2 − 25 A Ptot total power dissipation Ts = 80 °C; note 3 − 3.5 W Tamb = 25 °C; note 4 − 2.6 W Tamb = 25 °C; note 5 − 1.1 W Tamb = 25 °C; note 6 − 1.5 W Tstg storage temperature −65 +150 °C Tj operating junction temperature −65 +150 °C Source-drain diode IS source current (DC) Ts = 80 °C − 3.5 A ISM peak pulsed source current note 2 − 14 A Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. THERMAL CHARACTERISTICS SYMBOL Rth j-s 1997 Oct 22 PARAMETER thermal resistance from junction to soldering point 3 VALUE UNIT 20 K/W Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 MGG340 8 MGG341 102 handbook, halfpage handbook, halfpage Ptot ID (A) (W) 6 tp = 10 10 µs (1) 100 µs 4 1 δ= P 1 ms tp T 10 ms t 100 ms DC 2 tp 10−1 0 0 50 100 Ts (°C) T 10−1 150 1 10 δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.2 Power derating curve. 1997 Oct 22 Fig.3 SOAR. 4 VDS (V) 102 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per N-channel V(BR)DSS drain-source breakdown voltage VGS = 0; ID = 10 µA 30 − − V VGSth gate-source threshold voltage VGS = VDS ; ID = 1 mA 1 − 2.8 V IDSS drain-source leakage current VGS = 0; VDS = 24 V − − 100 nA IGSS gate leakage current VGS = ±20 V; VDS = 0 − − ±100 nA RDSon drain-source on-state resistance VGS = 4.5 V; ID = 1.6 A − − 0.1 Ω VGS = 10 V; ID = 3.2 A − − 0.05 Ω Ciss input capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 450 − pF Coss output capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 200 − pF Crss reverse transfer capacitance VGS = 0; VDS = 24 V; f = 1 MHz − 100 − pF QG total gate charge VGS = 10 V; VDD = 15 V; ID = 3.2 A − 15 − nC QGS gate-source charge VGS = 10 V; VDD = 15 V; ID = 3.2 A − 1 − nC QGD gate-drain charge VGS = 10 V; VDD = 15 V; ID = 3.2 A − 5 − nC td(on) turn-on delay time VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 7 − ns tf fall time VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 8 − ns ton turn-on switching time VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 15 − ns td(off) turn-off delay time VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 20 − ns tr rise time VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 12 − ns toff turn-off switching time VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω; see Fig.4 − 32 − ns Source-drain diode VSD source-drain diode forward voltage VGD = 0; IS = 1.25 A − − 1 V trr reverse recovery time IS = 1.25 A; di/dt = −100 A/µs − 45 − ns 1997 Oct 22 5 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor handbook, full pagewidth PHN205 VDD 90 % Vin RL 10 % 0 Vout 90 % Vout Vin 10 % 0 td(off) td(on) tf MAM274 tr ton toff Fig.4 Switching time test circuit; input and output waveforms. MGG342 102 handbook, full pagewidth Rth js (K/W) (1) 10 (2) (3) (4) (5) 1 (6) δ= P tp T (7) (8) 10−1 10−6 t tp (9) T 10−5 10−4 (1) δ = 0.75. (2) δ = 0.5. (3) δ = 0.33. (4) δ = 0.2. (5) δ = 0.1. (6) δ = 0.05. (7) δ = 0.02. (8) δ = 0.01. 10−3 10−2 10−1 tp (s) 1 (9) δ = 0. Fig.5 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values. 1997 Oct 22 6 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 MGG343 1250 C (pF) MGG344 30 handbook, halfpage handbook, halfpage ID (A) 1000 (1) (2) 20 750 (3) (1) 500 10 (4) (2) 250 (5) (3) (6) 0 0 4 8 12 0 16 20 VDS (V) 0 VGS = 0; f = 1 MHz; Tj = 25 °C. (1) Ciss. (2) Coss. (3) Crss. Fig.6 4 8 Tamb = 25 °C; tp = 80 µs; δ = 0. (1) VGS = 10 V. (2) VGS = 5 V. (3) VGS = 4.5 V. Capacitance as a function of drain-source voltage; typical values. 12 (4) VGS = 4 V. (5) VGS = 3.5 V. (6) VGS = 3 V. Fig.7 Output characteristics; typical values. MGG345 30 VDS (V) MGG346 16 handbook, halfpage handbook, halfpage V (V) ID (A) 12 20 8 (1) (2) 10 4 0 0 0 2 4 VGS (V) 6 0 4 8 12 16 QG (nC) VDD = 12.5 V; ID = 3.2 A; Tamb = 25 °C. (1) VDS. (2) VGS. VDS = 10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. Fig.9 Fig.8 Transfer characteristics; typical values. 1997 Oct 22 7 Gate-source voltage and drain-source voltage as a function of total gate charge; typical values. Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 MGG347 16 MGG348 103 handbook, halfpage handbook, halfpage IS (A) RDSon 12 (1) (2) (3) (4) (5) (mΩ) (1) (2) (3) 102 8 4 0 0 0.4 0.8 VSD (V) 10 1.2 0 2 4 6 Tamb = 25 °C; tp = 300 µs; δ = 0. VDS ≥ ID × RDSon. (2) I = 1.6 A. VGD = 0. (1) Tamb = 150 °C; tp = 300 µs; δ = 0. (2) Tamb= 25 °C; tp = 300 µs; δ = 0. (3) Tamb= −65 °C; tp = 300 µs; δ = 0. D (1) ID = 0.5 A. 10 VGS (V) (4) ID = 6.4 A. (5) ID = 10 A. Fig.11 Drain-source on-state resistance as a function of gate-source voltage; typical values. Fig.10 Source current as a function of source-drain diode forward voltage; typical values. MGG349 1.3 (3) ID = 3.2A. 8 MGG359 2 handbook, halfpage handbook, halfpage k k 1.2 (1) 1.5 (2) 1.1 1 1 0.9 0.5 0.8 0.7 −100 −50 0 50 100 0 −100 150 Tj (°C) −50 0 50 100 150 Tj (°C) R DSon at T j k = ---------------------------------------R DSon at 25 °C V GSth at T j k = ------------------------------------V GSth at 25°C VGSth at VDS = VGS; ID = 1 mA. (1) RDSon at VGS = 10 V; ID = 3.2 A. (2) RDSon at VGS = 4.5 V; ID = 1.6 A. Fig.12 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; typical values. Fig.13 Temperature coefficient of drain-source on-resistance as a function of junction temperature; typical values. 1997 Oct 22 8 Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Oct 22 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 9 o 8 0o Philips Semiconductors Product specification Dual N-channel enhancement mode MOS transistor PHN205 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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