LH168A 384-output TFT-LCD Source Driver IC LH168A DESCRIPTION PIN CONNECTIONS The LH168A is a 384-output TFT-LCD source driver IC which can simultaneously display 262 144 colors in 64 gray scales. TOP VIEW 444-PIN TCP XO1 1 YO1 2 ZO1 3 FEATURES • Number of LCD drive outputs : 384 • Built-in 6-bit digital input DAC • 2-port input for each circuit of data inputs R, G and B, and it is possible to sample and hold display data of two pixels at the same time • Possible to display 262 144 colors in 64 gray scales with reference voltage input of 10 gray scales : This reference voltage input corresponds to ‹ correction and intermediate reference voltage input can be abbreviated • Cascade connection • Sampling sequence : Output shift direction can be selected XO1, YO1, ZO1/XO128, YO128, ZO128 or ZO128, YO128, XO128/ZO1, YO1, XO1 • Shift clock frequency : 55 MHz (MAX.) • Supply voltages – VCC (for logic system) : +2.7 to +3.6 V – VLS (for LCD drive system) : +3.0 to +5.5 V • Package : 444-pin TCP (Tape Carrier Package) 444 443 442 441 GNDA VLS TESTB XA5 436 XA0 435 YA5 CHIP SURFACE 430 YA0 429 ZA5 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 ZA0 SPOI GNDL POL1 POL2 CK VCC V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 SPIO XB5 401 XB0 400 YB5 395 YB0 394 ZB5 389 388 387 386 385 ZB0 LS LBR VLS GNDA XO128 382 YO128 383 ZO128 384 NOTE : Doesn't prescribe TCP outline. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LH168A PIN DESCRIPTION PIN NO. 1 to 384 SYMBOL XO1-ZO128 I/O O LCD drive output pins DESCRIPTION 385, 444 386, 443 GNDA VLS – Ground pins for analog circuit – Power supply pins for analog circuit 387 388 LBR LS I I Shift direction selection input pin Latch input pin 389 to 394 395 to 400 ZB0-ZB5 YB0-YB5 I I Data input pins Data input pins 401 to 406 XB0-XB5 I Data input pins 407 408 to 417 SPIO V10-V1 I/O I Reference voltage input pins 418 VCC 419 CK – I Power supply pin for digital circuit Shift clock input pin 420, 421 POL2, POL1 I Input data polarity exchange input pins 422 423 GNDL SPOI – I/O 424 to 429 430 to 435 ZA0-ZA5 I Data input pins YA0-YA5 I Data input pins 436 to 441 XA0-XA5 I Data input pins 442 TESTB I IC test pin Start pulse input/cascade output pin Ground pin for digital circuit Start pulse input/cascade output pin 2 LH168A BLOCK DIAGRAM VCC GNDL 418 GNDA GNDA 385 422 444 LBR 387 SPIO 407 SHIFT REGISTER 423 SPOI CK 419 POL1 421 1 2 XA0 436 401 XB0 XA5 441 406 XB5 YA0 430 395 YB0 YA5 435 400 YB5 ZA0 424 389 ZB0 ZA5 429 394 ZB5 64 6x2 442 TESTB DATA LATCH 6x2 SAMPLING MEMORY 6x2 POL2 420 6x2 6x2 6x2 6x2 6x2 6x2 6x2 LS 388 HOLD MEMORY 6x2 V1 417 386 VLS LEVEL SHIFTER V2 416 6x2 V3 415 V4 414 V5 413 V6 412 REFERENCE VOLTAGE GENERATION CIRCUIT 64 DA CONVERTER V7 411 V8 410 V9 409 OUTPUT CIRCUIT V10 408 1 2 3 XO1 YO1 ZO1 3 382 383 384 XO128 YO128 ZO128 443 VLS LH168A FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK Shift Register FUNCTION Used as a bi-directional shift register which performs the shifting operation by CK and Data Latch selects bits for data sampling. Used to temporary latch the input data which is sent to the sampling memory. Sampling Memory Hold Memory Used to sample the data to be entered by time sharing. Used for temporary latch processing of data in the sampling memory by LS input. Level Shifter Used to shift the data in the hold memory to the power supply level of the analog circuit unit and sends the shifted data to DA converter. Reference Voltage Generation Circuit DA Converter Output Circuit Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit. Used to generate an analog signal according to the display data and sends the signal to the output circuit. Used as a voltage follower, configured with an operational amplifier and an output buffer, which outputs analog signals of 64 gray scales to LCD drive output pin. INPUT/OUTPUT CIRCUITS VCC I To Internal Circuit GNDL ¿Applicable pins¡ CK, LS, LBR, XA0-XA5, XB0-XB5, YA0-YA5, YB0-YB5, ZA0-ZA5, ZB0-ZB5 Fig. 1 Input Circuit (1) VCC I To Internal Circuit GNDL ¿Applicable pins¡ POL1, POL2 GNDL Fig. 2 Input Circuit (2) 4 LH168A VCC VCC I To Internal Circuit ¿Applicable pin¡ TESTB GNDL Fig. 3 Input Circuit (3) Pch Tr I VCC Output Signal O Output Control Signal Nch Tr GNDL VCC To Internal Circuit ¿Applicable pins¡ SPIO, SPOI GNDL Fig. 4 Input/Output Circuit VLS Operational Amplifier O + From Internal Circuit ¿Applicable pins¡ XO1-XO128, YO1-YO128, ZO1-ZO128 – GNDA Fig. 5 Output Circuit 5 LH168A FUNCTIONAL DESCRIPTION Pin Functions SYMBOL VCC FUNCTIONS Used as power supply pin for digital circuit, connected to +2.7 to +3.6 V. VLS Used as power supply pin for analog circuit, connected to +3.0 to +5.5 V. Used as ground pin for logic circuit, connected to 0 V. GNDL GNDA Used as ground pin for LCD drive circuit, connected to 0 V. Used as input pins of start pulse and also used as output pins for cascade connection. SPIO When "H" is input into start pulse input pin, data sampling is started. On completion of SPOI sampling, "H" pulse is output to output pin for cascade connection. Pin functions are selected by LBR. For selecting, refer to "Functional Operations". LBR LS CK Used as input pin for selecting the shift register direction. For selecting, refer to "Functional Operations". Used as input pin for parallel transfer from sampling memory to hold memory. Data is transferred at the rising edge and output from LCD drive output pin. Used as shift clock input pin. Data is latched into sampling memory from data input pin at the rising edge. Used as reference voltage input pins. Hold the reference voltage fixed during the period of V1-V10 XA0-XA5, YA0-YA5 ZA0-ZA5, XB0-XB5 YB0-YB5, ZB0-ZB5 LCD drive output. For relation between input data and output voltage values, refer to "Output Voltage Value". For internal gamma correction, refer to "Gamma Correction Value". Used as data input pins of R, G, and B colors. 6-bit x 2-pixel data are input from data pins at the rising edge of CK. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value". Select the data to be entered into X, Y, and Z according to picture element arrays of the panel. Used as LCD drive output pins which output the voltage corresponding to the input of data XO1-XO128, YO1-YO128, ZO1-ZO128 input pins (XA0 to XA5, XB0 to XB5, YA0 to YA5, YB0 to YB5, ZA0 to ZA5, ZB0 to ZB5). Data of XO1 to XO128 correspond to XA0 to XA5 and XB0 to XB5. Data of YO1 to YO128 correspond to YA0 to YA5 and YB0 to YB5, and data of ZO1 to ZO128 correspond to ZA0 to ZA5 and ZB0 to ZB5. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value". POL1 POL2 TESTB Used as input pins for input data polarity exchange. When "L" is entered, display data becomes normal mode. When "H" is entered, input data becomes polarity exchange mode (POL1 = A system, POL2 = B system). For relation between input data and output voltage values, refer to "Output Voltage Value". Must be connected to 0 V or opened. Used as pin for IC testing. Must be connected to VCC or opened. 6 LH168A Functional Operations The following describes the relation between data input pin and output direction. Data input pin XA0-XA5 YA0-YA5 ZA0-ZA5 XB0-XB5 YB0-YB5 ZB0-ZB5 Output direction XO1 YO1 ZO1 XO2 YO2 ZO2 πππ πππ XB0-XB5 YB0-YB5 ZB0-ZB5 XO128 YO128 ZO128 The following describes the relation between LBR pin, SPOI pin, SPIO pin and output direction. PIN OUTPUT DIRECTION LBR SPOI RIGHT SHIFT (XO1, YO1, ZO1/XO128, YO128, ZO128) H Input LEFT SHIFT (ZO128, YO128, XO128/ZO1, YO1, XO1) L Output SPIO Output Input NOTE : Color data corresponding to X, Y, and Z vary depending on the output direction. 7 LH168A Output Voltage Value value is determined by the lower 3-bit data (D2, D1 and D0). Relation between input data and output voltage values is shown below. Two voltages are selected from all of the reference voltages (V1-V10) by the upper 3-bit data (D5, D4 and D3) of the 6-bit input data (D5, D4, D3, D2, D1 and D0) taken by time sharing, and intermediate INPUT DATA 0 OUTPUT VOLTAGE POL1, POL2 = "L" V1 INPUT OUTPUT VOLTAGE POL1, POL2 = "H" V10 DATA 20 POL1, POL2 = "L" V6 + (V5 – V6) x 7/8 POL1, POL2 = "H" V5 1 V2 + (V1 – V2) x 6/7 V9 21 V6 + (V5 – V6) x 6/8 V5 + (V4 – V5) x 1/8 2 V2 + (V1 – V2) x 5/7 V2 + (V1 – V2) x 4/7 V9 + (V8 – V9) x 1/7 V9 + (V8 – V9) x 2/7 22 23 V6 + (V5 – V6) x 5/8 V6 + (V5 – V6) x 4/8 V5 + (V4 – V5) x 2/8 V5 + (V4 – V5) x 3/8 5 V2 + (V1 – V2) x 3/7 V2 + (V1 – V2) x 2/7 V9 + (V8 – V9) x 3/7 V9 + (V8 – V9) x 4/7 24 25 V6 + (V5 – V6) x 3/8 V6 + (V5 – V6) x 2/8 V5 + (V4 – V5) x 4/8 V5 + (V4 – V5) x 5/8 6 V2 + (V1 – V2) x 1/7 V9 + (V8 – V9) x 5/7 26 V6 + (V5 – V6) x 1/8 V5 + (V4 – V5) x 6/8 7 V2 8 V3 + (V2 – V3) x 7/8 V9 + (V8 – V9) x 6/7 V8 27 28 V6 V7 + (V6 – V7) x 7/8 V5 + (V4 – V5) x 7/8 V4 9 A V3 + (V2 – V3) x 6/8 V3 + (V2 – V3) x 5/8 V8 + (V7 – V8) x 1/8 V8 + (V7 – V8) x 2/8 29 2A V7 + (V6 – V7) x 6/8 V7 + (V6 – V7) x 5/8 V4 + (V3 – V4) x 1/8 V4 + (V3 – V4) x 2/8 B V3 + (V2 – V3) x 4/8 V8 + (V7 – V8) x 3/8 2B V7 + (V6 – V7) x 4/8 V4 + (V3 – V4) x 3/8 C V3 + (V2 – V3) x 3/8 V3 + (V2 – V3) x 2/8 V8 + (V7 – V8) x 4/8 V8 + (V7 – V8) x 5/8 2C 2D V7 + (V6 – V7) x 3/8 V7 + (V6 – V7) x 2/8 V4 + (V3 – V4) x 4/8 V4 + (V3 – V4) x 5/8 F V3 + (V2 – V3) x 1/8 V3 V8 + (V7 – V8) x 6/8 V8 + (V7 – V8) x 7/8 2E 2F V7 + (V6 – V7) x 1/8 V7 V4 + (V3 – V4) x 6/8 V4 + (V3 – V4) x 7/8 10 V4 + (V3 – V4) x 7/8 V7 30 V8 + (V7 – V8) x 7/8 V3 11 12 V4 + (V3 – V4) x 6/8 V4 + (V3 – V4) x 5/8 V7 + (V6 – V7) x 1/8 V7 + (V6 – V7) x 2/8 31 32 V8 + (V7 – V8) x 6/8 V8 + (V7 – V8) x 5/8 V3 + (V2 – V3) x 1/8 V3 + (V2 – V3) x 2/8 13 V4 + (V3 – V4) x 4/8 V4 + (V3 – V4) x 3/8 V7 + (V6 – V7) x 3/8 V7 + (V6 – V7) x 4/8 33 34 V8 + (V7 – V8) x 4/8 V8 + (V7 – V8) x 3/8 V3 + (V2 – V3) x 3/8 V3 + (V2 – V3) x 4/8 V4 + (V3 – V4) x 2/8 V4 + (V3 – V4) x 1/8 V7 + (V6 – V7) x 5/8 V7 + (V6 – V7) x 6/8 35 36 V8 + (V7 – V8) x 2/8 V8 + (V7 – V8) x 1/8 V3 + (V2 – V3) x 5/8 V3 + (V2 – V3) x 6/8 17 V4 V7 + (V6 – V7) x 7/8 37 V8 V3 + (V2 – V3) x 7/8 18 V5 + (V4 – V5) x 7/8 V5 + (V4 – V5) x 6/8 V6 V6 + (V5 – V6) x 1/8 38 39 V9 + (V8 – V9) x 6/7 V9 + (V8 – V9) x 5/7 V2 V2 + (V1 – V2) x 1/7 1B V5 + (V4 – V5) x 5/8 V5 + (V4 – V5) x 4/8 V6 + (V5 – V6) x 2/8 V6 + (V5 – V6) x 3/8 3A 3B V9 + (V8 – V9) x 4/7 V9 + (V8 – V9) x 3/7 V2 + (V1 – V2) x 2/7 V2 + (V1 – V2) x 3/7 1C V5 + (V4 – V5) x 3/8 V6 + (V5 – V6) x 4/8 3C V9 + (V8 – V9) x 2/7 V2 + (V1 – V2) x 4/7 1D 1E V5 + (V4 – V5) x 2/8 V5 + (V4 – V5) x 1/8 V6 + (V5 – V6) x 5/8 V6 + (V5 – V6) x 6/8 3D 3E V9 + (V8 – V9) x 1/7 V9 V2 + (V1 – V2) x 5/7 V2 + (V1 – V2) x 6/7 1F V5 V6 + (V5 – V6) x 7/8 3F V10 V1 3 4 D E 14 15 16 19 1A 8 LH168A ‹ (gamma) Correction Value reference voltage input pins matches the reference voltages (V2 to V9) for ‹ correction of LCD panel, the external power supply of the intermediate voltages (for V2 to V9 pins) is not required. Between reference voltage input pins, 7 or 8 resistors of the same resistance value are connected in series. When the resistance ratio between respective LH168A External Reference Voltage V1 V2 R1 7 equal parts V3 R2 8 equal parts V4 R3 8 equal parts V5 R4 8 equal parts V6 R5 8 equal parts V7 R6 8 equal parts V8 R7 8 equal parts V9 R8 7 equal parts V10 R9 The following shows the ratio of ‹ correction resistance. R9 7.85 R8 R7 1.98 1.32 R6 0.99 R5 0.91 1.24 R4 R3 R2 1.08 2.15 R1 2.48 9 LH168A PRECAUTIONS Reference voltage input The relation of the reference voltage input is shown here. Precautions when connecting or disconnecting the power supply This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. GNDA < V1 ≤ V2 ≤ π ≤ V9 ≤ V10 < VLS or VLS > V1 ≥ V2 ≥ π ≥ V9 ≥ V10 > GNDA Maximum ratings When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings. VCC / logic input / VLS, V1-V10 When disconnecting the power supply, follow the reverse sequence. Target output load This IC is designed for a 70 pF output load capacity. When using this IC for other than 70 pF panels, confirm the device is having no problem before using it. ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Input voltage Output voltage Storage temperature SYMBOL VCC VLS VI VI VO VO TSTG APPLICABLE PINS VCC VLS V1-V10 SPIO, SPOI, CK, LS, LBR, POL1, POL2, TESTB, XA0-XA5, XB0-XB5, YA0-YA5, YB0-YB5, ZA0-ZA5, ZB0-ZB5 SPIO, SPOI XO1-ZO128 RATING –0.3 to +7.0 –0.3 to +7.0 –0.3 to VLS + 0.3 UNIT V V V –0.3 to VCC + 0.3 V –0.3 to VCC + 0.3 –0.3 to VLS + 0.3 –45 to +125 V V ˚C NOTES : 1. TA = +25 ˚C 2. The maximum applicable voltage on any pin with respect to GNDL and GNDA (0 V). RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VCC Supply voltage VLS Reference voltage input V1-V10 Clock frequency fCK LCD drive output load capacity CL TOPR Operating temperature MIN. +2.7 +3.0 0 TYP. –20 MAX. +3.6 +5.5 VLS 55 70 +75 UNIT V V V MHz pF ˚C NOTE : 1. The applicable voltage on any pin with respect to GNDL and GNDA (0 V). 10 NOTE 1 NOTE 1, 2 LH168A ELECTRICAL CHARACTERISTICS DC Characteristics PARAMETER Input "Low" voltage VIL Input "High" voltage VIH Output "Low" voltage Output "High" voltage VOL VOH Input "Low" current IILL Input "High" current (VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C) SYMBOL CONDITIONS IILH1 IILH2 Supply current (In operation mode) ICC1 Supply current (In standby mode) ICC2 Supply current (In operation mode) ILS1 Supply current (In standby mode) ILS2 Output voltage range VOUT Deviations between VOD output voltage pins Output current IO1, IO2 Resistance between RGMA reference voltage input pins APPLICABLE PINS MIN. TYP. MAX. UNIT XA0-XA5, YA0-YA5, ZA0-ZA5, GNDL 0.3VCC V XB0-XB5, YB0-YB5, ZB0-ZB5, VCC V SPIO, SPOI, CK, LS, LBR 0.7VCC IOL = 0.3 mA GNDL GNDL + 0.4 V SPIO, SPOI IOH = –0.3 mA VCC – 0.4 VCC V XA0-XA5, YA0-YA5, ZA0-ZA5, XB0-XB5, YB0-YB5, ZB0-ZB5, 1 µA SPIO, SPOI, CK, LS, LBR, POL1, POL2 XA0-XA5, YA0-YA5, ZA0-ZA5, 1 µA XB0-XB5, YB0-YB5, ZB0-ZB5, SPIO, SPOI, CK, LS, LBR POL1, POL2 400 µA fCK = 55 MHz VCC-GNDL 12 mA fLS = 50 kHz (Data sampling state) fCK = 55 MHz fLS = 50 kHz VCC-GNDL 4 mA SPI = GND is fixed. (Standby state) fCK = 55 MHz 10 mA VLS-GNDA fLS = 50 kHz (Data sampling state) fCK = 55 MHz fLS = 50 kHz VLS-GNDA 9 mA SPI = GND is fixed. (Standby state) GNDA + 0.1 VLS – 0.1 V XO1-ZO128 –20 20 V1-V10 10 20 50 mV µA 30 NOTE 1 2 k$ NOTES : 1. Criterion of evaluating voltage deviations. (a) Between output voltage pins Measuring values : Output voltage value at the time after 10 µs at the rising edge of LS. (Average of several times) (Conditions) Output load capacity is 70 pF. In a state when the reference voltage is fixed. Expecting values : Calculated following these specifications. (Conditions) In a state when the reference voltage is fixed. (b) Between LCD drivers Measuring values : Applicable to (a). (Conditions) Applicable to (a). Expecting values : Applicable to (a). (Conditions) Applicable to (a). Each input voltage between the LCD drivers must be made perfectly equal by connecting corresponding reference voltage input pins. 2. IO1 : Applied voltage = 3.0 V for output pins XO1 to ZO128. Output voltage = 2.5 V for output pins XO1 to ZO128. VLS = 5.0 V IO2 : Applied voltage = 2.0 V for output pins XO1 to ZO128. Output voltage = 2.5 V for output pins XO1 to ZO128. VLS = 5.0 V 11 LH168A AC Characteristics PARAMETER Clock frequency "H" level pulse width "L" level pulse width (VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C) SYMBOL CONDITIONS fCK APPLICABLE PINS tCR Input fall time tCF CK Data setup time tSUD XA0-XA5, YA0-YA5, ZA0-ZA5, XB0-XB5, YB0-YB5, ZB0-ZB5, Data hold time tHD POL1, POL2 Start pulse setup time tSUSP Start pulse hold time tHSP Start pulse width tWSP Start pulse output delay time LCD drive output delay time 1 LCD drive output delay time 2 CL = 10 pF tDO1 CL = 70 pF UNIT MHz ns ns 4 ns 4 ns 4 ns 0 ns 4 0 ns ns 1 -------fCK ns 12 ns 3 µs 10 µs XO1-ZO128 tDO2 tLSSP LS signal-CK signal hold time tHLS width MAX. 55 4 SPIO, SPOI tDSP LS signal-SPI signal set up time LS signal "H" level TYP. 4 tCWH tCWL Input rise time MIN. CL = 70 pF LS tWLS 12 1 -------fCK ns 9 ns 1 -------fCK ns LH168A Timing Chart 1 fCK tCWH CK tCWL 1 tSUSP tHSP tCR 2 tCF SPIO Input (SPOI) tWSP XA0-XA5 XB0-XB5 YA0-YA5 YB0-YB5 ZA0-ZA5 ZB0-ZB5 POL1 POL2 tSUD tHD 1 LAST – 1 CK 2 LAST tDSP SPIO Output (SPOI) tHLS tWLS LS tLSSP tSUSP tHSP SPIO Input (SPOI) tDO1 Target voltage ±(VLS x 0.1) XO1-ZO128 Target voltage (6-bit accuracy) tDO2 13 0.20 LH168AF 0.35±0.03 0.20 ±0.03 13.6 (SR) 14.0 (SL) [0.80] 27.1 (SL) 27.0 (SL) [P0.090 x (296 – 1) = 26.55 W0.045] 27.6 (Backside PI coating) [31.0] [28.6 (E.L.)] 14.0 (SL) 13.6 (SR) NC GNDA COM2 COM1 1.5 (SL) 0.6 (SL) 1.4 (Backside PI coating) 0.8 (SL) 1.5 (SL) 5.0±0.7 5.35±0.05(Hole) 6.9 (SR) 7.2 (SL) [9.2 (E.L.)] [16.8 (E.L.)] [10.0] 10.875 (SL) 3.4 (SL) 4.8 (SR) 6.6±0.05(Mark) [7.6 (E.L.)] UPILEX is a trademark of UBE INDUSTRIES, LTD.. 14 8.3 (SR) 2.8 (SL) 4.3 (SL) 3.1 [2.8TYP. (2.5MIN.)] ZO1 YO1 XO1 NC NC NC NC COM2 COM2 COM2 COM1 COM1 COM1 0.40±0.02 0.60±0.02 48 mm Super wide 5 pitches Substrate UPILEX S75 Adhesive #7100 USLP 18 µm Cu foil [thickness] Solder resist Epoxy resin/Polyimide ø Tape Material 1.1MAX. Total 0.75MAX. Backside PACKAGE Tape width Tape type Perforation pitch COM4 COM4 COM4 COM3 COM3 COM3 NC NC NC NC ZO128 YO128 XO128 ø Tape Specification Flexible slit 4.5MAX. (Resin area) 2.1MAX. (Resin area) 2.4MAX. (Resin area) 27.6 (Backside PI coating) [28.6 (E.L.)] [31.0] 13.7 (SR) 4.75±0.05 0.2MAX. Pattern side Chip center Sprocket center NC 13.7 (SR) (Resin area) 2-Ø1.0 (PI) 2-R0.8 (SR) Flexible slit COM4 P0.065 x (404 – 1) = 26.195±0.04 W0.032 [P0.065 x (410 – 1) = 26.585±0.04 W0.032] 27.0 (SL) ±0.04 (Mark) 27.2 MAX. 9.5 (SL) 1.42±0.05 20.4 0.20±0.03 1.42±0.05 GNDA Ø2.0 (Good device hole) 25.6±0.05 (Holes) P0.40 x (64 – 1) = 25.2±0.04 W0.020±0.03 5.6 (SL) 5.6 (SL) 10.0 (SL) 5.0 (SL) 5.0 (SL) NC COM4 COM3 GNDA VLS LBR LS ZB0 ZB1 ZB2 ZB3 ZB4 ZB5 YB0 YB1 YB2 YB3 YB4 YB5 XB0 XB1 XB2 XB3 XB4 XB5 SPIO V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 NC VCC CK POL2 POL1 GNDL SPOI ZA0 ZA1 ZA2 ZA3 ZA4 ZA5 YA0 YA1 YA2 YA3 YA4 YA5 XA0 XA1 XA2 XA3 XA4 XA5 VLS GNDA COM2 COM1 NC 9.5 (SL) 1.0 (SL) 0.20±0.03 0.20 0.35±0.03 [0.80] 0.60±0.02 0.40±0.02 1.0 (SL) 17.0±0.7 Device center 48.175±0.2 44.86 Film center PACKAGES FOR LCD DRIVERS (Unit : mm) COM3 1.4 (Backside PI coating) 2.1 (SL) 1.8 0.8 (SL) [0.60]