LH1692 300-output TFT-LCD Gate Driver IC LH1692 DESCRIPTION PIN CONNECTIONS The LH1692 is a 300-output TFT-LCD gate driver IC. TOP VIEW 319-PIN TCP 1 OG1 2 OG2 3 OG3 • Number of LCD drive outputs : 300 • LCD drive output sequence : Output shift direction can be selected OG1/OG300 or OG300/OG1 • Cascade connection : Max. 4 cascades (internal counting system) • Usable with both positive/negative power supplies • Output mode selection – Normal mode (1-pulse scanning) – Continuous 2-pulse mode (2-pulse scanning) – Jumping 2-pulse mode (2-pulse scanning) • LCD drive voltage : +16.0 to +42.0 V • Operating temperature : –30 to + 85 ˚C • Package : 319-pin TCP (Tape Carrier Package) VDD VEE VSS VCC VLS TEST1 TEST2 CKV SPV CE1 CE2 R/L MODE1 MODE2 VLS VCC VSS VEE VDD 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 CHIP SURFACE FEATURES 298 OG298 299 OG299 300 OG300 NOTE : Doesn't prescribe TCP outline. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LH1692 PIN DESCRIPTION PIN NO. 1 to 300 SYMBOL OG1-OG300 I/O O DESCRIPTION 301, 309 VDD – Power supply pins for LCD drive 302, 318 VEE – Power supply pins for LCD drive 303, 317 VSS – Power supply pins for logic system 304, 316 VCC – Power supply pins for logic system 305, 315 VLS 306, 307 MODE2, MODE1 – I Power supply pins for input level shifter Output mode selection pins 308 R/L I 309, 310 CE2, CE1 I Cascade sequence setting pins 311 312 SPV CKV I I Vertical scanning start pulse input pin Vertical shift clock input pin 313, 314 TEST2, TEST1 I IC test pins LCD drive output pins Pin for selecting bi-directional shift register and setting cascade sequence BLOCK DIAGRAM MODE2 306 BI-DIRECTIONAL SHIFT REGISTER MODE1 307 R/L 308 1 300 CE2 309 CONTROL LOGIC CE1 310 LEVEL SHIFTER SPV 311 1 300 CKV 312 TEST2 313 OUTPUT CIRCUIT TEST1 314 1 301 319 305 315 304 316 302 318 303 317 VDD VDD VLS VLS VCC VCC VEE VEE VSS VSS 2 300 1 300 OG1 OG300 LH1692 FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK Control Logic FUNCTION Used to create signals necessary for mode selecting signal, cascade sequence setting Bi-directional Shift signal and for operation of bi-directional shift register. Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive Register output sequence of OG1/OG300 direction or OG300/OG1 direction. , Used as circuit which shifts LCD drive output signals transferred by bi-directional shift Level Shifter Output Circuit register to VDD-VEE level. Configured with output buffers to output VDD-VEE level. INPUT/OUTPUT CIRCUITS VLS I To Internal Circuit Level Shifter Internal Logic (VLS-0 V/VCC-VSS) (VCC-VSS) VSS ¿Applicable pins¡ SPV, CKV, CE1, CE2, R/L, MODE1, MODE2, TEST1, TEST2 Fig. 1 Input Circuit VDD O From Internal Circuit (VDD-VEE) ¿Applicable pins¡ OG1-OG300 VEE Fig. 2 Output Circuit 3 LH1692 FUNCTIONAL DESCRIPTION Pin Functions SYMBOL VDD FUNCTION Used as power supply pin for high level LCD drive. VLS Used as power supply pin for input level shifters. VCC Used as power supply pin for logic system, normally connected to VSS + 5.0 V. VEE Used as power supply pin for low level LCD drive. Used as logic system power supply pin. VSS CKV Used as vertical shift clock pulse input pin. SPV Used as vertical scanning start pulse input pin. (At least, input one cycle of CKV during "L" period of SPV.) Used as input pins for selecting output mode. Output mode is set as shown in the table below by setting MODE1 pin and MODE2 pin. MODE1 MODE2 H L H H Normal mode (1-pulse scanning) Continuous 2-pulse mode H L L L Jumping 2-pulse mode Set all outputs to VEE level. MODE1 MODE2 Output mode Used as input pin for selecting the shift direction of bi-directional shift register and for setting the sequence of cascade connection. R/L LCD drive outputs shift from OG1 to OG300 when set to "H". LCD drive outputs shift from OG300 to OG1 when set to "L". At the same time, cascade sequence is set as shown in the table below. Used as input pins for setting of chip cascade sequence. (Max. 4 cascades) Cascade sequence CE2 CE1 R/L = "H" R/L = "L" CE1 CE2 H L H H 1st 2nd 4th 3rd H L L L 3rd 4th 2nd 1st TEST1 With above setting, sets the cascade sequence signal inside the IC. Used as input pins for IC testing. TEST2 Must be set to "H". OG1-OG300 Used as output pins for LCD drive output, and which output data at 2 levels. • Selecting data is output at VDD level . • Non-selecting data is output at VEE level . 4 LH1692 Functional Operations (1) Example of Cascade Sequence (One Side Assembled) OG1 CE1 = "H" CE2 = "H" OG300 OG1 CE1 = "L" CE2 = "H" OG300 TFT-LCD Panel OG1 CE1 = "H" CE2 = "L" OG300 OG1 CE1 = "L" CE2 = "L" OG300 Scanning Direction When R/L = "L". Scanning Direction When R/L = "H". * At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H", jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L", continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and output VEE level is set when MODE1 = "L" and MODE2 = "L". 5 LH1692 (2) Example of Input/Output Timing (For 1st Cascade Sequence) CKV SPV OG1 OG300 OG2 OG299 OG3 OG298 OG1 OG300 OG2 OG299 OG3 OG298 (1-pulse Mode) (Jumping 2-pulse Mode) R/L = "H" R/L = "L" 6 LH1692 (3) Example of Cascade Sequence (Both Side Assembled) OG1 CE1 = "H" CE2 = "H" OG300 OG300 CE1 = "H" CE2 = "L" OG1 TFT-LCD Panel OG1 OG300 CE1 = "L" CE2 = "H" CE1 = "L" CE2 = "L" OG300 OG1 Scanning Direction When R/L = "L". Scanning Direction When R/L = "H". * At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H", jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L", continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and output VEE level is set when MODE1 = "L" and MODE2 = "L". 7 LH1692 (4) Example of Input/Output Timing (For 1st Cascade Sequence) CKV SPV OG1 OG300 OG2 OG299 OG3 OG298 OG1 OG300 OG2 OG299 OG3 OG298 (1-pulse Mode) (Continuous 2-pulse Mode) R/L = "H" R/L = "L" 8 LH1692 PRECAUTIONS Logic system power supply (VLS), internal logic system power supply (VSS, VCC; VCC > VSS) and low-level LCD drive power supply (VEE) / logic input / high-level LCD drive power supply (VDD) Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. When disconnecting the power supply, follow the reverse sequence. Since the logic state of the internal circuit is unstable immediately after the logic system power is supplied, input CKV and SPV while initializing the internal circuit (minimum input clock number is 300 CKV). MODE1 and MODE2 should be set to "L" during the initializing period for setting the LCD drive output to VEE level. Logic system power supply (VLS) or internal logic system power supply (VSS, VCC; VCC > VSS) / logic input / LCD drive power supply (VEE, VDD) It is possible to set voltage VEE to the same as VSS. When connecting the power supply when VEE = VSS, observe the following sequence and the recommended sequence figure shown below. VDD VLS Input 0V VCC VSS, VEE Maximum ratings When connecting or disconnecting the power, this IC must be used within the range of the absolute maximum ratings. Input pin setting Input pins other than CKV and SPV must be set to "H" or "L" level. 9 LH1692 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage SYMBOL VDD APPLICABLE PINS VDD RATING –0.3 to +45.0 UNIT V VLS VLS –0.3 to +7.0 V VCC – VSS VCC, VSS –0.3 to +7.0 V VEE – VSS VEE, VSS –0.3 to +45.0 V VDD, VEE, VSS –0.3 to +45.0 V –0.3 to VLS + 0.3 V –45 to +125 ˚C VDD – VEE (VSS) Input voltage Storage temperature VIN CKV, SPV, CE1, CE2, R/L, MODE1, MODE2, TEST1, TEST2 TSTG NOTES : 1. TA = +25 ˚C 2. The maximum applicable voltage on any pin with respect to 0 V. RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage MIN. +5.5 +3.0 TYP. +9.0 +5.0 VCC – VSS +3.0 +5.0 SYMBOL VDD VLS VEE – VSS VDD – VEE Input voltage (VSS) VIN Operating temperature TOPR 0 +16.0 +25.0 MAX. +42.0 +5.5 UNIT V V +5.5 V +11.0 V +42.0 V 0 VLS V –30 +85 ˚C NOTES : 1. The applicable voltage on any pin with respect to 0 V. 2. Ensure that voltages are set as follows. VSS, VEE ≤ 0 V VCC – VSS = VLS±0.1 V (For 3.3 V specifications) VCC – VSS = VLS±0.2 V (For 5.0 V specifications) VCC ≤ VLS 10 NOTE 1, 2 NOTE 1, 2 LH1692 When power supply pins are set as shown below, the LH1692 can output positive voltage and negative voltage to LCD drive output. Example 1 : For Positive Voltage Output LCD Drive Output VDD VLS, VCC Input Internal Logic VSS, VEE (0 V) Example 2 : For Negative Voltage Output VDD, VLS LCD Drive Output Input 0V VCC Internal Logic VSS, VEE 11 LH1692 ELECTRICAL CHARACTERISTICS DC Characteristics PARAMETER Input "Low" voltage (VLS = +3.3±0.3 V (= VCC – VSS), VEE = VSS, TOPR = –30 to +85 ˚C) SYMBOL CONDITIONS VIL Input "High" voltage VIH Output "Low" voltage VOL IOL = 0.4 mA Output "High" voltage VOH IOH = –0.4 mA IIL VI = 0 V VI = VLS Input "Low" current Input "High" current IIH APPLICABLE PINS CKV, SPV, MODE1, OG1-OG300 CKV, SPV, MODE1, MODE2, CE1, CE2, R/L UNIT V V 5.0 5.0 µA µA µA µA VDD – 0.4 V ILS For 1-pulse mode 80 µA 50 µA 130 µA 200 90 µA µA IEE 50 µA IDD 130 µA ILS ICC For jumping 2-pulse mode ILS For continuous 200 µA ICC 2-pulse mode 90 90 µA µA IEE NOTE V VEE + 0.4 ICC IDD Supply current (3) MAX. 0.2VLS 60 130 IEE Supply current (2) TYP. MODE2, CE1, CE2, R/L 0.8VLS IDD Supply current (1) MIN. 1 2 3 4 NOTES : 1. All input pins : 3.3 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz Other input pins : 3.3 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 3.3 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 3.3 V All output pins are opened. 12 LH1692 (VLS = +5.0±0.5 V (= VCC – VSS), VEE = VSS, TOPR = –30 to +85 ˚C) PARAMETER Input "Low" voltage SYMBOL CONDITIONS VIL Input "High" voltage VIH Output "Low" voltage VOL IOL = 0.4 mA Output "High" voltage VOH IOH = –0.4 mA IIL VI = 0 V VI = VLS Input "Low" current Input "High" current IIH APPLICABLE PINS CKV, SPV, MODE1, Supply current (2) OG1-OG300 CKV, SPV, MODE1, MODE2, CE1, CE2, R/L MAX. 0.2VLS UNIT V VEE + 0.4 V V 5.0 5.0 µA µA µA µA VDD – 0.4 ILS For ICC 1-pulse mode 100 µA IEE 50 µA IDD 130 µA 300 150 µA µA 50 µA ILS ICC For jumping 2-pulse mode IDD 130 µA ILS For continuous 300 µA ICC 2-pulse mode 150 µA 50 µA IEE NOTE V 60 180 IEE Supply current (3) TYP. MODE2, CE1, CE2, R/L 0.8VLS IDD Supply current (1) MIN. 1 2 3 4 NOTES : 1. All input pins : 5 V 2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz Other input pins : 5 V All output pins are opened. 3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz MODE2 : 0 V Other input pins : 5 V All output pins are opened. 4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs SPV : Frequency = 60 Hz MODE1 : 0 V Other input pins : 5 V All output pins are opened. 13 LH1692 AC Characteristics PARAMETER Clock frequency "L" clock pulse width (VLS = +3.3±0.3 V (= VCC – VSS), VEE = VSS, TOPR = –30 to +85 ˚C) SYMBOL CONDITIONS fCKV tWL Clock rise time tRCKV Clock fall time tFCKV Data setup time tSU Data hold time tH Pulse rise time tRSPV Pulse fall time tFSPV Output transfer delay time tD Output rise time Output fall time tR tF APPLICABLE PINS CKV CKV, SPV MIN. TYP. 0.5 UNIT kHz µs 100 ns 100 ns ns 100 300 SPV CL = 500 pF MAX. 100 OG1-OG300 100 ns ns 100 ns 3.0 µs 1.0 1.0 µs µs (VLS = +5.0±0.5 V (= VCC – VSS), VEE = VSS, TOPR = –30 to +85 ˚C) PARAMETER SYMBOL CONDITIONS Clock frequency fCKV "L" clock pulse width tWL Clock rise time tRCKV Clock fall time tFCKV Data setup time tSU Data hold time tH Pulse rise time tRSPV Pulse fall time tFSPV Output transfer delay time tD Output rise time Output fall time tR tF APPLICABLE PINS CKV CKV, SPV SPV CL = 500 pF OG1-OG300 14 MIN. TYP. MAX. 100 0.5 UNIT kHz µs 100 ns 100 ns ns 100 300 100 ns ns 100 ns 2.0 µs 1.0 1.0 µs µs LH1692 Timing Chart tFCKV 90% CKV 10% tSU tFSPV SPV 90% 10% tWL tRCKV 90% 50% 50% 50% 50% 50% 50% 10% tH tRSPV 90% 10% tD 90% 50% tD 10% tR tD 50% 50% OG1-OG300 (1-pules Mode) OG1-OG300 (Continuous 2-pulse Mode) tD 50% OG1-OG300 (Jumping 2-pulse Mode) 15 tD 50% tD 90% 50% 10% tF LH1692F VSS VDD VEE COM1 COM2 COM1 31.0 (SL) 5.0±0.7 (Good device hole) VCC VLS 5.0 (SL) [5.5 (E.L.)] 6.5 (SR) 8.5±0.05 [10.0 (E.L.)] [15.5 (E.L.)] UPILEX is a trademark of UBE INDUSTRIES, LTD.. 16 VCC VSS 10.0 (SL) 5.0 (SL) [3.5TYP. (3.2MIN.)] 2.7 (SR) 2.0 (SL) 3.0 (SL) 0.4±0.02 0.6±0.02 UPILEX S75 #7100 USLP 18 µm Epoxy resin COM4 OG238 OG239 OG300 DUMMY COM2 COM1 COM1 Substrate Adhesive Cu foil [thickness] Solder resist ø Tape Material 22.7 (SL) 5.3MAX. (Resin area) Chip center Sprocket center 2-Ø1.5 (Cu hole) 1.0 (SL) Ø1.9 (PI) COM4 COM4 COM3 DUMMY OG1 OG2 OG3 70 mm Wide 4 pitches VEE [46.0 (E.L.)] VDD 22.1 (SR) COM3 44.6±0.085 (Mark) P0.14 x (308 – 1) = 42.98±0.085 W0.07±0.02 20.4MAX. (Resin area) 0.4±0.02 2-Ø2.7 (Cu) 1.981±0.05 1.2MAX. Total 0.75MAX. Backside 0.3MAX. Pattern side PACKAGE Tape width Tape type Perforation pitch MODE2 1.981±0.05 ø Tape Specification R/L 0.4±0.02 0.6±0.02 MODE1 36.0±0.06 4.75±0.05 22.7 (SL) CE2 22.1 (SR) CE1 P1.2 x (25 – 1) = 28.8±0.06 W0.40±0.02 VLS 1.0 (SL) Ø2.0 (Good device hole) CKV Device center TEST2 26.75±0.7(Good device hole) SPV 63.949±0.12 TEST1 Film center PACKAGES FOR LCD DRIVERS (Unit : mm) COM4