E2B0033-27-Y2
¡ Semiconductor
MSM6262-xx
¡ Semiconductor
This version:MSM6262-xx
Nov. 1997
Previous version: Mar. 1996
DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER
GENERAL DESCRIPTION
The MSM6262-xx is a dot matrix LCD controller which is fabricated by OKI's low power
consumption CMOS silicon gate technology. In combination with 8-bit microcontroller, the
MSM6262-xx can control the dot matrix character type LCD module.
The MSM6262-xx is provided with a serial data transfer output. So, a maximum of 160 characters
can be controlled by combining this device with the MSM5259, MSM5839C, or MSM5260.
The MSM6262-xx is recommended for use in an LCD panel which is capable of displaying 81 to
160 characters. If an LCD panel of which display capacity is 80 characters or less is used, the
MSM6222B-xx is recommended.
The MSM6262-xx is best suited to be used as an LCD controller for applications such as electronic
typewriters, POS system terminals, and data banks.
FEATURES
• Dot matrix LCD controller/driver for three different font configuration
(5 x 7 dots, 5 x 11 dots and 5 x 12 dots)
• Up to 160 characters can be controlled
(Display data RAM ... 160 x 9-bit)
• On-chip character generator ROM (CGROM) for 256 different characters
5 x 7 dots ... 128 characters
5 x 11 dots ... 96 characters
5 x 12 dots ... 32 characters
• On-chip character generator RAM (CGRAM) (32 x 8-bit)
5 x 8 dots ... 4 kinds
5 x 12 dots ... 2 kinds
• Easy interface with Z80, 6809, 80C49, and 80C51
• Underline function
• Shift function for g, i, p, q and y
• Selectable driving duty
Duty
Font Configuration (dots)
Cursor Display
Display (characters x lines)
1/16
5x 7
Available
80 x 2
1/24
5 x 11
Available
80 x 2
1/32
5x 7
Available
40 x 4
1/48
5 x 11
Available
40 x 4
• Package :
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6262-xxGS-BK)
xx indicates code number.
1/52
LCD driving
voltage
V1
V4
V5
TEST1
TEST2
TEST3
DB0 - DB7
68 series/80 series
CS
R/W (WR)
E (RD)
A0
A1
RESET
VDD
VSS
OSC1
OSC2
OSC3
8
Input/
Output
buffer
2
8
8
6
9
Busy
flag
Data
register
(DR)
Instruction
9
register
(I/R)
9
8
5
Character
generator
RAM
(CGRAM),
256 bits
Instruction
decoder
8
5
1
Parallel / Serial converter
5
Character generator
ROM (CGROM),
11,680 bits
8
9
Display data RAM
(DDRAM)
160 x 9 bits
8
Address counter (ADC)
1
Cursor
blink,
under-line
function
control
8
48-bit
shift
register
Timing generator
48
COMMON
signal
driver
2
48
BUSY1 OUT
BUSY2 OUT
DO
COM1 - COM48
CP
LOAD
DF
¡ Semiconductor
MSM6262-xx
BLOCK DIAGRAM
2/52
¡ Semiconductor
MSM6262-xx
INPUT AND OUTPUT CONFIGURATION
Input pin
VDD
To the inside of the device
Applicable pins: OSC1, 68 series/80 series, CS
R/W (WR), E (RD)
A0, A1
VDD
VDD
To the inside of the device
Applicable pin: RESET
Input /Output pin
VDD
VDD
From the inside of the device
To the inside of the device
Applicable pins: OSC2, OSC3
VDD
VDD
To the inside of of the device
VDD
From the inside of the device
Applicable pins: DB0 - DB7
3/52
¡ Semiconductor
MSM6262-xx
Output pin
From the inside of the device
Applicable pins: CP, LOAD, DF, DO,
BUSY1 OUT, BUSY2 OUT
4/52
¡ Semiconductor
MSM6262-xx
65
66
67
68
69
70
71
72
73
74
75
76
77
78
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
COM 29
COM 28
COM 27
COM 26
COM 25
COM 24
COM 23
COM 22
COM 21
COM 20
COM 19
COM 18
COM 17
COM 16
COM 15
COM 14
COM 13
COM 12
COM 11
COM 10
COM 9
COM 8
COM 7
COM 6
40
51
15
39
52
14
38
53
13
37
54
12
36
55
11
35
56
10
34
57
9
33
58
8
32
59
7
31
60
6
30
61
5
29
62
4
28
3
27
63
26
64
2
25
1
DB7
BUSY 1 OUT
BUSY 2 OUT
DF
LOAD
CP
DO
VDD
V1
V4
V5
COM 1
COM 2
COM 3
COM 4
COM 5
COM 46
COM 47
COM 48
VSS (GND)
OSC1
OSC2
OSC3
TEST1
TEST2
TEST3
RESET
68 series/80 series
CS
E (RD)
R/W (WR)
A0
A1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
79
80
COM 45
COM 44
COM 43
COM 42
COM 41
COM 40
COM 39
COM 38
COM 37
COM 36
COM 35
COM 34
COM 33
COM 32
COM 31
COM 30
PIN CONFIGURATION (TOP VIEW)
80-Pin Plastic QFP
5/52
¡ Semiconductor
MSM6262-xx
PIN DESCRIPTIONS
Symbol
OSC1
Type
I/O
OSC2, OSC3
RESET
68 series/80 series
CS
I
I
I
R/W (WR)
I
Description
Clock oscillating pins required for internal operation upon receipt
of the LCD drive signal and CPU instruction.
Reset pin
Selection pin for either 68 series CPU or 80 series CPU
Chip select pin. By setting CS at "L" level, MSM6262-xx
is set at selecting condition.
R/W pin of 68 series CPU shall be connected to this pin,
while WR pin shall be connected to this pin in the case of
80 series CPU.
E (RD)
I
E pin of 68 series CPU shall be connected to this pin,
while RD pin shall be connected to this pin in the case of
80 series CPU.
A0, A1
DB0 - DB7
I
I/O
The address bus of CPU shall be connected to these pins.
Instruction code is set by these pins.
The data bus of CPU shall be connected to these pins. These
pins are used to set the data of the instruction or to read
the data.
TEST1 - TEST3
I
Test pins. Normally these pins should be set at VSS or
open.
VDD, VSS
—
V1, V4, V5
DO
—
O
Serial data output pin for SEGMENT drivers
CP
O
Clock pulse output pin. The clock output from this pin
Voltage supply pins. VDD is also used for the common
bias voltage level to drive the LCD.
Common bias voltage input pins to drive the LCD
enables the character pattern data, which is output from
DO, to input to the SEGMENT drivers (MSM5839C or MSM5259).
LOAD
O
Load signal output pin. The character pattern data to
the SEGMENT drivers, which was output from DO and
CP, is loaded to the LCD output of the SEGMENT
drivers, synchronized with the COMMON signal.
DF
COM1 - COM48
O
O
B-type AC signal output pin to drive the LCD
COMMON signal output pins to drive the LCD
BUSY1 OUT
O
This pin shows the internal condition of MSM6262-xx.
"H" shows that MSM6262-xx is in internal operation,
while "L" shows that MSM6262-xx is ready to receive
the instruction from the CPU.
BUSY2 OUT
O
This pin shows that MSM6262-xx is in internal operation
based on the instruction from the CPU, or MSM6262-xx
is in display revising operation based on the instruction
from the CPU.
"H" shows that MSM6262-xx is in internal operation,
while "L" shows that the display on the LCD has been
established and the MSM6262-xx is ready to receive an
instruction.
6/52
¡ Semiconductor
MSM6262-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Supply Voltage
for Driving LCD
Symbol
Condition
Rating
Unit
Applicable Pin
VDD
Ta = 25°C, VDD–VSS
–0.3 to +7.0
V
VDD, VSS
V1, V4, V5
Ta = 25°C
V
V1, V4, V5
VDD – 12 to
VDD + 0.3
OSC1, RESET
Input Voltage
VIN
Ta = 25°C
–0.3 to VDD + 0.3
V
68 series / 80 series
CS, A0, A1, R/W (WR)
E (RD), DB0 - DB7
Power Dissipation
Storage Temperature
PD
Ta = 25°C
500
mW
TSTG
––
–55 to +125
°C
––
––
Unit
Applicable Pin
VDD, GND
RECOMMENDED OPERATING CONDITOINS
Parameter
Supply Voltage
LCD Driving Voltage
Operating Temperature
Symbol
VDD
VLCD
Top
Condition
––
Range
4.5 to 5.5
V
1/5 bias, VDD–V5
3.0 to 11
V
1/6, 1/7 bias, VDD–V5
4.0 to 11
4.5 to 11
V
V
VDD, V1, V4, V5
1/8 bias, VDD–V5
––
–20 to +75
°C
––
Note: For bias, refer to *3 in the section "DC Characteristics".
7/52
¡ Semiconductor
MSM6262-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5 V , Ta = –20 to +75°C)
Applicable Pin
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
VIH1
––
2.2
––
VDD
V
"L" Input Voltage
VIL1
––
–0.3
––
0.7
V
"H" Output Voltage
VOH1
IO = –250 mA
2.4
––
––
V
"L" Output Voltage
VOL1
IO = 1.8 mA
––
––
0.4
V
"H" Input Voltage
VIH2
––
VDD–0.8
––
VDD
V
"L" Input Voltage
VIL2
––
–0.3
––
0.8
V
OSC1, RESET
68series/80series
"H" Output Voltage
VOH2
IO = –500 mA
0.85 VDD
––
––
V
DO, LOAD, DF
"L" Output Voltage
VOL2
IO = 500 mA
––
0.15 VDD
V
"H" Output Voltage
VOH3
IO = –1 mA
––
––
V
"L" Output Voltage
VOL3
IO = 1 mA
––
––
0.15 VDD
V
"H" Output Voltage
"L" Output Voltage
VOH4
IO = –100 mA
2.4
––
––
V
VOL4
IO = 1.6 mA
––
––
0.4
V
BUSY1 OUT
BUSY2 OUT
COM Voltage Drop
VCOM
IO = ± 50 mA
––
––
2.9
V
COM1 - COM48
"H" Input Current
IILH1
VIN = VDD
––
––
1
mA
"L" Input Current
IILL1
VIN = VSS
––
––
–1
mA
CS, R/W (WR)
E (RD), A0, A1
OSC1, 68series/
80series
––
––
1.5
mA
IDD1
Supply Current
IDD2
LCD Driving
Voltage
"H" Input Current
"L" Input Current
*1.
*2.
*3.
VLCD
IILH2
IILL2
––
0.85 VDD
*1
*2
VDD = 5 V,
fOSC = 500 kHz
(RC oscillation)
VDD = 5 V,
*2
fIN = 500 kHz
(external oscillation)
––
––
1.5
mA
1/5 bias
3.0
––
11
V
VDD–V5
1/6-1/7
bias
4.0
––
11
V
1/8 bias
4.5
––
11
V
2
mA
–60
mA
VIN = VDD
DB0 - DB7
CP
VDD
*3
VIN = VSS,VDD = 5 V
CS, R/W (WR)
E (RD), A0, A1
DB0 - DB7
––
––
–8
–20
V1 , V4, V5
RESET
This is applicable to the voltage drop which is caused between VDD, V1, V4, V5 and COM1
- COM48 when a current of 50 mA is flowed in/out to/from all of COM1 - COM48. (When
the output level is either VDD or V1, it should be applied only when the current flows in.
When the output level is either V4 or V5, it should be applied only when the current flows
in.
In this case, +5V is applied to VDD and V1, while –6 V is applied to V4 and V5.)
This is applicable to the current which flows in to VDD under following conditions.
VDD = 5 V, VSS = 0 V, V1 = 2.8 V, V4 = -3.8 V, V5 = –6 V, No load, No interface with CPU
V1 to V5 should be set at as follows.
8/52
¡ Semiconductor
MSM6262-xx
No. of lines
(N)
Pin
2 lines
Fon
confit g
u
ration
4 lines
5x8
5 x 12
5x8
5 x 12
V1
1
VDD – –– VLCD
5
1
VDD – –– VLCD
6
1
VDD – –– VLCD
7
1
VDD – –– VLCD
8
V4
4
VDD – –– VLCD
5
5
VDD – –– VLCD
6
6
VDD – –– VLCD
7
7
VDD – –– VLCD
8
V5
VDD – VLCD
VDD – VLCD
VDD – VLCD
VDD – VLCD
VLCD = LCD driving voltage
AC Characteristics
Parameter
(VDD = 4.5 to 5.5V , Ta = –20 to +75°C)
Symbol
Input Frequency
fIN
Input Clock Duty
Condition
Min.
Typ.
Max.
Unit
*1, *2
300
500
700
kHz
fDUTY
*2
45
50
55
%
Input Clock Rise Time
tr
*2
––
––
100
ns
Input Clock Fall Time
tf
*2
––
––
100
ns
fCR
*3
300
500
700
kHz
––
––
1
mA
–45
–120
–250
mA
RC Oscillation
Frequency
"H" Input Current
IILH3
"L" Input Current
IILL3
*1
VIN = VDD
VIN = VSS
VDD = 5 V
Open
OSC3
*3
Open
OSC2
Rf
OSC1
OSC1, OSC2, OSC3
DB0 - DB7
OSC3
OSC2
Cf
Oscillation source
Applicable Pin
OSC1
OSC1
Rf = 39 kW ± 5%
Cf = 22 pF ± 10%
(Keep the wiring from
OSC1, OSC2, and
OSC3 to Rf and Cf
as short as possible.)
*2
TH
TL
VDD–0.8 V
VDD–0.8 V
0.5 VDD
0.5 VDD
0.8 V
0.5 VDD
0.8 V
tr
tf
TH
x 100%
fDUTY = –––––––
TH + TL
9/52
¡ Semiconductor
MSM6262-xx
TIMING DIAGRAM
Interface with 80 Series CPU
(VDD = 4.5 to 5.5V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Max.
Unit
Address Set-up Time
tSA1
110
––
ns
CS Set-up Time
tSA2
100
––
ns
WR "L" Pulse Width
tWWR
320
––
ns
RD "L" Pulse Width
tWRD
320
––
ns
WR, RD "H" Pulse Width
tWH
210
––
ns
Address Hold Time
tHA1
25
––
ns
CS Hold Time
tHA2
25
––
ns
Data Set-up Time
tSWD
300
––
ns
Data Hold Time (Write operation)
tHWD
20
––
ns
WR, RD Fall Time
tf
––
25
ns
WR, RD Rise Time
tr
––
25
ns
Data Delay Time
tSRD
––
190
ns
Data Hold Time (Read operation)
tHRD
0
––
ns
Busy Output Delay Time
tBD
––
410
ns
10/52
¡ Semiconductor
MSM6262-xx
Write operation
VIH
VIL
A0,A1
VIH
VIL
tSA1
tHA1
CS
VIL
VIL
tW WR
tSA2
tHA2
tWH
R/W (WR)
VIH
VIL
VIH
VIL
tf
tr
tSWD
VIH
VIL
DB0 - DB7
VIH
tHWD
Valid data
VIH
VIL
tBD
VOH
BUSY 1 OUT, BUSY 2 OUT
Read operation
VIH
VIL
VIH
VIL
A0,A1
tSA1
tHA1
CS
VIL
VIL
tWRD
tSA2
tHA2
tWH
E (RD)
VIH
VIL
VIH
VIL
tf
tr
tHRD
tSRD
DB0 - DB7
VIH
VOH
VOL
Valid data
VOH
VOL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH
and VOL.
11/52
¡ Semiconductor
MSM6262-xx
• Interface with Z80
Z80
MSM6262-xx
VSS
RD
*
WR
*
IORQ
*
A0 - A15
DB0 - DB7
68 series/80 series
E (RD)
R/W (WR)
Address
Decoder
*
CS
*
A0, A1
DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
12/52
¡ Semiconductor
MSM6262-xx
• Interface with 80C49
MSM80C49
MSM6262-xx
VSS
68 series/80 series
RD
*
E (RD)
WR
*
R/W (WR)
ALE
DB0 - DB7
STB
8282
Address
Decoder
P20 - P22
*
CS
*
A0, A1
DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
• Interface with 80C51
MSM80C51
MSM6262-xx
VSS
68 series/80 series
RD
*
E (RD)
WR
*
R/W (WR)
ALE
P00 - P07
P20 - P22
STB
8282
Address
Decoder
*
CS
*
A0, A1
DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
13/52
¡ Semiconductor
MSM6262-xx
Interface with 68 Series CPU
(VDD = 4.5 to 5.5 V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Max.
Unit
Cycle Time
tC
500
––
ns
Address, R/W Set-up Time
tB1
100
––
ns
CS Set-up Time
tB2
90
––
ns
E signal "H" Pulse Width
tW
220
––
ns
E signal "L" Pulse Width
tL
210
––
ns
Address, R/W Hold Time
tA1
20
––
ns
CS Hold Time
tA2
20
––
ns
Data Set-up Time
tI
225
––
ns
Data Hold Time (Write operation)
tH
30
––
ns
E signal Rise Time
tr
––
25
ns
E signal Fall Time
tf
––
25
ns
Data Delay Time
tD
––
180
ns
Data Hold Time (Read operation)
tO
10
––
ns
Busy Output Delay Time
tBD
––
410
ns
14/52
¡ Semiconductor
MSM6262-xx
Write operation
VIH
VIL
A0, A1
VIH
VIL
tB1
tA1
VIL
R/W (WR)
VIL
tW
tL
VIH
VIH
VIL
VIL
tr
E (RD)
tI
tf
VIH
VIL
DB0 - DB7
tB2
VIL
tH
Valid data
VIH
VIL
tA2
tC
CS
VIL
VIL
tBD
VOH
Busy 1 OUT, Busy 2 OUT
Read operation
VIH
VIL
A0, A1
VIH
VIL
tB1
tA1
VIH
R/W (WR)
VIH
tW
tL
VIH
VIL
tr
E (RD)
VIH
VIL
tf
tD
VOH
VOL
DB0 - DB7
tB2
tO
Valid data
tC
VIL
VOH
VOL
tA2
CS
VIL
VIL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
15/52
¡ Semiconductor
MSM6262-xx
• Interface with 6809
6809
MSM6262-xx
O
VDD
E
*
E (RD)
R/W
*
R/W(WR)
*
CS
*
A0, A1
A0 - A15
DB0 - DB7
Address
decoder
68 series/80 series
DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
16/52
¡ Semiconductor
MSM6262-xx
Interface with Segment Driver
(VDD = 4.5 to 5.5 V, Ta = –20 to +75°C, fOSC = 500 kHz)
Parameter
Symbol
Min.
Max.
Unit
Clock "L" Pulse Width
tLW(CP)
400
—
ns
Clock "H" Pulse Width
tHW(CP)
400
—
ns
Do Set-up Time
tSETUP
200
—
ns
Do Hold Time
tHOLD
200
—
ns
LOAD, Clock Set-up Time
tCL
200
—
ns
LOAD, Clock Hold Time
tLC
100
—
ns
LOAD, "H" Pulse Width
tHW(L)
400
—
ns
tM
–500
500
ns
DF Delay Time
VOH
VOL
DO
VOH
VOL
tSETUP
CP
VOL
VOH
tLW(CP)
LOAD
VOL
tHOLD
VOH
THW(CP)
VOH
VOH
tCL
tLC
VOH
VOL
tHW(L)
tM
DF
VOH
VOL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
17/52
¡ Semiconductor
MSM6262-xx
Reset Waveform
(VDD = 4.5 to 5.5 V, Ta = –20 to +75°C)
Parameter
Symbol
Min.
Max.
Unit
"L" Input Time upon power on
tRR1
0.25
––
ms
"L" Input Width when in operation
tRLW
0.5
––
ms
Rise Time
tRR2
0.1
200
ms
4.5 V
VDD
0V
tRR1
tRR2
tRR2
VIH
RESET
VIL
VIH
VIL
VIL
tRLW
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
18/52
¡ Semiconductor
MSM6262-xx
FUNCTIONAL DESCRIPTION
1. Instruction Register (IR) and Data Register (DR)
The MSM6262-xx has two registers, instruction register (IR) and data register (DR).
IR is used to store the address code or instruction code of display data RAM (DD RAM) or
character generator RAM (CG RAM).
This register can be written by the CPU, but cannot be read out by the CPU.
DR is used to store the data to write into (or read out) the data to/from DD RAM or CG RAM.
The data written into DR by the CPU is automatically written into the DD RAM or CG RAM.
When an address code is written into IR, the data of the specified address is automatically
transferred to the DR from either DD RAM or CG RAM. By having the CPU subsequently read
the DR, it is possible to verify DD RAM or CG RAM data.
After the writing of DR by the CPU, the DD RAM or CG RAM of the next address is selected
to be ready for the next CPU writing.
Likewise, after the reading operation of the CPU, DD RAM or CG RAM data of the next
address is transferred to the DR, when CPU is ready for the next reading operation.
2. Busy Flag (BF)
When the output of BUSY 1 OUT is "H", MSM6262-xx is engaged in internal operation.
When the output of BUSY 2 OUT is "H", it indicates that MSM6262-xx is engaged in internal
operation or MSM6262-xx is engaged in the revising of the display starting line on the LCD.
(Refer to the instruction table.)
When the output of BUSY 1 OUT is "H", any input of new instruction is ignored. So, before
setting a new instruction, it is necessary to check whether BUSY 1 OUT and BUSY 2 OUT are
at "L".
3. Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read
and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to IR,
after deciding whether it is DD RAM or CG RAM, the address counter code is transferred from
IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the
ADC increments (or decrements) by 1 automatically as its internal operation.
19/52
¡ Semiconductor
MSM6262-xx
4. Timing Generator Circuit
This circuit generates the timing signal for the internal operation by CPU's instruction as well
as to operate the internal circuit of DD RAM, CG RAM, CG ROM and so forth. It also generates
the transfer signal to the SEGMENT driver (MSM5839C or MSM5259).
The internal operation accessed by the CPU and internal operation for LCD display is
independent.
So, a manipulation such as writing data from CPU to DD RAM will not have an influence such
as display flickering upon any part other than the display part to which the data is written.
5. Display Data RAM (DD RAM)
DD RAM is used to store the 8-bit character code (refer to Table 1) and 1-bit under-line data.
The address of DD RAM corresponds to the display position on the LCD. The correspondence
is described below.
DD RAM address (set to ADC) is described as hexadecimal.
DB7
ADC
DB6 DB5
DB4
DB3 DB2
DB1 DB0
MSB
LSB
Hexadecimal
Hexadecimal
Example: When DD RAM address is 3A
L
L
H
H
H
L
3
H
L
A
(1) Relation between DD RAM and display position in 2-line display mode
Digit
1
2
3
4
5
– – –
79
80
Display position
1st line
00
01
02
03
04
– – –
4E
4F
2nd line
80
81
82
83
84
– – –
CE
CF
DD RAM address
(hexadecimal)
Note: The address of the last digit of the first line and the first digit of the second line
does not have any continuity.
(2) When 2 pieces of MSM5389C(or MSM5259) are connected to MSM6262-xx, 32
characters can be displayed from the first digit to yhe 16th degit.
1st line
2nd line
Digit
1
2 3
00 01 02
80
{ or
81 82
4
5
03 04
6
7
05 06
8 9
07 08
10 11 12 13 14 15 16
09 0A 0B 0C 0D 0E 0F
83 84
85 86
87 88
89 8A 8B 8C 8D 8E
MSM5839C (1)
MSM5259 (1)
8F
MSM5839C (2)
MSM5259 (2) }
20/52
¡ Semiconductor
MSM6262-xx
When the display is shifted by an instruction, the relation between the DD RAM address and
the display position becomes as follows.
(Shift to the right)
1st line
Digit
1
2
4F 00
2nd line
CF
80
3
01
4
02
5
03
6
04
7
05
8 9
06 07
10 11
08 09
12 13 14 15 16
0A 0B 0C 0D 0E
81
82
83
84
85
86 87
88
8A 8B 8C 8D 8E
MSM5839C (1)
MSM5259 (1)
{ or
89
MSM5839C (2)
MSM5259 (2) }
1st line
01
02
03
04
05
06
07
08 09
0A 0B 0C 0D 0E
0F
10
2nd line
81
82
83
84
85
86
87
88 89
8A 8B 8C 8D 8E
8F
90
(Shift to the left)
(3) The maximum DD RAM capacity of MSM6262-xx is for 160 characters. So, up to 10 pieces
of MSM5839C (or MSM5259) can be connected in the case of 2-line display mode.
Digit
1
2
1st line
00
01 02
03 04
05 06
07 08
09 0A 0B 0C 0D 0E
0F 10
2nd line
80
81 82
83 84
85 86
87 88
89 8A 8B 8C 8D 8E
8F 90
{ or
3
4
5
6
7
8
9
MSM5839C (1)
MSM5259 (1)
10
11 12
13 14
15 16
MSM5839C (2)
MSM5259 (2)
17 18
– – –
73 74
11
– – –
48
91
– – –
C8 C9 CA CB CC CD CE CF
MSM5839C (3)-(9)
MSM5259 (3)-(9)
75 76 77 78
79 80
49 4A 4B 4C 4D 4E
4F
MSM5839C (10)
MSM5259 (10) }
(4) Relation between the DD RAM and display position in 4-line display mode
Digit
1
2
3
4
5
1st line
00
01
02
03
04
– – –
– – –
39
40
26
27
2nd line
3rd line
40
41
42
43
44
66
67
84
– – –
– – –
80
81
82
83
4th line
C0
C1
C2
C3
A6
A7
C4
– – –
E6
E7
Display position
DD RAM address
(hexadecimal)
Note: The address of the last digit of the previous line and the first digit of the
next line does not have any continuity.
21/52
¡ Semiconductor
MSM6262-xx
(5) When 2 pieces of MSM5839C (or MSM5259) are connected to MSM6262-xx, 64 characters
can be displayed from the first digit to the 16th digit.
Digit
1
2 3
1st line 00 01 02
2nd line 40 41 42
3rd line 80 81 82
4th line
4
5
03 04
6
7
05 06
8 9
07 08
10 11 12 13 14 15 16
09 0A 0B 0C 0D 0E 0F
43 44
45 46
47 48
49 4A 4B 4C 4D 4E
4F
83 84
85 86
87 88
89 8A 8B 8C 8D 8E
8F
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CB CF
MSM5839C (1)
MSM5259 (1)
{ or
MSM5839C (2)
MSM5259 (2) }
When the display is shifted by an instruction, the relation between the DD RAM address and
the display position becomes as follows.
(shift to right direction)
Digit
1
2 3
4
5
1st line 27 00 01 02 03
2nd line 67 40 41 42 43
6
04
7
05
8 9
06 07
10 11
08 09
12 13 14 15 16
0A 0B 0C 0D 0E
44
45
46 47
48
49
4A 4B 4C 4D 4E
3rd line
A7 80
84
85 86
88
89
8A 8B 8C 8D 8E
4th line
E7
81
82
83
87
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE
MSM5839C (1)
MSM5259 (1)
{ or
MSM5839C (2)
MSM5259 (2) }
1st line
01
02
03
04
05
06
07
08 09
0A 0B 0C 0D 0E 0F
10
2nd line
41
42
43
44
45
46
47
48 49
4A 4B 4C 4D 4E 4F
50
3rd line
81
82
83
84
85
86 87
88 89
8A 8B 8C 8D 8E 8F
90
C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF
(shift to left direction)
D0
4th line
(6) The maximum DD RAM capacity of MSM6262-xx is for 160 characters. So, up to 5pieces
of MSM5839C (or MSM5259) can be connected in the case of 4-line display mode.
Digit
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18
– – –
33 34 35 36
37 38 39
40
1st line
00
01 02 03 04
05 06
07 08 09 0A 0B 0C 0D 0E 0F
10
11
– – –
20 21 22 23 24 25 26 27
2nd line
40
41 42 43 44
45 46
47 48 49 4A 4B 4C 4D 4E 4F
50
51
– – –
60 61 62 63 64 65 66 67
3rd line
80
81 82 83 84
85 86
87 88 89 8A 8B 8C 8D 8E 8F
90
91
– – –
A0 A1 A2 A3 A4 A5 A6 A7
4th line
C0
C1 C2 C3 C4
C5 C6
C7 C8 C9 CA CB CC CD CE CF D0 D1
– – –
E0 E1 E2 E3 E4 E5 E6 E7
or
MSM5839C (1)
MSM5259 (1)
MSM5839C (2)
MSM5259 (2)
MSM5839C (3),(4)
MSM5259 (3),(4)
MSM5839C (5)
MSM5259 (5)
22/52
¡ Semiconductor
MSM6262-xx
6. Cursor/Blink Control Circuit
This is the circuit to control the generation of cursor and its blinking. This circuit is controlled
by the program of the CPU.
The position of the cursor and its blink appears on the position according to the ADC contents,
which correspond to the address of DD RAM. For example, when the ADC is set as "07" (hex.),
the position of cursor and its blinking becomes as follows.
DB7
ADC
0
– – –
0
0
0
DB0
0
1
1
0
2-line display
Digit
1 2
3
00 01
80 81
02
82
4-line display
Digit
1 2
1
7
Cursor and its blinking position
4
5
6
03 04
83 84
05
85
7
8
9
06 —
07
86 87
08
88
79
– – –
– – –
80
4E 4F
CE CF
Cursor and its blinking position
3
4
5
6
7
9
– – –
39 40
06 —
07 08
47 48
– – –
26 27
66 67
00 01
02
03 04
05
40 41
42
43 44
45 46
80 81
82
83 84
85 86
8
87
88
– – –
– – –
A6 A7
– – –
C0 C1 C2 C3 C4 C5 C6 C7 C8
E6 E7
Note: Cursor display and blinking can be performed even when the CG RAM address is
set in the ADC. So, it is necessary to disable the cursor display and blinking when
the CG RAM address is set in the ADC.
7. Underline Control Circuit
First, either underline display mode or underline blinking mode has to be set by the CPU.
When an instruction to enable the underline function is input from the CPU, the cursor
display shifts to the right direction (increment) or left direction (decrement). Display of
underline appears (or disappears) on the same position where cursor was displayed.
An input of "H" data enables the underline display, while an input of "L" data deletes the
underline.
8. Character Generator ROM (CG ROM)
CG ROM stores the character pattern. MSM6262-xx has 128 kinds of 5 x 7-dot patterns, 96
kinds of 5 x 11-dot patterns and 32 kinds of 5 x 12-dot patterns. The character pattern
corresponds to the character code which is written into the DD RAM.
The relation between 8-bit character code and character pattern is described in Table 1.
When the 8-bit character code of CG ROM is written into the DD RAM, the character pattern
of the corresponding character code of the CG ROM is displayed on the LCD position
corresponding to the DD RAM address.
When all of the upper 4 bits of CG ROM code are "L", CG ROM can be switched to CG RAM.
23/52
¡ Semiconductor
MSM6262-xx
Table 1 Character code and character pattern of Standard Code (MSM6262-04)
24/52
¡ Semiconductor
MSM6262-xx
9. Character Generator RAM (CG RAM)
The CG RAM is used to display user's original character pattern other than CG ROM.
The CG RAM has capacity (32 bytes = 256 bits) to write 4 kinds of 5 x 8 dots and 2 kinds of 5
x 12 dots.
In displaying the character pattern stored in the CG RAM, CG RAM has to be enabled by an
instruction. When CG RAM is enabled, CG ROM code for 16 characters cannot be read out
since the CGROM code with all "L" on the upper 4 bits is used as CG RAM code.
The following describes how to write character patterns into the CG RAM and how to display
them on the LCD.
(1) When the character pattern is 5 x 8 dots (See Table 2-1)
• A method to write character pattern into the CG RAM by the CPU
The lower 3 bits (0 - 2) of the CG RAM address correspond to the line position of the
character pattern. The upper 2 bits (3, 4) of the CG RAM address correspond to the lower
2 bits (0, 1) of the character code.
First, set increment of decrement by the CPU, and then input CG RAM address. After this,
write character pattern data into CG RAM through DB0 to DB7 line by line.
DB0 - DB7 correspond to CG RAM data 0 - 7 in Table 2-1.
Display is turned on when "H" is set as input data and turned off when "L" is set as input
data.
Since the ADC is automatically incremented or decremented by 1 after the writing of data
to the CG RAM, it is not necessary to set the CG RAM address again.
To enable cursor display, set all input data on the line where the lower 3 bits of the CG RAM
(0-2) are all "H" to "L".
0 - 4 bits of CG RAM data are output to the LCD as the display data; however, 5 - 7 bits of
CG RAM data are not. But it can be used as the data RAM because the data can be written/
read through DB0 to DB7.
• A method to display the CG RAM character pattern to the LCD
First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is
selected only when all of the upper 4 bits of the character code is "L".
So, the character pattern of CG RAM is displayed on the LCD position that corresponds to
the DD RAM address, when the character code shown in Table 2-1 is written into DD RAM.
Since the bits 2 and 3 of the character code are regarded as invalid, "K" is displayed when
the character codes "01", "05", "'09", and "0D" are selected.
(2) When the character pattern is 5 x 12 dots (See Table 2-2)
• A method to write character pattern into the CG RAM by the CPU
The lower 4 bits of CG RAM address (0 - 3) correspond to the line position of the character
pattern.
The upper 1 bit of CG RAM address bit 4 corresponds to the bit 1 of the character code.
First, set increment or decrement by the CPU, and then input CG RAM address.
After this, write the character pattern data into CG RAM through DB0 to DB7 line by line.
DB0 - DB7 correspond to CG RAM data 0 - 7 in Table 2-2.
Display is turned on when "H" is set as the input data and turned off when "L" is set
25/52
¡ Semiconductor
MSM6262-xx
as the input data.
Since the ADC is automatically incremented or decremented by 1 after the writing of data
to the CG RAM, it is not necessary to set the CG RAM address again.
To enable cursor display, set all input data on the line where the CG RAM address is "0B"
or "1B" (hex.) to "L".
The addresses "0" to "B" (hexadecimal) in the bits 0 to 4 of the CG RAM data are output on
the LCD as the display data. However, the addresses "C" to "F" (hexadecimal) in the bits
0 to 4, and 5 to 7 of the CG RAM data are not output on the LCD. But these CG RAM data
can be used as the data RAM so that they can be written into or read out through DB0 to
DB7.
• A method to display the CG RAM character pattern on the LCD
First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is
selected only when all of the upper 4 bits of the character code is "L".
So, the character pattern of CG RAM is displayed on the LCD position corresponding to
the DD RAM address, when the character code shown in Table 2-2 is written into the DD
RAM.
Since bits 0, 2 and 3 of the character code are regarded as invalid, the character of "m" is
displayed when the character codes "00", "01", "04", "05", "08", "09", "0C" and "0D" are
selected.
(3) A method to read out the CG RAM data
First, set the CG RAM address by inputting a CG RAM address set instruction from the
CPU.
Then, execute the CG RAM/DD RAM data read instruction. The set data of CG RAM
address is output from the DB0 to DB7. The 8-bit data, read out from the MSM6262-xx,
corresponds to the data which is written into the CG RAM. Since the CG RAM address is
automatically incremented or decremented by 1, the CG RAM read out instruction c a n
be successfully input. It is necessary, however, to set the DD RAM at data transferring
condition by executing the DD RAM address set instruction after all of CG RAM data are
read out.
26/52
¡ Semiconductor
MSM6262-xx
Table 2-1 Relation between CG RAM data (character pattern) vs. CGRAM
address and DDRAM data vs. character pattern when the character
pattern is 5 ¥ 8 dots.
CG RAM
ADDRESS
CG RAM DATA
(Character Pattern )
DD RAM DATA
(Character Code )
4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LSB MSB
LSB MSB
LSB
L L L L L X X X L H H H L
H L L L H
L L H
H L L L H
L H L
L H H
H L L L H
L L L L X X L L
H L L L H
H L L
H L L L H
H L H
L H H H L
H H L
L L L L L
H H H
L H L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
X X X H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
L
H H L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
X X X L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L L L L X X L H
L L L L X X H H
X: Don't care
27/52
¡ Semiconductor
MSM6262-xx
Table 2-2 Relation between CGRAM data (character pattern) vs. CGRAM address
and DDRAM data vs. character pattern when the character pattern
is 5 ¥ 12 dots.
CG RAM
CG RAM DATA
DD RAM DATA
(Character Code)
ADDRESS
(Character Pattern)
4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
LSB MSB
LSB MSB
LSB
L
L
L
L
L
X X X L L L L L
L L L L L
L L L H
L L L L L
L L H L
L L H H
L H L L L
L H H H H
L H L L
H L L H L
L H L H
L L L L X X L X
L H H L
L H H H H
L H H H
L H L H L
H L L L
H H H H H
H L L H
L L L H L
H L H L
L L L L L
H L H H
L L L L L
X X X X X
H H L L
H H L H
H H H L
H H H H
H L L L L X X X L L L L L
L L L L L
L L L H
L L L L L
L L H L
L L H H
L L L L L
L L L L L
L H L L
H L L L H
L H L H
L L L L X X H X
H L L L H
L H H L
L H L H L
L H H H
H L L L
L L H L L
H L L H
L H L L L
H L H L
H L L L L
H L H H
L L L L L
H H L L
X X X X X
H H L H
H H H L
H H H H
B
B
X: Don't care
28/52
¡ Semiconductor
MSM6262-xx
9. LCD Display Circuit (COM1 to COM48, DO, CP, LOAD, DF)
The MSM6262-xx is provided with COMMON signal output. So, maximum 160 characters
can be displayed when it is used together with SEGMENT drivers (MSM5259 or MSM5839C).
Interface between MSM6262-xx and SEGMENT drivers can be done by using DO, CP, LOAD
and DF.
The SEGMENT data is serially output from DO pin, synchronized with the pulse which is
output from the CP pin.
This data, input to the SEGMENT driver, is converted from serial data to parallel data by the
latch pulse which is output from the LOAD pin of MSM6262-xx and this converted data is
used as the display data. This parallel/serial conversion is performed synchronized with the
COMMON signal of MSM6262-xx and LCD display AC signal which is output from DF pin.
So, this signal can drive dot matrix LCD panel.
10. Reset Circuit
Power-on-reset is required for MSM6262-xx when it is powered-on. So, a capacitor has to be
connected between RESET pin and VSS pin.
It is also advisable to connect a diode between RESET pin and VDD pin when it is required to
connect a capacitor of more than 3.3 µF to RESET pin.
When the power-on reset circuit normally operates, the busy flags 1 and 2 become at "H" level
for about 10 ms after the power-on. During this period, a initialization of MSM6262-xx is
performed by following procedures.
1 Display is cleared
2 CG ROM becomes enabled
3 No display shift
4 ADC is incremented
5 2-line display mode
6 5 x 8 dots font configuration
7 No display shift for "g", "j", "p", "q" and "y"
8 Display off
9 No display of cursor, blinking and underline
11. Data Bus with CPU
MSM6262-xx can be interfaced with 8-bit CPU, such as 6809, Z80, 80C49 and 80C51. When
MSM6262-xx is connected with 6809, the 68 series/80 series pin has to be connected to VDD.
When MSM6262-xx is connected with Z80, 80C49 or 80C51, the 68 series/80 series pin has to
be connected to VSS. The level at 68 series/80 series cannot be switched during MSM6262-xx's
operation. It must be connected with either VDD or VSS before MSM6262-xx is turned on.
Note: It is possible, indeed, to change the 68 series/ 80 series pin's level when a reset signal
is being input to RESET pin. However, the 68 series /80 series pin does not have
characteristics to have an interface with MCU, nor does it have an antichattering
circuit.
Further, if a reset signal is input, the MSM6262-xx is initialized as described above.
So, in this case, changing the 68 series/80 series pin level is not recommended.
29/52
¡ Semiconductor
MSM6262-xx
,,
,
,,,
,
,,
,,
80 series CPU data transfer
E (RD)
R/W (WR)
A1
A0
NO BUSY1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BUSY1
(Internal
operation)
BUSY2
(Internal
operation)
IR7
BUSY1
DR7
NO BUSY2
IR6
BUSY2
IR5
*
CG/DD
DR5
IR4
*
I/D
DR4
IR3
*
S
DR3
IR2
*
A/O
DR2
IR1
*
D
DR1
IR0
*
UD
DR0
Write an instruction (IR)
DR6
Read the busy flag
Write the data register (RD)
* : Don't care
30/52
¡ Semiconductor
MSM6262-xx
68 series CPU data transfer
,
,,
,
,
,
,
,,
,
,,
,
E (RD)
R/W (WR)
A1
A0
NO BUSY1
DB7
IR7
BUSY1
DR7
NO BUSY2
DB6
IR6
BUSY2
DB5
IR5
*
CG/DD
DR5
DB4
IR4
*
I/D
DR4
DB3
IR3
*
S
DR3
DB2
IR2
*
A/O
DR2
DB1
IR1
*
D
DR1
DB0
IR0
*
UD
DR0
DR6
BUSY1
(Internal
operation)
BUSY2
(Internal
operation)
Write an instruction (IR)
Read the busy flag
Write the data register (RD)
* : Don't care
31/52
¡ Semiconductor
MSM6262-xx
Instruction Table
* : DON'T CARE
80series
CPU Note
68se
1
ries
CPU R/W
L
Display Clear
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
A1
L
A0
L
DB7
L
DB6
L
DB5
L
DB4
L
DB3
L
DB2
L
DB1
L
DB0
H
Return
L
L
L
L
L
L
L
L
L
H
CR/C
Under Line
L
L
L
L
L
L
L
L
H
UL
*
Entry Mode Set
Display/Cursor Shift
CG RAM address Set
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
S/C
I/D
UD/
RL
S
D2
UR/
DL
( )
A/O
D1
( )
*
H
ACG
L
Function Set
Display Control
L
L
L
L
L
L
H
H
D
N
C
*
F1
F2
F3
*
B
UC
UB
*
*
CG RAM/DD RAM
Data Write
DD RAM Address
Set
L
L
H
L
H
L
Read the Underlined
Data
H
L
L
Read the CG RAM/
DD RAM Data
Read the Address
Counter Content
Read Busy Flag
H
L
H
READ DATA
H
H
L
ADC
H
H
H
CR/C = H :
:
UL = H
:
I/D = H
:
S=H
A/O = L :
S/C = H :
UD/RL = H :
:
D2,D1
UR/DL = H :
:
N =L
:
N =H
:
F1 = H
:
F2 = L
:
F3 = H
ULD = H
B1F = H
B2F = H
:
:
:
CG/DD = H :
WRITE DATA
ADD
ULD
B1F
READ DATA
B2F
CG/
DD
I/D
S
A/O
D
Carriage Return
CR/C = L : Cursor home
Write underline
: Underline erase
UL = L
Increment
: Decrement
I/D = L
Accompany display shift
CG ROM ENABLE
A/O = H : CG RAM ENABLE
Display move
S/C = L : Cursor move
Up/Down move
UD/RL = L : Left/Right move
The bit to set the line to be displayed in the uppermost position.
:
D1 is LSB. D2 is MSB.
Upper-right move
UR/DL = L : Down-left move
2 lines
4 lines
: 5 x 7 dots
5 x 11 dots
F1 = L
: 5 x 11 dots or 5 x 7 dots
F2 = H
5 x 12 dots or 5 x 8 dots
: Disable character shift
F3 = L
Shift "g, j, p, q, y" to the
lower position by 1 dot.
ULD = L : No underline data
Underline data exists
B1F = L : Ready to receive instruction
Internal operation going on
B2F = L : No revision on display
Revising the display starting
starting line
line or internal operation going on
CG/DD = L : Transmit/Receive of DD RAM data
Transmit /Receive CG RAM data
UD
Explanation
Clears all of the display. and sets
address 0 of DD RAM in the address
counter.
CR/C = L: Cursor home
CR/C = H: Carriage Return
UL = H: Writes the underline in the
cursor part before executing
this instruction.
UL = L : Erases the underline in the
cursor part before executing
this instruction.
Sets whether the display of the direction of
cursor (I/D) move should be shifted or not.
When the data is being written or read,
this operation is performed.
This instruction also sets whether the
character code of DD RAM is used as
CG ROM or CG RAM.(A/O)
Shifts the cursor and display without
changing the DD RAM contents.
(S/C, UD/RL,UR/DL)
The line to be displayed in the uppermost
position can be set.
Sets the CG RAM address.
The dara, which will be sent/received
after the CG RAM address is set, is
CG RAM data.
Sets the following:
No. of display digits (N), Character font
(F1), Cursor line font (F2), Font shift
of "g, j, p, q, y" (F3)
Sets the following:
All display on/off (D), Cursor display
on/off (C), Character on the cursor
position blink on/off (B), Underline display
on/off (UC), Character, on the
underline, blink on/off (UB)
Writes a data in either DD RAM or
CG RAM.
Sets DD RAM address.
The data which is sent/received after
that is DD RAM data.
Reads following data:
Data on the underline, DD RAM or
CG from RAM data.
Reads the data either from DD RAM
or from CG RAM.
Reads the address counter contents.
Busy 1 flag (B1F) shows that
MSM6262-xx's internal operation is going on.
Busy 2 flag (B2F) shows that the revising
of display starting line is going on.
CG/DD shows whether the data, being
transmitted or received, is of CG RAM
or DD RAM.
I/D shows the direction in which cursor moves.
S shows the display shift.
A/O shows that the DD RAM character
code is CG RAM character code or
CG RAM character code.
D shows the all display on/off.
UD shows underline display on/off.
DD RAM : Display data RAM
CG RAM : Character generator
RAM
ACG
: CG RAM address
ADD
: DD RAM address
ADC
: Address counter which
is used for both DD
RAM and CG RAM
Execution Time (MAX),
When fosc = 500kHz
3.22 ms
1.62 ms
20 ms
20 ms
20 ms
20 ms
20 ms
20 ms
20 ms
20 ms
20 ms
20 ms
0 ms
0 ms
When
fosc =
600 kHz,
execution time
becomes
500
20 ms¥––––
600
·=· 16.7 ms
Note 1: In the case of 80 series CPU, access to MSM6262-xx is done by WR and RD. So, a bit for part of the read/write code is not required.
32/52
¡ Semiconductor
MSM6262-xx
12. Instruction Code
The instruction code is defined as the signal through which the MSM6262-xx is accessed by
the CPU. MSM6262-xx starts its operation upon receipt of the instruction code.
The internal processing operation starts with a timing that does not affect the LCD display,
so, the busy condition is longer than that of cycle time.
In the busy condition, MSM6262-xx does not execute any instruction other than the reading
of busy flag. Therefore, make certain that busy flag is set at "L" before inputting the instruction code.
(1) Display clear
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
L
L
L
L
L
L
L
L
H
When this instruction is executed, the LCD display is cleared.
When cursor display and/or character blink is being performed, their display position
moves to the left end of the LCD. (In the case of 2-line or 4-line display mode, it moves to
the left end of the first line.)
All of the DD RAM data becomes "20" (hex), while ADC data becomes "00" (hex.). If the
display is on a shifted position, it returns to the original position.
Data for underline is re-written as "L" and display turns off.
(2) Return
• CR/C = L (Cursor home)
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
L
L
L
L
L
L
L
H
CR/C
When this instruction is executed, cursor and blinking position moves to the left end of the
LCD. (In the case of 2-line or 4-line display mode, it moves to the left end of the first line.)
When display is being shifted, the display returns to its original position for both
horizontally and vertically.
ADC becomes "00" (hex.).
• CR/C = H (Carriage return)
When this instruction is executed, cursor and blinking position moves to the left end of the
line on which the cursor and brink were positioned before execution of instruction.
If the display is being shifted when this instruction was executed, the cursor and blinking
position moves to the original position before it was shifted only concerning to the shift to
the right and left.
All bits other than line specifying bit of ADC will be reset to "0" (hex.).
33/52
¡ Semiconductor
MSM6262-xx
(3) Underline
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
L
L
L
L
L
L
H
UL
*
*: Don't care
• UL = H (Write underline)
When this instruction is executed, the underline appears on the cursor position. Cursor
will move to the right or left if either increment or decrement is specified.
• UL = L (Erase underline)
When this instruction is executed, the underline on the cursor position disappears. Cursor
will move to the right or left if either increment or decrement is specified.
When this instruction is executed, ADC will be automatically incremented by +1 or
decremented by –1. Display is shifted accordingly.
(4) Entry mode set
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
L
L
L
L
L
H
I/D
S
A/O
• I/D (Increment/Decrement)
When this instruction is executed, DD RAM address will be incremented (I/D = "H") or
decremented (I/D = "L") by 1, after the character code or underline code is written into (or
read out from) the DD RAM.
In the case of increment, cursor moves to the right, while the cursor moves to the left in the
case of decrement.
Processing for writing/reading the data into/from CG RAM is performed the same way.
• S (Display shift upon writing)
When S = "H" and data is written into DD RAM, display is shifted either to the right or
left. When I/D = "H", the whole display shifts to the left, while it shifts to the right when
I/D = "L". So, display of cursor looks being stopped and display itself looks being shifted.
In the case of reading the data from DD RAM, display is not shifted. Also in the case of
reading/writing the data from/to CG RAM, display shall not be shifted.
When S = "L", display is not be shifted.
• A/O (CG RAM ENABLE/CG ROM ENABLE)
When A/O is "L", CG ROM will be enabled, and all CG ROM contets on Table 2 becomes
selectable and CG RAM cannot be selected.
CG RAM cannot be used as character code for display. But it can be used as data RAM.
When A/O = "H", CG RAM is enabled.
When the upper 4 bits of the character code in Table 1 are "00" (hex.), the bit pattern of CG
RAM is displayed on the LCD. (CG RAM has a RAM area for 4 kinds of 5 x 8 dots and 2
kinds of 5 x 12 dots)
CG ROM is selected when the upper 4 bits of the character code in Table 1 are "01" - "0F"
(hex.).
34/52
¡ Semiconductor
MSM6262-xx
(5) Display/Cursor move
A1
Instruction
code
L
A0
L
DB7
L
DB6
L
DB5
DB4
L
H
DB3
S/C
DB2
UD/
RL
DB1
D2
(UR/
DL)
DB0
D1
(*)
*: Don't care
• S/C (Display move/Cursor move)
This is the bit to select either display or cursor to move. S/C = "H" enables the display
movement, while S/C = "L" enables the cursor movement.
• UD/RL (Upward or downward move/Right or left move)
UD/RL = "H" enables upward or downward move. UD/RL = "L" enables right or left
move.
• D2, D1 (Starting line of display)
Upward or downward movement is enabled by setting the starting line of display. D1 is
LSB and D2 is MSB. Both D1 and D2 are expressed in 2-bit binary data.
Only D1 is valid in 2-line mode. Both D1 and D2 are valid in 4-line mode.
[ 2-line mode ]
DD RAM
D2 = *, D1 = "L"
Display of the LCD
1st line
1st line
2nd line
2nd line
D2 = *, D1 = "H"
1st line
1st line
2nd line
2nd line
* : Don't care
35/52
¡ Semiconductor
MSM6262-xx
[ 4-line mode ]
DD RAM
D2 = "L", D1 = "L" Display of the LCD
1st line
1st line
2nd line
2nd line
3rd line
3rd line
4th line
4th line
D2 = "L", D1 = "H"
1st line
1st line
2nd line
2nd line
3rd line
3rd line
4th line
4th line
D2 = "H", D1 = "L"
1st line
1st line
2nd line
2nd line
3rd line
3rd line
4th line
4th line
D2 = "H", D1 = "H"
1st line
1st line
2nd line
2nd line
3rd line
3rd line
4th line
4th line
36/52
¡ Semiconductor
MSM6262-xx
• UR/DL (Up-right move/Down-left move)
UR/DL = "H" enables up-right movement.
UR/DL = "L" enables down-left movement.
Combination of bit for Display/Cursor movement is as follwes
S/C
UD/
RL
D2
(UR/
DR)
D1
*
L
L
L
*
Move the cursor to the left by 1 digit
L
L
H
*
L
H
L
*
Move the cursor to the right by 1 digit
Move the cursor downward by 1 digit
L
H
H
*
Move the cursor upward by 1 digit
H
L
L
*
Move the display to the left by 1 digit
H
L
H
*
Move the display to the right by 1 digit
H
H
L
L
Set the first line as the display starting line
H
H
L
H
Set the 2nd line as the display starting line
H
H
H
L
Set the 3rd line as the display starting line s
H
H
H
H
Set the 4th line as the display starting line s
Explanation
* : Don't care
s : Invalid in 2-line mode
(6) CG RAM address set
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
L
L
L
L
H
Ac4
DB3
Ac3
DB2
Ac2
DB1 DB0
Ac1 Ac0
Set the CG RAM address which consists of 5 bits of Ac4 - Ac0. The data which will be
transferred after this instruction is set will be limited to the CG RAM data (character font
data).
37/52
¡ Semiconductor
MSM6262-xx
(7) Function set
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
L
L
L
H
N
*
F1
F2
DB1 DB0
*
F3
*: Don't care
• N (Selection of LCD lines to be displayed)
N
LCD lines
L
2-line mode
H
4-line mode
• F1 (5 x 11 dots/5 x 7 dots)
When F1 = "H", 5 x 12-dot font is selected.
When F1 = "L", 5 x 8-dot font is selected.
• F2 (Font assignment of cursor line)
When F2 = "L" and if character code, which has a display dot on the cursor position, is
selected, it is displayed on the cursor line of LCD.
When F2 = "H" and if character code, which has a display dot on the cursor position, is
selected, cursor is displayed but the bit on the cursor position is not displayed.
However, this function does not apply to CG RAM and the bit on the cursor position is also
displayed.
• F3 (Character shift of "g, j, p, q, y")
When F3 = "H", each character of "g, j, p, q, y" is displayed shifted downward by 1 dot for
the whole character.
When F3 = "L", display of these characters is the same as other characters, as shown in Table
1. This bit is valid only for 5 x 12-dot font.
Example
q
F1 = "L" (5 x 8-dot/font)
5 x 11- or 5 x 12-dot font ROM
5 x 7-dot font ROM
3 dots
7 dots
Cursor position
Cursor
Not displayed
1 or 2 dots
38/52
¡ Semiconductor
MSM6262-xx
w
F1 = "H" (5 x 12-dot/font)
5 x 12-dot
font ROM
5 x 11-dot
font ROM
5 x 7-dot font ROM
3 dots
7 dots
(1 dot)
Cursor position
e
F2 = "H"
1 dot
r
F2 = "L"
Cursor position
t
F3 = "L"
y
Cursor position
F3 = "H" (5 x 12-dot font only)
Shifted downward by 1 dot
39/52
¡ Semiconductor
MSM6262-xx
(8) Display control
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
L
L
H
D
C
B
UC
UB
*
DB0
*
*: Don't care
• D (All display on/off)
When D = "H", display on the LCD is enabled.
When D = "L", display is disabled.
When display was disabled by setting D at "L", character code in the DD RAM does not
change. So, when D becomes "H" again, display is enabled immediately.
• C (Cursor display on/off)
C = "H", cursor display appears.
When C = "L", cursor display disappears.
• B (Cursor blinking)
When B = "H", blinking of character on the position corresponding to the cursor position,
starts. Blinking of all-dot's-on and character (and cursor)-on is performed alternately for
every 409.6 ms in case of fosc = 500 kHz and 5 x 8 dots font configuration (every 614.4 ms
in case of 5 x 12 dots font configuration)
When B = "L", blinking stops.
Cursor and blinking can be set together.
• UC (Underline display)
When UC = "H", underline is displayed on the cursor position.
When UC = "L", underline display is disabled.
• UB (Underlined character blinking)
When UB = "H", blinking of character on the position corresponding to the underline
position, starts. Blinking of character stops when UB = "L".
Cursor, blink, underline, and blinking of character on the underline can be set together.
(9) CG RAM and DD RAM data write
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
H
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Write the 8-bit data (DI7 - DI0) into either CG RAM or DD RAM. Determination of either
CG RAM or DD RAM is made by the previously set CC RAM or DD RAM address set.
After the data is written into the RAM, it is incremented or decremented by 1 according
to the entry mode of the address. Display shift is also determined by the entry mode.
40/52
¡ Semiconductor
MSM6262-xx
(10) DD RAM address set
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
H
L
AI7
AI6
AI5
AI4
AI3
AI2
AI1
AI0
This instruction code sets the DD RAM address, which consists of 8 bits (AI7 to AI0). The
data which is received after this instruction is set is limited to the DD RAM data (character
code data).
Do not input any address code other than those below.
2-line mode : 1st line
00 - 4F
2nd line
80 - CF
4-line mode : 1st line
00 - 27
2nd line
40 - 67
3rd line
80 - A7
4th line
C0 - E7
(11) Underline data read
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
L
ULD
D06
D05
D04
D03
D02
D01
D00
This instruction reads underline data, and CG RAM or DD RAM data.
Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD
RAM address set.
The first data read by this instruction is an invalied data. Normal data is read out from
the second instruction onward if the read instruction is executed continuously. This
instruction address will be incremented or decremented by 1 according to the entry
mode. Display shift is, however, not performed. Underline data is output to DB7 as either
"H" (when display is on) or "L" (when display is off).
The MSB of RAM data is not read. RAM data consists of 7 bits (DB0 to DB6).
41/52
¡ Semiconductor
MSM6262-xx
(12) CG RAM and DD RAM data read
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L
H
D07
D06
D05
D04
D03
D02
D01
D00
This instruction reads the 8-bit data (DO7 to DO0) from either CG RAM or DD RAM.
Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD
RAM address set.
The CG RAM address set instruction or DD RAM address set instruction has to be input
just before executing this read instruction. If it is not input, the first output of the data
becomes invalid. When this read instruction is performed continuously, normal data is
output from the 2nd data onward.
In the case of DD RAM data read, normal data is output from the first data even if the
address set is not input, provided that cursor is moved by the cursor shift instruction.
After reading the data, the address is incremented or decremented by 1 by the entry
mode.
The shift of the display, however, is not performed.
(13) Address counter read
Instruction
code
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
H
L
A07
A06
A05
A04
A03
A02
A01
A00
This instruction reads the 8-bit data (AO7 to AO0) . Address counter is determined by the
previously set address set because it is used for both CG RAM and DD RAM.
(14) Busy flag read
Instruction
code
•
•
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
H
H
B1F
B2F
CG/
DD
I/D
S
A/O
D
UD
B1F (Busy 1 flag)
When B1F = "H", MSM6262-xx is engaged in internal operation and next instruction is not
accepted until when B1F becomes "L". So, subsequent instruction has to be input after B1F
is confirmed at "L". During B1F = "H", DB5 to DB0 are undefined.
B2F (Busy 2 flag)
B2F indicates that MSM6262-xx is engaged in its internal operation and it also indicates
that the display starting line is under being revised.
Instruction contents of B1F and B2F are the same except when setting the starting line of
display.
B2F = "H" indicates that MSM6262-xx is engaged in its internal operation. B2F = "L"
indicates that MAM6262-xx is ready for accepting new instruction.
Even when B2F = "H", new instruction can be accepted if B1F = "L". However, if the
starting line of display is revised under this condition, the previous set data about
starting line of display becomes invalid and the newly input data about starting line
becomes valid.
42/52
¡ Semiconductor
MSM6262-xx
• CG/DD (CG RAM/DD RAM)
This bit indicates whether the address counter contents are CG RAM or DD RAM when
B1F = "L". It indicates that CG RAM data has been selected when CG/DD = "H" and that
DD RAM data has been selected when CG/DD = "L".
• I/D (Increment/Decrement)
This bit indicates which has been set in the entry mode set, increment or decrement, when
B1F = "L". It indicates that increment has been set when I/D = "H" and that decrement has
been set when I/D = "L".
• S (Shift)
This bit reads the shift condition in the entry mode when B1F = "L". It indicates that shift
is set when S = "H" and shift is disabled when S = "L".
• A/O (CG RAM ENABLE/CG ROM ENABLE)
This bit indicates which has been selected in the entry mode, CG ROM or CG RAM, when
BIF = "L".
It indicates the CG ROM selected state when A/O = "L" and CG RAM selected state when
A/O = "H".
• D (Display)
This bit indicates which has been set by display control instruction, LCD display ON or
OFF, when B1F = "L". It indicates that the display is on when D = "H" and the display is
off when D = "L".
• UD (Underline)
This is the bit to indicate the condition of underline or blinking on the underline, both of
which were set by display control instruction, when B1F = "L".
When UD = "H", either (or both of) underline display or blinking on the underline is being
executed. When UD = "L", it indicates neither of underline display nor blinking on the
underline is performed.
43/52
¡ Semiconductor
MSM6262-xx
APPLICATION CIRCUITS
1
2-line display mode
5 x 7 dots, 2 lines ¥ 16 characters
(Note: COM17 - COM48 should be left open)
COM1
COM16
COM17
COM48
MSM6262-xx
DO
DF
CP
LOAD
LCD
O1
DI1
O40
DO40
MSM5259
CP
LOAD DF
DO20 DI21
O1
DI1
O40
MSM5259
CP
LOAD DF
DO20 DI21
44/52
¡ Semiconductor
2
MSM6262-xx
2-line display mode
5 x 11 dots, 2 lines ¥ 16 characters
(Note: COM25 - COM48 should be left open)
COM1
underline
COM24
COM25
LCD
COM48
MSM6262-xx
DO
DF
CP
LOAD
cursor
O1
DI1
O40
DO40
MSM5259
CP
LOAD DF
DO20 DI21
O1
DI1
O40
MSM5259
CP
LOAD DF
DO20 DI21
45/52
¡ Semiconductor
3
MSM6262-xx
4-line display mode
5 x 7 dots, 4 lines ¥ 16 characters
(Note: COM33 - COM48 should be left open)
LCD
COM1
COM32
COM33
COM48
MSM6262-xx
DO
DF
CP
LOAD
O1
DI1
O40
DO40
MSM5839C
CP
LOAD DF
DO20 DI21
O1
DI1
O40
MSM5839C
CP
LOAD DF
DO20 DI21
46/52
¡ Semiconductor
4
MSM6262-xx
4-line display mode
5 x 11 dots, 4 lines ¥ 16 characters
LCD
COM1
COM48
MSM6262-xx
DO
DF
CP
LOAD
O1
DI1
O40
DO40
MSM5839C
CP
LOAD DF
DO20 DI21
O1
DI1
O40
MSM5839C
CP
LOAD DF
DO20 DI21
47/52
V5
V4
VSS
V1
VDD
DF
CP
LOAD
DO
COM48
COM1
0V
C
5V
R
C
O1 ~ O40
R
C
DO40
MSM5839C
CP
DO20
LOAD
DI21
DF
VDD VSS V2 V3VEE
DI1
C
4R
C
R
C
R
C
VR
O1 ~ O40
r
–5 V
DO40
MSM5839C
CP
DO20
LOAD
DI21
DF
VDD VSS V2 V3VEE V2V3 VEE
DI1
LCD
O1 ~ O40
DO40
MSM5839C
CP
DO20
LOAD
DI21
DF
VDD VSS
V2 V3VEE
DI1
•
MSM6262-xx
¡ Semiconductor
MSM6262-xx
Example of connection with MSM5839C and bias circuit
48/52
¡ Semiconductor
•
MSM6262-xx
Example of bias circuit
1/5 - 1/8 bias example 1.
Bias
1/5
1/6
1/7
1/8
RR
R
2R
3R
4R
VLCD: LCD driving voltage
VDD
R
VLCD
V1
R
V2
MSM6262-xx
RR
V3
to segment
driver
R
V4
R
V5
VEE
r
VR
1/5 - 1/8 bias example 2.
Bias
1/5
1/6
1/7
1/8
RR
R
2R
3R
4R
VLCD: LCD driving voltage
VDD
C R
V1
VLCD
R
MSM6262-xx
C
V2
RR
C
V3
C
V4
V5
C
R
R
to segment
driver
C
VEE
r
VR
C
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¡ Semiconductor
•
MSM6262-xx
LCD duty and bias
No. of lines
2 lines
4 lines
Duty
1/16
1/24
1/32
1/48
Bias
1/5
1/6
1/7
1/8
Above are examples of relation between LCD duty and bias. Use these values for reference,
for they vary depending on the characteristics of LCD panel.
The value of resistor on bias circuit is determined by the operational margin and power
consumption. To make the power consumption lower, the value of resistor has to be larger,
but it makes the LCD driving output impedance high and causes the distortion on the LCD
driving waveform.
If a large LCD panel is used, the value of the resistor should be much lower because the
LCD capacitance increases.
Connecting a bypass capacitor to the bias resistor in parallel can improve the distortion of
LCD driving waveform. However, connecting a capacitor of too large value may cause a
level shift of the bias voltage.
So, it has to be determined carefully after checking experimentally.
Followings are the reference values.
R = 2 to 10 kW
VR = 10 to 50 kW
r = 0.2 to 2 kW
C = 0.0022 to 0.047 mF
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¡ Semiconductor
•
MSM6262-xx
LCD driving waveform (at 1/5 to 1/8 bias)
1 2
COM1
VDD
V1
V2
V3
V4
V5
COM2
VDD
V1
V2
V3
V4
V5
SEG
VDD
V1
V2
V3
V4
V5
1 2
1 2
Lighting waveform
DF
1 frame
Duty
1/16
Frame frequency
78.125 Hz
1/24
52.08 Hz
1/32
1/48
78.125 Hz
52.08 Hz
Note: fosc = 500 kHz
Selecting a SEGMENT driver IC
When VLCD is within the voltage range of VDD and that of VSS, MSM5259 is recommendable as
SEGMENT driver. When VLCD is beyond the voltage range of VDD and that of VSS, MSM5839C
or MSM5260 is recommendable as SEGMENT driver.
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¡ Semiconductor
MSM6262-xx
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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