LH168P 309-output TFT-LCD Source Driver IC LH168P DESCRIPTION PIN CONNECTIONS The LH168P is a 309-output TFT-LCD source driver IC which can simultaneously display 262 144 colors in 64 gray scales. TOP VIEW 350-PIN TCP XO1 1 YO1 2 ZO1 3 FEATURES CHIP SURFACE • Selectable number of LCD drive outputs : 309/300 • Built-in 6-bit digital input DAC • Possible to display 262 144 colors in 64 gray scales with reference voltage input of 11 gray scales : This reference voltage input corresponds to ‹ correction and intermediate reference voltage input can be abbreviated • Cascade connection • Sampling sequence : Output shift direction can be selected XO1, YO1, ZO1/XO103, YO103, ZO103 or ZO103, YO103, XO103/ZO1, YO1, XO1 • Shift clock frequency : 55 MHz (MAX.) • Supply voltages – VCC (for logic system) : +3.0 to +5.5 V – VLS (for LCD drive system) : +3.0 to +5.5 V • Package : 350-pin TCP (Tape Carrier Package) 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 GND VLS V9 V7 V5 V3 V1 XI5 XI4 XI3 XI2 XI1 XI0 YI5 YI4 YI3 YI2 YI1 YI0 SPOI GND MODE CK VCC SPIO LS ZI5 ZI4 ZI3 ZI2 ZI1 ZI0 LBR V0 V2 V4 V6 V8 V10 VLS GND XO103 307 YO103 308 ZO103 309 NOTE : Doesn't prescribe TCP outline. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LH168P PIN DESCRIPTION PIN NO. 1 to 309 SYMBOL XO1-ZO103 I/O O LCD drive output pins 310, 330, 350 311, 349 GND VLS – Ground pins – Power supply pins for analog circuit 312 to 317 318 V10, V8, V6, V4, V2, V0 LBR I I Reference voltage input pins Shift direction selection input pin 319 to 324 ZI0-ZI5 325 LS I I Data input pins Latch input pin 326 SPIO I/O Start pulse input/cascade output pin 327 VCC Power supply pin for digital circuit Shift clock input pin 309/300-output selection input pin Start pulse input/cascade output pin 328 CK – I 329 331 MODE SPOI I I/O DESCRIPTION 332 to 337 YI0-YI5 I Data input pins 338 to 343 XI0-XI5 344 to 348 V1, V3, V5, V7, V9 I I Data input pins Reference voltage input pins 2 LH168P BLOCK DIAGRAM VCC GND 327 GND GND 310 330 350 MODE 329 LBR 318 SHIFT REGISTER SPOI 331 326 SPIO CK 328 1 2 103 6 XI0 338 XI5 343 YI0 332 YI5 337 DATA LATCH 6 SAMPLING MEMORY ZI0 319 6 ZI5 324 6 6 6 LS 325 HOLD MEMORY V0 317 6 6 6 V1 344 311 VLS LEVEL SHIFTER V2 316 6 6 6 V3 345 V4 315 V5 346 V6 314 REFERENCE VOLTAGE GENERATION CIRCUIT 64 DA CONVERTER V7 347 V8 313 OUTPUT CIRCUIT V9 348 V10 312 1 2 3 XO1 YO1 ZO1 3 307 308 309 XO103 YO103 ZO103 349 VLS LH168P FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK Shift Register FUNCTION Used as a bi-directional shift register which performs the shifting operation by CK and Data Latch selects bits for data sampling. Used to temporary latch the input data which is sent to the sampling memory. Sampling Memory Hold Memory Used to sample the data to be entered by time sharing. Used for latch processing of data in the sampling memory by LS input. Level Shifter Used to shift the data in the hold memory to the power supply level of the analog circuit unit and sends the shifted data to DA converter. Reference Voltage Generation Circuit DA Converter Output Circuit Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit. Used to generate an analog signal according to the display data and sends the signal to the output circuit. Used as a voltage follower, configured with an operational amplifier and an output buffer, which outputs analog signals of 64 gray scales to LCD drive output pin. INPUT/OUTPUT CIRCUITS VCC I To Internal Circuit ¿Applicable pins¡ CK, LS, LBR, XI0-XI5, YI0-YI5, ZI0-ZI5 GND Fig. 1 Input Circuit (1) VCC VCC I To Internal Circuit ¿Applicable pin¡ MODE GND Fig. 2 Input Circuit (2) 4 LH168P Pch Tr I VCC Output Signal O Output Control Signal Nch Tr GND VCC To Internal Circuit ¿Applicable pins¡ SPIO, SPOI GND Fig. 3 Input/Output Circuit VLS Operational Amplifier O + From Internal Circuit ¿Applicable pins¡ XO1-XO103, YO1-YO103, ZO1-ZO103 – GND Fig. 4 Output Circuit 5 LH168P FUNCTIONAL DESCRIPTION Pin Functions SYMBOL VCC FUNCTION Used as power supply pin for digital circuit, connected to +3.0 to +5.5 V. VLS GND Used as power supply pin for analog circuit, connected to +3.0 to +5.5 V. Used as ground pin, connected to 0 V. SPIO Used as input pins of start pulse and also used as output pins for cascade connection. When "H" is input into start pulse input pin, data sampling is started. On completion of SPOI sampling, "H" pulse is output to output pin for cascade connection. Pin functions are LBR LS CK V0-V10 XI0-XI5 YI0-YI5 XI0-ZI5 MODE selected by LBR. For selecting, refer to "Functional Operations". Used as input pin for selecting the shift register direction. For selecting, refer to "Functional Operations". Used as input pin for parallel transfer from sampling memory to hold memory. Data is transferred at the rising edge and output from LCD drive output pin. Used as shift clock input pin. Data is latched into sampling memory from data input pin at the rising edge. Used as reference voltage input pins. Hold the reference voltage fixed during the period of LCD drive output. For relation between input data and output voltage values, refer to "Output Voltage Value". For internal gamma correction, refer to "Gamma Correction Value". Used as data input pins of R, G, and B colors. 6-bit data are input from data pins at the rising edge of CK. For relation between input data and output voltage values, refer to "Output Voltage Value". Select the data to be entered into X, Y, and Z according to picture element arrays of the panel. Used as input pin for selecting the number of LCD drive outputs (309 outputs or 300 outputs). When "L" is entered, it is 309-output mode. When "H" is entered, it is 300-output mode. This pin is pulled up at the inside. Used as LCD drive output pins which output the voltage corresponding to the data input XO1-XO103 YO1-YO103 ZO1-ZO103 pins (XI0 to XI5, YI0 to YI5, ZI0 to ZI5). When 300-output mode, 9 output pins (XO51 to XO53, YO51 to YO53, ZO51 to ZO53) are invalid. Invalid output pins must be opened. Data of XO1 to XO103 correspond to XI0 to XI5. Data of YO1 to YO103 correspond to YI0 to YI5, and data of ZO1 to ZO103 correspond to ZI0 to ZI5. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value". 6 LH168P Functional Operations The following describes the relation between LBR pin, SPOI pin, SPIO pin and output direction. PIN OUTPUT DIRECTION LBR RIGHT SHIFT (XO1, YO1, ZO1/XO103, YO103, ZO103) H LEFT SHIFT (ZO103, YO103, XO103/ZO1, YO1, XO1) L SPOI SPIO Input Output Output Input NOTE : Color data corresponding to X, Y, and Z vary depending on the output direction. 7 LH168P Output Voltage Value value is determined by the lower 3-bit data (D2, D1 and D0). Relation between input data and output voltage values is shown below. Two voltages are selected from all of the reference voltages (V0-V10) by the upper 3-bit data (D5, D4 and D3) of the 6-bit input data (D5, D4, D3, D2, D1 and D0) taken by time sharing, and intermediate INPUT DATA 0 OUTPUT VOLTAGE INPUT V0 DATA 20 OUTPUT VOLTAGE V6 + (V5 – V6) x 7/8 V1 21 V6 + (V5 – V6) x 6/8 V2 + (V1 – V2) x 6/7 V2 + (V1 – V2) x 5/7 22 23 V6 + (V5 – V6) x 5/8 V6 + (V5 – V6) x 4/8 4 V2 + (V1 – V2) x 4/7 V2 + (V1 – V2) x 3/7 24 25 V6 + (V5 – V6) x 3/8 V6 + (V5 – V6) x 2/8 5 V2 + (V1 – V2) x 2/7 26 V6 + (V5 – V6) x 1/8 6 V2 + (V1 – V2) x 1/7 V2 27 28 V6 V7 + (V6 – V7) x 7/8 9 V3 + (V2 – V3) x 7/8 V3 + (V2 – V3) x 6/8 29 2A V7 + (V6 – V7) x 6/8 V7 + (V6 – V7) x 5/8 A V3 + (V2 – V3) x 5/8 2B V7 + (V6 – V7) x 4/8 B V3 + (V2 – V3) x 4/8 V3 + (V2 – V3) x 3/8 2C 2D V7 + (V6 – V7) x 3/8 V7 + (V6 – V7) x 2/8 E V3 + (V2 – V3) x 2/8 V3 + (V2 – V3) x 1/8 2E 2F V7 + (V6 – V7) x 1/8 V7 F V3 30 V8 + (V7 – V8) x 7/8 10 V4 + (V3 – V4) x 7/8 V4 + (V3 – V4) x 6/8 31 32 V8 + (V7 – V8) x 6/8 V8 + (V7 – V8) x 5/8 V4 + (V3 – V4) x 5/8 V4 + (V3 – V4) x 4/8 33 34 V8 + (V7 – V8) x 4/8 V8 + (V7 – V8) x 3/8 15 V4 + (V3 – V4) x 3/8 V4 + (V3 – V4) x 2/8 35 36 V8 + (V7 – V8) x 2/8 V8 + (V7 – V8) x 1/8 16 V4 + (V3 – V4) x 1/8 37 V8 17 18 V4 V5 + (V4 – V5) x 7/8 38 39 V9 + (V8 – V9) x 6/7 V9 + (V8 – V9) x 5/7 19 V5 + (V4 – V5) x 6/8 V5 + (V4 – V5) x 5/8 3A 3B V9 + (V8 – V9) x 4/7 V9 + (V8 – V9) x 3/7 1B V5 + (V4 – V5) x 4/8 3C V9 + (V8 – V9) x 2/7 1C 1D V5 + (V4 – V5) x 3/8 V5 + (V4 – V5) x 2/8 3D 3E V9 + (V8 – V9) x 1/7 V9 1E 1F V5 + (V4 – V5) x 1/8 V5 3F V10 1 2 3 7 8 C D 11 12 13 14 1A 8 LH168P ‹ (gamma) Correction Value reference voltage input pins matches the reference voltages (V1 to V9) for ‹ correction of LCD panel, the external power supply of the intermediate voltages (for V1 to V9 pins) is not required. Between reference voltage input pins, 7 or 8 resistors of the same resistance value are connected in series. When the resistance ratio between respective LH168P External Reference Voltage V0 V1 R0 V2 R1 7 equal parts V3 R2 8 equal parts V4 R3 8 equal parts V5 R4 8 equal parts V6 R5 8 equal parts V7 R6 8 equal parts V8 R7 8 equal parts V9 R8 7 equal parts V10 R9 The following shows the ratio of ‹ correction resistance, when R0 equals 1. R9 R8 1.05 1.42 R7 R6 0.84 0.66 R5 0.84 R4 0.90 1.50 R3 R2 R1 2.77 2.00 R0 1.00 9 LH168P PRECAUTIONS Reference voltage input The relation of the reference voltage input is shown here. Precautions when connecting or disconnecting the power supply This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. GND < V0 ≤ V1 ≤ π ≤ V9 ≤ V10 < VLS or VLS > V0 ≥ V1 ≥ π ≥ V9 ≥ V10 > GND Maximum ratings When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings. VCC / logic input / VLS, V0-V10 When disconnecting the power supply, follow the reverse sequence. Target output load This IC is designed for a 150 pF output load capacity. When using this IC for other than 150 pF panels, confirm the device is having no problem before using it. ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage SYMBOL VCC VLS VI Input voltage Output voltage Storage temperature VI APPLICABLE PINS VCC VLS V0-V10 SPIO, SPOI, CK, LS, MODE, LBR, XI0-XI5, YI0-YI5, ZI0-ZI5 VO VO SPIO, SPOI XO1-ZO80 TSTG RATING –0.3 to +6.0 –0.3 to +6.0 UNIT V V –0.3 to VLS + 0.3 V –0.3 to VCC + 0.3 V –0.3 to VCC + 0.3 –0.3 to VLS + 0.3 V –45 to +125 ˚C NOTES : 1. TA = +25 ˚C 2. The maximum applicable voltage on any pin with respect to GND (0 V). RECOMMENDED OPERATING CONDITIONS PARAMETER Supply voltage Reference voltage input SYMBOL VCC VLS MIN. +3.0 +3.0 V0-V10 0 TYP. MAX. +5.5 +5.5 UNIT V V VLS V Clock frequency fCK 55 MHz LCD drive output load capacity CL 150 pF +75 ˚C Operating temperature TOPR –20 NOTE : 1. The applicable voltage on any pin with respect to GND (0 V). 10 NOTE 1 V NOTE 1, 2 LH168P ELECTRICAL CHARACTERISTICS DC Characteristics (VCC = VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C) PARAMETER SYMBOL CONDITIONS APPLICABLE PINS XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, Input "Low" voltage VIL VIH SPOI, CK, LS, LBR, MODE Input "High" voltage Output "Low" voltage VOL IOL = 0.3 mA SPIO, SPOI Output "High" voltage VOH IOH = –0.3 mA XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, IILL1 SPOI, CK, LS, LBR Input "Low" current IILL2 MODE XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, Input "High" current VILH SPOI, CK, LS, LBR, MODE fCK = 55 MHz Supply current ICC1 fLS = 50 kHz (In operation mode) (Data sampling state) fCK = 55 MHz VCC-GND Supply current fLS = 50 kHz ICC2 (In standby mode) SPI = GND is fixed. (Standby state) fCK = 55 MHz Supply current ILS1 fLS = 50 kHz (In operation mode) (Data sampling state) fCK = 55 MHz VLS-GND fLS = 50 kHz Supply current ILS2 SPI = GND is fixed. (In standby mode) (Standby state) Output voltage range VOUT Deviations between XO1-ZO103 VOD output voltage pins Output current IO1, IO2 Resistance between RGMA V0-V10 reference voltage input pins MIN. TYP. MAX. UNIT GND 0.3VCC V 0.7VCC VCC V GND GND + 0.4 V VCC – 0.4 VCC V 10 µA 400 µA 10 µA 12 mA 4 mA 8 mA 7 mA GND + 0.1 VLS – 0.1 V –20 20 mV 20 50 10 20 µA 30 NOTE 1 2 k$ NOTES : 1. Criterion of evaluating voltage deviations. (a) Between output voltage pins Measuring values : Output voltage value at the time after 10 µs at the rising edge of LS. (Average of several times) (Conditions) Output load capacity is 150 pF. In a state when the reference voltage is fixed. Expecting values : Calculated following these specifications. (Conditions) In a state when the reference voltage is fixed. (b) Between LCD drivers Measuring values : Applicable to (a). (Conditions) Applicable to (a). Expecting values : Applicable to (a). (Conditions) Applicable to (a). Each input voltage between the LCD drivers must be made perfectly equal by connecting corresponding reference voltage input pins. 2. IO1 : Applied voltage = 3.0 V for output pins XO1 to ZO103. Output voltage = 2.5 V for output pins XO1 to ZO103. VCC = VLS = 5.0 V IO2 : Applied voltage = 2.0 V for output pins XO1 to ZO103. Output voltage = 2.5 V for output pins XO1 to ZO103. VCC = VLS = 5.0 V 11 LH168P AC Characteristics PARAMETER Clock frequency "H" level pulse width "L" level pulse width (VCC = VLS = +3.0 to +5.5 V, TOPR = –20 to +75 ˚C) SYMBOL CONDITIONS fCK tCWH tCWL APPLICABLE PINS MIN. CK 4 4 TYP. MAX. 55 UNIT MHz ns ns Input rise time tCR 10 ns Input fall time tCF 10 ns Data setup time tSUD Data hold time tHD XI0-XI5, YI0-YI5, ZI0-ZI5 4 0 ns ns ns Start pulse setup time tSUSP 4 Start pulse hold time tHSP 0 Start pulse width Start pulse output delay time LCD drive output delay time LS signal-SPI signal setup time LS signal-CK signal hold time LS signal "H" level width SPIO, SPOI tWSP tDSP CL = 15 pF tDO CL = 150 pF XO1-ZO103 tLSSP tHLS LS tWLS 12 ns 1 -------fCK ns 12 ns 10 µs 1 -------fCK ns 7 ns 1 -------fCK ns LH168P Timing Chart 1 fCK tCWH CK tCWL 1 tSUSP tHSP tCR 2 tCF SPIO Input (SPOI) tWSP tHD tSUD XI0-XI5 YI0-YI5 ZI0-ZI5 1 2 CK LAST – 1 LAST tDSP SPIO Output (SPOI) tHLS tWLS LS tLSSP tSUSP tHSP SPIO Input (SPOI) tDO XO1-ZO103 Target voltage (6-bit accuracy) 13 PACKAGES FOR LCD DRIVERS PACKAGES [0.75] 0.15MAX. Pattern side ø Tape Material 0.24±0.02 Tape width Tape type Perforation pitch XO1 4.5 (SL) 2.1 (Backside PI coat) 4.3 (Backside PI coat) 2.4 (SL) 4.9 (Backside PI coat) 4.6 (SL) ±0.05 5.2 (SL) (Hole) 8.4±0.15(SR) (On the output leads) 10.4 (SL) [11.4 (E.L.)] [19.45 (E.L.)] 11.7 12.45 (SL) 6.4±0.15(SR) (On the output leads) ±0.05 (Mark) 7.4 [8.05 (E.L.)] 12.7±0.5(Good device hole) UPILEX is a trademark of UBE INDUSTRIES, LTD.. 14 1.6 (Backside PI coat) 1.0 (SL) 1.6 (Backside PI coat) [0.40] 1.0 (SL) [1.65TYP. (1.50MIN.)] 0.24 ±0.02 ] 0.8 (SL) ZO1 YO1 XO1 VCOM3 VCOM3 VCOM3 VCOM2 VCOM2 VCOM2 VCOM2 VCOM2 VCOM1 VCOM1 20 0. [C 0.5 (SL) ZO54 YO54 XO54 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY ZO50 YO50 XO50 1.0±0.05 2.5 (SL) 2.0 (SL) 7.2 [3.0TYP. (2.85MIN.)] VCOM6 VCOM6 VCOM5 VCOM5 VCOM5 VCOM5 VCOM5 VCOM4 VCOM4 VCOM4 ZO103 YO103 XO103 ø Tape Specification P0.065 x (358 – 1) = 23.205 W0.033 P0.46 x (52 – 1) = 23.46 W0.23 24.4 (SL) ±0.05 21.4 25.0 (Backside PI coat) Ø1.0 (Good device hole) 1.6 (Backside PI coat) 1.0 (SL) LH168PF MAX. (Resin area) 20.4 ±0.015 W0.04±0.015 P0.070 x (332 – 1) x 0.99866 = 23.139 11.95 (SR) 11.95 (SR) 24.0±0.04(Mark) 24.4 (SL) 25.0 (Backside PI coat) [26.0 (E.L.)] Flexible slit ZO103 0.8 (SL) 12.6 (SL) 12.3 (SR) 24.2 (SL) ±0.05 (Holes) 23.6 P0.46 x (52 – 1) x 0.99869 = 23.429±0.03 W0.23±0.02 ±0.5 (Good device hole) 11.5 5.0 (SL) 7.0 (SL) 5.0 (SL) 5.0 (SL) 8.0 (SL) 12.6 (SL) 12.3 (SR) 0.8 (SL) 34.975 31.82 [26.0 (E.L.)] Device center Film center DUMMY VCOM6 VCOM5 VCOM4 DUMMY GND VLS V10 V8 V6 V4 V2 V0 LBR ZI0 ZI1 ZI2 ZI3 ZI4 ZI5 LS SPIO VCC CK MODE GND SPOI YI0 YI1 YI2 YI3 YI4 YI5 XI0 XI1 XI2 XI3 XI4 XI5 DUMMY V1 V3 V5 V7 V9 VLS GND DUMMY VCOM3 VCOM2 VCOM1 DUMMY Flexible slit 4.75±0.05 1.42±0.05 4.3MAX.(Resin area) 1.42±0.05 (0.035) Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 FQ-VLP 15 µm Polyimide SSF (0.07) 2-R0.5 (Cu) 2-Ø0.6 (PI hole) Chip center Sprocket center Flexible slit 2-Ø0.8 (Cu hole) 2-R0.7 (SR) 2-Ø1.2 (PI hole) 2-Ø1.8 (Cu) 0.2 0.3 0.5 0.2 35 mm Super wide 5 pitches [0.3] 1.0MAX. Total 0.75MAX. Backside (Unit : mm) [0.65] [1.65TYP. (1.50MIN.)] (0.05) ø Tape Material Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 FQ-VLP 15 µm Polyimide SSF ±0.02 ZO1 YO1 XO1 VCOM3 VCOM3 VCOM3 VCOM2 VCOM2 VCOM2 VCOM2 VCOM2 VCOM1 VCOM1 35 mm Super wide 5 pitches ZO54 YO54 XO54 ZO53 YO53 XO53 ZO52 YO52 DUMMY DUMMY DUMMY XO52 ZO51 YO51 XO51 ZO50 YO50 XO50 Tape width Tape type Perforation pitch 23.0 (SL) 23.0 (SL) 20.0±0.05 20.4MAX. (Resin area) VCOM6 VCOM6 VCOM5 VCOM5 VCOM5 VCOM5 VCOM5 VCOM4 VCOM4 VCOM4 ZO103 YO103 XO103 ø Tape Specification Flexible slit 23.6 (Backside PI coating) Flexible slit 1.42±0.05 2-R0.5 2-R0.5 1.4 (SL) 12.3 (SR) 12.0 (SL) 24.2 (SL) 23.6±0.05(Holes) P0.46 x (52 – 1) x 0.99869 = 23.429±0.025 W0.23±0.02 11.5±0.5(Good device hole) 5.0 (SL) 5.0 (SL) 5.0 (SL) 7.0 (SL) 8.0 (SL) 1.4 (SL) 12.3 (SR) 12.0 (SL) 34.975 31.82 [26.0 (E.L.)] Device center 2-Ø0.6 (PI hole) 0.15 Pattern side MAX. 4.75±0.05 1.42±0.05 4.3MAX. (Resin area) Film center (0.1) Flexible slit Chip center Sprocket center 2-R0.9 (Cu) 2-R0.6 (SR) 2-Ø1.2 (PI) 2-Ø0.8 (Cu hole) 0.2 0.3 0.5 0.2 DUMMY VCOM6 VCOM5 VCOM4 GND VLS V10 V8 V6 V4 V2 V0 LBR ZI0 ZI1 ZI2 ZI3 ZI4 ZI5 LS SPIO VCC CK MODE GND DUMMY SPOI YI0 YI1 YI2 YI3 YI4 YI5 XI0 XI1 XI2 XI3 XI4 XI5 POL V1 V3 V5 V7 V9 VLS GND DUMMY VCOM3 VCOM2 VCOM1 DUMMY 2-R0.5 (Cu) [0.75] P0.070 x (332 – 1) x 0.99866 = 23.139±0.015 W0.04±0.015 23.6 (Backside PI coating) 11.95 (SR) 11.95 (SR) ±0.02 (Mark) 23.968 24.8 (SL) 25.4 (Backside PI coating) [26.0 (E.L.)] [0.3] 1.0MAX. Total 0.75MAX. Backside PACKAGES FOR LCD DRIVERS 1.6 (Backside PI coating) 4.3 (Backside PI coating) 6.0 (SL) ±0.05 7.2 0.8 (SL) (Hole) 8.2±0.15(SR) (On the output leads) 10.4 (SL) [11.4 (E.L.)] [19.45 (E.L.)] 11.7 12.45 (SL) 5.2 (SL) ±0.15 (SR) 6.4 (On the output leads) 7.4±0.05(Mark) [8.05 (E.L.)] 12.7±0.5(Good device hole) 15 1.0 (SL) [0.40] 1.6 (Backside PI coating) 1.0 (SL) [1.65TYP. (1.50MIN.)] 0.24±0.02 ] 0.5 (SL) 4.5 (SL) 10.5 (SL) 4.9 (Backside PI coating) 20 [3.2TYP. (3.05MIN.)] 2.4 (SL) 0. Ø1.0 (Good device hole) 4.6 (SL) [C LH168PF1 1.6 (Backside PI coating) 1.0 (SL) 0.24 2.5±0.05 2.1 (Backside PI coating) [0.65] [1.65TYP. (1.50MIN.)]