July 1997 FDC6304P Digital FET, Dual P-Channel General Description Features These P-Channel enhancement mode field effect transistor are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance at low gate drive conditions. This device is designed especially for application in battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. SOT-23 SuperSOTTM-6 SuperSOTTM-8 -25 V, -0.46 A continuous, -1.0 A Peak. RDS(ON) = 1.5 Ω @ VGS= -2.7 V RDS(ON) = 1.1 Ω @ VGS = -4.5 V. Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model. SO-8 SOIC-16 SOT-223 Mark: .304 Absolute Maximum Ratings Symbol 4 3 5 2 6 1 TA = 25oC unless other wise noted Parameter FDC6304P Units VDSS Drain-Source Voltage -25 V VGSS Gate-Source Voltage -8 V ID Drain Current -0.46 A - Continuous - Pulsed -1 PD Maximum Power Dissipation TJ,TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm) (Note 1a) (Note 1b) 0.9 W 0.7 -55 to 150 °C 6.0 kV THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W © 1997 Fairchild Semiconductor Corporation FDC6304P Rev.D Electrical Characteristics (TA = 25 OC unless otherwise noted ) Symbol Parameter Conditions Min -25 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 o C IDSS Zero Gate Voltage Drain Current VDS = -20 V, VGS = 0 V IGSS Gate - Body Leakage Current VGS = -8 V, VDS= 0 V V TJ = 55°C ON CHARACTERISTICS Gate Threshold Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 o C VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA RDS(ON) Static Drain-Source On-Resistance µA -10 µA -100 nA On-State Drain Current Forward Transconductance mV /o C 2.1 -0.65 -0.86 -1.5 V VGS = -2.7 V, ID = -0.25 A 1.22 1.5 Ω VGS = -4.5 V, ID = -0.5 A 0.87 1.1 1.21 2 TJ =125°C gFS -1 (Note 2) ∆VGS(th)/∆TJ ID(ON) mV /o C -22 VGS = -2.7 V, VDS = -5 V -0.5 VGS = -4.5 V, VDS = -5 V -1 A VDS = -5 V, ID= -0.5 A 0.8 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 62 pF 35 pF 9.5 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge (Note 2) VDD = -6 V, ID = -0.5 A, VGS = -4.5 V, RGEN = 50 Ω VDS = -5 V, ID = - 0.25 A, VGS = -4.5 V 7 20 ns 8 20 ns 55 110 ns 35 70 ns 1.1 1.5 nC 0.32 nC 0.28 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.5 A (Note 2) -0.88 -0.5 A -1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 140OC/W on a 0.125 in2 pad of 2oz copper. b. 180OC/W on a 0.005 in2 of pad of 2oz copper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDC6304P Rev.D Typical Electrical Characteristics -3.5 -3.0 -1.25 R DS(on), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) VGS = -4.5V DRAIN-SOURCE ON-RESISTANCE 2.5 -1.5 -2.7 -1 -2.5 -0.75 -0.5 -2.0 -0.25 -1.5 0 V GS = -2.0 V 2 -2.5 -3.0 -3.5 -1 -2 -3 -4 -4.5 1 0.5 0 -2.7 1.5 -5 0 0.25 R DS(on) , ON-RESISTANCE (OHM) R DS(ON) , NORMALIZED 1 5 1.6 DRAIN-SOURCE ON-RESISTANCE 0.75 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. I D = -0.25A V GS = -2.7V 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 T J, JUNCTION TEMPERATURE (°C) 125 J 3 2 1 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 Figure 4. On Resistance Variation with Gate-To- Source Voltage. 0.5 = -55°C -I , REVERSE DRAIN CURRENT (A) T I D = -0.5A 125°C V GS , GATE TO SOURCE VOLTAGE (V) -1 V DS = -5V 25°C 4 0 150 Figure 3. On-Resistance Variation with Temperature. 25°C -0.75 125°C -0.5 -0.25 VGS = 0V 0.1 T J = 125°C 25°C 0.01 -55°C S I D , DRAIN CURRENT (A) 0.5 -ID , DRAIN CURRENT (A) V DS, DRAIN-SOURCE VOLTAGE (V) 0 -0.5 -1 -1.5 -2 -2.5 V GS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. -3 0.0001 0 0.2 0.4 0.6 0.8 1 -V SD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC6304P Rev.D Typical Electrical And Thermal Characteristics 150 VDS = 5V I D = -0.25A 100 10V 15V 4 Ciss 50 CAPACITANCE (pF) -V GS , GATE-SOURCE VOLTAGE (V) 5 3 2 Coss 20 1 Crss f = 1 MHz 10 V GS = 0 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 5 0.1 Q g , GATE CHARGE (nC) 2 15 25 5 1m s 10 m s 1 IT IM )L ON ( S RD POWER (W) 10 0m s 1s 0.1 0.03 VGS = -4.5V SINGLE PULSE RθJA = See Note 1a A T = 25°C A 0.01 0.1 0.2 0.5 SINGLE PULSE 4 DC R =See note 1a TA = 25°C θJ A 3 2 1 1 2 5 10 20 0 0.01 40 0.1 - V DS , DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. 1 10 SINGLE PULSE TIME (SEC) 100 300 Figure 10. Single Pulse Maximum Power Dissipation. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE -I D , DRAIN CURRENT (A) 0.5 1 5 10 , DRAIN TO SOURCE VOLTAGE (V) DS Figure 8. Capacitance Characteristics. Figure 7. Gate Charge Characteristics. 0.3 0.3 -V 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 0.0001 RθJA (t) = r(t) * R θJA R θJA = See Note 1b 0.1 P(pk) 0.05 t1 0.02 0.01 Single Pulse t2 TJ - TA = P * R JA(t) θ Duty Cycle, D = t 1/ t 2 0.001 0.01 0.1 1 10 100 300 t 1, TIME (sec) Figure 11. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal response will change depending on the circuit board design. FDC6304P Rev.D