PHILIPS TDA4685

INTEGRATED CIRCUITS
DATA SHEET
TDA4685
Video processor with automatic
cut-off control
Product specification
Supersedes data of May 1993
File under Integrated Circuits, IC02
1997 Jun 20
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
FEATURES
• Operates from an 8 V DC supply
• Black level clamping of the colour difference, luminance
and RGB input signals with coupling-capacitor DC level
storage
• Two analog RGB inputs, selected either by fast switch
signals or via I2C-bus; brightness and contrast control of
both RGB inputs
The required input signals are:
• Saturation, contrast, brightness and white adjustment
via I2C-bus
• 2 or 3-level sandcastle pulse for internal timing pulse
generation
• Luminance and negative colour difference signals
• Same RGB output black levels for Y/CD and RGB input
signals
• I2C-bus data and clock signals for microcontroller
control.
• Timing pulse generation from either a 2 or 3-level
sandcastle pulse for clamping, vertical synchronization
and cut-off timing pulses
Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector and the
other from an on-screen display generator. The TDA4685
includes full I2C-bus control of all parameters and
functions with automatic cut-off control of the picture tube
cathode currents. It provides RGB output signals for the
video output stages.
• Automatic cut-off control or clamped output selectable
via I2C-bus
• Automatic cut-off control with picture tube leakage
current compensation
• Cut-off measurement pulses after end of the vertical
blanking pulse or end of an extra vertical flyback pulse
The TDA4685 is a simplified, pin compatible (except for
pin 18) version of the TDA4680. The module address via
I2C-bus can be used for both ICs; where a function is not
included in the TDA4685 the I2C-bus command is not
executed. The differences with the TDA4680 are:
• Two switch-on delays to prevent discolouration before
steady-state operation
• Average beam current and peak drive limiting
• No automatic white level control; the white levels are
determined directly by the I2C-bus data
• PAL/SECAM or NTSC matrix selection via I2C-bus
• Emitter-follower RGB output stages to drive the video
output stages
• RGB reference levels for automatic cut-off control are
not adjustable via I2C-bus
• I2C-bus controlled DC output e.g. for hue-adjust of
NTSC (multistandard) decoders.
• Clamping delay is fixed
• Only contrast and brightness adjust for the RGB input
signals
GENERAL DESCRIPTION
• The measurement lines are triggered either by the
trailing edge of the vertical component of the sandcastle
pulse or by the trailing edge of an optional external
vertical flyback pulse (on pin 18), according to which
occurs first.
The TDA4685 is a monolithic integrated circuit with a
luminance and a colour difference interface for video
processing in TV receivers. Its primary function is to
process the luminance and colour difference signals from
a colour decoder which is equipped e.g. with the
multistandard decoder TDA4655 or TDA9160 plus delay
line TDA4661 and the Picture Signal Improvement (PSI)
IC, TDA467X, or from a feature module.
The TDA4686 is like TDA4685 but intended for double line
frequency application.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA4685
1997 Jun 20
DIP28
DESCRIPTION
plastic dual in-line package; 28 leads (600 mil)
2
VERSION
SOT117-1
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VP
supply voltage (pin 5)
7.2
8.0
8.8
V
IP
supply current (pin 5)
−
60
−
mA
V8(p-p)
luminance input (peak-to-peak value)
−
0.45
−
V
V6(p-p)
−(B − Y) input (peak-to-peak value)
−
1.33
−
V
V7(p-p)
−(R − Y) input (peak-to-peak value)
−
1.05
−
V
V14
3-level sandcastle pulse
H+V
−
2.5
−
V
H
−
4.5
−
V
BK
−
8.0
−
V
H+V
−
2.5
−
V
BK
−
4.5
−
V
2-level sandcastle pulse
Vi(p-p)
RGB input signals at pins 2, 3, 4, 10, 11 and 12
(peak-to-peak value)
−
0.7
−
V
Vo(b-w)
RGB outputs at pins 24, 22 and 20 (black-to-white value)
−
2.0
−
V
Tamb
operating ambient temperature
0
−
70
°C
1997 Jun 20
3
1997 Jun 20
4
1
2
3
4
G2
B2
6
−(B − Y)
R2
7
−(R − Y)
FSW2
8
12
B1
Y
11
13
FSW1
10
14
sandcastle
pulse
G1
18
VFB
R1
28
SCL
I2C-bus
27
I2C-bus data and
control signals
SATURATION
ADJUST
NMEN
2 x 8-BIT
CONTROL
REGISTERS
B
G
R
26
R
CONTRAST
ADJUST
4 x 6-BIT
D/A
CONVERTERS
timing
pulses
TIMING
GENERATOR
1ST AND 2ND
SWITCH-ON
DELAYS
B
G
R
VP = 8 V
5
SUPPLY
R
BRIGHTNESS
ADJUST,
G
BLANKING 2,
MEASUREMENT B
PULSES
PEAK DRIVE
AND
AVERAGE
BEAM CURRENT
LIMITING
6-BIT D/A
CONVERTER
9
WHITE
POINT
ADJUST
3 x 6-BIT
D/A
CONVERTERS
B
G
R
B
21
G
23
CUT-OFF
ADJUST,
OUTPUT
STAGES
R
20
22
24
15
16
17
BO
GO
RO
MED708
RGB
outputs
average
beam
current
peak drive
limiting
storage
leakage
storage
RC
cut-off
control
cut-off storage
25
BCOF
CUT-OFF
COMPARATORS
19
leakage
and cut-off
current input
Video processor with automatic cut-off control
Fig.1 Block diagram.
FAST SIGNAL
G
SOURCE SWITCH,
BLANKING 1
B
FSDIS2, FSON2,
FSDIS1, FSON1
BCOF
SANDCASTLE BK
PULSE
H+V
DETECTOR
(H)
TDA4685
A05 to A00, A15 to A10, A25 to A20, A35 to A30
AA5 to AA0
PAL/SECAM,
NTSC
MATRIX
SC5
BREN
I2C-BUS
RECEIVER
handbook, full pagewidth
SDA
A45 to A40, A55 to A50, A65 to A60
hue control voltage
Philips Semiconductors
Product specification
TDA4685
BLOCK DIAGRAM
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
PINNING
SYMBOL PIN
DESCRIPTION
FSW2
1
fast switch 2 input
R2
2
red input 2
G2
3
green input 2
B2
4
blue input 2
VP
5
supply voltage
−(B − Y)
6
colour difference input −(B − Y)
FSW2 1
28 SCL
−(R − Y)
7
colour difference input −(R − Y)
R2 2
27 SDA
Y
8
luminance input
G2 3
26 HUE
GND
9
ground
B2 4
25 CR
R1
10
red input 1
VP 5
24 RO
−(B − Y) 6
23 CG
G1
11
green input 1
B1
12
blue input 1
FSW1
13
fast switch 1 input
SC
14
sandcastle pulse input
BCL
15
average beam current limiting input
CPDL
16
storage capacitor for peak drive
limiting
CL
17
storage capacitor for leakage current
VFB
18
vertical flyback pulse input
CI
19
cut-off measurement input
BO
20
blue output
CB
21
blue cut-off storage capacitor
GO
22
green output
CG
23
green cut-off storage capacitor
RO
24
red output
CR
25
red cut-off storage capacitor
HUE
26
hue control output
SDA
27
I2C-bus serial data input;
acknowledge output
SCL
28
I2C-bus serial clock input
1997 Jun 20
handbook, halfpage
−(R − Y) 7
TDA4685
22 GO
Y 8
21 CB
GND 9
20 BO
R1 10
19 CI
G1 11
18 VFB
B1 12
17 CL
16 CPDL
FSW1 13
15 BCL
SC 14
MED709
Fig.2 Pin configuration.
5
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
I2C-BUS PROTOCOL
I2C-BUS RECEIVER (MICROCONTROLLER WRITE MODE)
Control
Each transmission to the I2C-bus receiver consists of at
least three bytes following the START bit. Each byte is
acknowledged by an acknowledge bit immediately
following each byte. The first byte is the Module Address
(MAD) byte, also called slave address byte. This includes
the module address, 1000100 for the TDA4685.
The TDA4685 is a slave receiver (R/W = 0), therefore the
module address byte is 10001000 (88H; see also Fig.3).
The I2C-bus transmitter provides the data bytes to select
and adjust the following functions and parameters:
• Brightness adjust
• Saturation adjust
• Contrast adjust
• DC output e.g. for hue control
The length of a data transmission is unrestricted, but the
module address and the correct subaddress must be
transmitted before the data byte(s). The order of data
transmission is shown in Figs 4 and 5.
Without auto-increment (BREN = 0 or 1) the module
address (MAD) byte is followed by a SubAddress (SAD)
byte and one data byte only (see Fig.4).
• RGB gain adjust
• Peak drive limiting level adjust
• Selects either 3-level or 2-level (5 V) sandcastle pulse
• Enables cut-off control; enables output clamping
• Selects either PAL/SECAM or NTSC matrix
• Enables/disables synchronization of the execution of
I2C-bus commands with the vertical blanking interval
• Enables Y/CD, RGB1 or RGB2 input.
I2C-bus transmitter and data transfer
I2C-BUS SPECIFICATION
The I2C-bus is a bidirectional, two-wire, serial data bus for
intercommunication between ICs in an equipment.
The microcontroller transmits data to the I2C-bus receiver
in the TDA4685 over the serial data line SDA (pin 27)
synchronized by the serial clock line SCL (pin 28). Both
lines are normally connected to a positive voltage supply
through pull-up resistors. Data is transferred when the
SCL line is LOW. When SCL is HIGH the serial data line
SDA must be stable. A HIGH-to-LOW transition of the SDA
line when SCL is HIGH is defined as a START bit.
A LOW-to-HIGH transition of the SDA line when SCL is
HIGH is defined as a STOP bit.
Each transmission must start with a START bit and end
with a STOP bit. The bus is busy after a START bit and is
only free again after a STOP bit has been transmitted.
1997 Jun 20
6
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
MSB
handbook, full pagewidth
1
TDA4685
LSB
0
0
0
1
0
0
module address
0
ACK
R/W
MED710
Fig.3 The module address byte.
handbook, full pagewidth
STA
MAD SAD
STO
MED697
START
condition
data byte
STOP
condition
Fig.4 Data transmission without auto-increment (BREN = 0 or 1).
handbook, full pagewidth
STA
MAD SAD
STO
MED698
START
condition
STOP
condition
data byte
data bytes
Fig.5 Data transmission with auto-increment (BREN = 0).
1997 Jun 20
7
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
AUTO-INCREMENT
CONTROL REGISTER 2
The auto-increment format enables quick slave receiver
initialization by one transmission, when the I2C-bus control
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.
FSON2 (Fast Switch 2 ON).
If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive subaddresses (see Fig.5).
FSDIS1 (Fast Switch 1 Disable).
All subaddresses from 00H to 0FH are automatically
incremented, the subaddress counter wraps round from
0FH to 00H. Reserved subaddresses 07H, 08H, 09H,
0BH, 0EH and 0FH are treated as legal but have no effect.
Subaddresses outside the range 00H and 0FH are not
acknowledged by the device.
• FSON2 has priority over FSON1
FSDIS2 (Fast Switch 2 Disable).
FSON1 (Fast Switch 1 ON).
The RGB input signals are selected by FSON2 and
FSON1 or FSW2 and FSW1:
• FSW2 has priority over FSW1
• FSDIS1 and FSDIS2 disable FSW1 and FSW2
(see Table 2).
BCOF (Black level Control Off):
Subaddresses are stored in the TDA4685 to address the
following parameters and functions (see Table 1):
0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are
clamped to fixed DC levels.
• Brightness adjust
• Saturation adjust
When the supply voltage has dropped below
approximately 6.0 V (usually occurs when the TV receiver
is switched on or the supply voltage is interrupted) all data
and function bits are set to 01H.
• Contrast adjust
• Hue control voltage
• RGB gain adjust
• Peak drive limiting adjust
• Control register functions.
The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.
CONTROL REGISTER 1
NMEN (NTSC Matrix Enable):
0 = PAL/SECAM matrix
1 = NTSC matrix.
BREN (Buffer Register Enable):
0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to
the data registers during the next vertical blanking
interval.
The I2C-bus receiver does not accept any new data until
this data is transferred into the data registers.
SC5 (SandCastle 5 V):
0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.
1997 Jun 20
TDA4685
8
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
Table 1
TDA4685
Subaddress (SAD) and data bytes; note 1
SAD
(HEX)
MSB
D7
D6
D5
D4
D3
D2
D1
D0
Brightness
00
0
0
A05
A04
A03
A02
A01
A00
Saturation
01
0
0
A15
A14
A13
A12
A11
A10
Contrast
02
0
0
A25
A24
A23
A22
A21
A20
Hue control voltage
03
0
0
A35
A34
A33
A32
A31
A30
Red gain
04
0
0
A45
A44
A43
A42
A41
A40
Green gain
05
0
0
A55
A54
A53
A52
A51
A50
Blue gain
06
0
0
A65
A64
A63
A62
A61
A60
Reserved
07
0
0
X
X
X
X
X
X
Reserved
08
0
0
X
X
X
X
X
X
Reserved
09
0
0
X
X
X
X
X
X
FUNCTION
LSB
Peak drive limit
0A
0
0
AA5
AA4
AA3
AA2
AA1
AA0
Reserved
0B
X
X
X
X
X
X
X
X
Control register 1
0C
SC5
X
BREN
X
NMEN
X
X
X
Control register 2
0D
X
X
X
BCOF
FSDIS2
FSON2
FSDIS1
FSON1
Reserved
0E
X
X
X
X
X
X
X
X
Reserved
0F
X
X
X
X
X
X
X
X
Note
1. X = don’t care, but for software compatibility with other or future video ICs it is recommended to set all X to logic 0.
1997 Jun 20
9
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
Table 2
TDA4685
Signal input selection by the fast source switches; notes 1 to 4
I2C-BUS CONTROL BITS
ANALOG SWITCH SIGNALS
FSON2 FSDIS2 FSON1 FSDIS1
L
L
L
L
L
L
L
H
L
L
H
X
L
H
L
L
FSW2
(PIN 1)
FSW1
(PIN 13)
L
L
L
H
H
X
L
X
H
X
L
X
H
X
X
L
X
H
L
H
L
H
X
X
L
H
H
X
X
X
H
X
X
X
X
X
INPUT SELECTED
RGB2
RGB1
Y/CD
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Notes
1. H: logic HIGH implies that the voltage >0.9 V.
2. L: logic LOW implies that the voltage <0.4 V.
3. X = don’t care.
4. ON indicates the selected input signal.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VP
supply voltage (pin 5)
−
8.8
V
Vi
input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25)
−0.1
+VP
V
input voltage (pins 15, 18 and 19)
−0.7
VP + 0.7
V
input voltage (pins 27 and 28)
−0.1
+8.8
V
V14
sandcastle pulse voltage
−0.7
VP + 5.8
V
Iav
average current (pins 20, 22 and 24)
−10
+4
mA
IM
peak current (pins 20, 22 and 24)
−20
+4
mA
I26
output current
−8
+0.6
mA
Tstg
storage temperature
−20
+150
°C
Tamb
operating ambient temperature
0
70
°C
Ptot
total power dissipation
−
1.2
W
1997 Jun 20
10
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
CHARACTERISTICS
All voltages are measured in test circuit of Fig.9 with respect to GND (pin 9); VP = 8.0 V; Tamb = 25 °C; nominal signal
amplitudes (black-to-white) at output pins 24, 22 and 20; nominal settings of brightness, contrast, saturation and white
level control; without beam current or peak drive limiting; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pin 5)
VP
supply voltage
7.2
8.0
8.8
V
IP
supply current
−
60
−
mA
notes 1 and 2
−
1.33
−
V
Colour difference inputs [−(B − Y): pin 6; −(R − Y): pin 7]
V6(p-p)
−(B − Y) input (peak-to-peak value)
V7(p-p)
−(R − Y) input (peak-to-peak value)
notes 1 and 2
−
1.05
−
V
V6,7
internal DC bias voltage
at black level clamping
−
4.1
−
V
I6,7
input current
during line scan
−
−
0.1
µA
at black level clamping
100
−
−
µA
10
−
−
MΩ
R6,7
input resistance
Luminance/sync (VBS; Y: pin 8)
Vi(p-p)
luminance input voltage at pin 8
(peak-to-peak value)
note 2
−
0.45
−
V
V8(bias)
internal DC bias voltage
at black level clamping
−
4.1
−
V
I8
input current
during line scan
−
−
0.1
µA
at black level clamping
100
−
−
µA
10
−
−
MΩ
−
0.7
−
V
R8
input resistance
RGB input 1 (R1: pin 10; G1: pin 11; B1: pin 12)
Vi(p-p)
input voltage at pins 10, 11 and 12
(peak-to-peak value)
note 2
V10/11/12(bias) internal DC bias voltage
at black level clamping
−
5.7
−
V
I10/11/12
during line scan
−
−
0.1
µA
at black level clamping
100
−
−
µA
10
−
−
MΩ
R10/11/12
input current
input resistance
RGB input 2 (R2: pin 2, G2: pin 3, B2: pin 4)
Vi(p-p)
input voltage at pins 2, 3 and 4
(peak-to-peak value)
note 2
−
0.7
−
V
V2/3/4
internal DC bias voltage
at black level clamping
−
5.7
−
V
I2/3/4
input current
during line scan
−
−
0.1
µA
at black level clamping
100
−
−
µA
10
−
−
MΩ
R2/3/4
1997 Jun 20
input resistance
11
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4685
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fast signal switch FSW1 (pin 13) to select Y, CD or R1, G1, B1 inputs (control bits: see Table 2)
V13
voltage to select Y and CD
−
−
0.4
V
voltage to select R1, G1, B1
0.9
−
5.0
V
R13
internal resistance to ground
−
4.0
−
kΩ
∆t
difference between transit times for
signal switching and signal insertion
−
−
10
ns
Fast signal switch FSW2 (pin 1) to select Y, CD/R1, G1, B1 or R2, G2, B2 inputs (control bits: see Table 2)
voltage to select Y, CD/R1, G1, B1
−
−
0.4
V
voltage to select R2, G2, B2
0.9
−
5.0
V
R1
internal resistance to ground
−
4.0
−
kΩ
∆t
difference between transit times for
signal switching and signal insertion
−
−
10
ns
V1
Saturation adjust [acts on −(R − Y) and −(B − Y) signals under I2C-bus control; subaddress 01H (bit resolution
1.5% of maximum saturation); data byte 3FH for maximum saturation, data byte 23H for nominal saturation
and data byte 00H for minimum saturation]
ds
saturation below maximum
at 23H
−
5
−
dB
at 00H; f = 100 kHz
−
50
−
dB
Contrast adjust [acts on internal RGB signals under I2C-bus control; subaddress 02H (bit resolution 1.5% of
maximum contrast); data byte 3FH for maximum contrast, data byte 22H for nominal contrast and data byte
00H for minimum contrast]
dc
contrast below maximum
at 22H
−
5
−
dB
at 00H
−
22
−
dB
Brightness adjust [acts on internal RGB signals under I2C-bus control; subaddress 00H (bit resolution 1.5%
of maximum brightness); data byte 3FH for maximum brightness, data byte 26H for nominal brightness and
data byte 00H for minimum brightness]
dbr
black level shift of nominal signal
amplitude referred to cut-off
measurement level
at 3FH
−
30
−
%
at 00H
−
−50
−
%
White potentiometers [under I2C-bus control; subaddresses 04H (red), 05H (green) and 06H (blue); data byte
3FH for maximum gain; data byte 19H for nominal gain and data byte 00H for minimum gain]; note 3
∆Gv
1997 Jun 20
relative to nominal gain
increase of gain
at 3FH
−
50
−
%
decrease of gain
at 00H
−
50
−
%
12
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4685
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RGB outputs (pins 24, 22 and 20; positive going output signals; peak drive limiter set = 3FH); note 4
Vo(b-w)
∆Vo
Vo
nominal output signals
(black-to-white value)
−
2.0
−
V
maximum output signals
(black-to-white value)
3.0
−
−
V
spread between RGB output signals
−
−
10
%
minimum output voltages
−
−
0.8
V
maximum output voltages
6.8
−
−
V
2.3
2.5
2.7
V
V24,22,20
voltage of cut-off measurement line
equivalent to voltage during
ultra-black
output clamping;
BCOF = 1
Iint
internal current sources
−
5.0
−
mA
Ro
output resistance
−
20
−
Ω
Frequency response
fres
frequency response of Y path
(from pin 8 to pins 24, 22 and 20)
f = 10 MHz
−
−
3
dB
frequency response of CD path
(from pins 7 to 24 and 6 to 20)
f = 8 MHz
−
−
3
dB
frequency response of RGB1 path
(from pins 10 to 24, 11 to 22 and
12 to 20)
f = 10 MHz
−
−
3
dB
frequency response of RGB2 path
(from pins 2 to 24, 3 to 22 and
4 to 20)
f = 10 MHz
−
−
3
dB
for horizontal and vertical blanking
pulses
2.0
2.5
3.0
V
for horizontal pulses (line count)
4.0
4.5
5.0
V
for burst key pulses (clamping)
7.6
−
VP + 5.8 V
for horizontal and vertical blanking
pulses
2.0
2.5
3.0
for burst key pulses
4.0
4.5
VP + 5.8 V
−
−
−100
µA
−
1.5
−
µs
Sandcastle pulse detector (pin 14)
CONTROL BIT SC5 = 0; 3-LEVEL; notes 5 and 6
V14
sandcastle pulse voltage
CONTROL BIT SC5 = 1; 2-LEVEL; notes 5 and 6
V14
sandcastle pulse voltage
V
GENERAL
I14
output current
td
leading edge delay of the clamping
pulse
1997 Jun 20
V14 = 0 V
13
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4685
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vertical flyback (pin 18); note 6
V18
vertical flyback pulse
internal voltage
I18
for LOW
−
−
2.5
V
for HIGH
4.5
−
−
V
pin 18 open-circuit;
note 7
−
5.0
−
V
−
−
5
µA
input current
Average beam current limiting (pin 15); note 8
Vc(15)
contrast reduction starting voltage
−
4.0
−
V
∆Vc(15)
voltage difference for full contrast
reduction
−
−2.0
−
V
Vbr(15)
brightness reduction starting voltage
−
2.5
−
V
∆Vbr(15)
voltage difference for full brightness
reduction
−
−1.6
−
V
Peak drive limiting voltage [pin 16; internal peak drive limiting level (Vpdl) acts on RGB outputs under I2C-bus
control; subaddress 0AH]; note 9
V20,22,24
I16
minimum RGB output voltages
at 00H
maximum RGB output voltages
at 3FH
charge current
discharge current
during peak white
−
−
3.0
V
7.0
−
−
V
−
−1
−
µA
−
5
−
mA
V16
internal voltage limitation
4.5
−
−
V
Vc(16)
contrast reduction starting voltage
−
4.0
−
V
∆Vc(16)
voltage difference for full contrast
reduction
−
−2.0
−
V
Vbr(16)
brightness reduction starting voltage
−
2.5
−
V
∆Vbr(16)
voltage difference for full brightness
reduction
−
−1.6
−
V
Automatic cut-off control (pin 19); notes 6 and 10 to 12; see Fig.7
V19
external voltage
−
−
VP − 1.4 V
I19
output current
−
−
−60
µA
input current
150
−
−
µA
−
additional input current
switch-on delay 1
−
0.5
V24,22,20
monitor pulse amplitude (under
I2C-bus control; subaddress 0AH)
switch-on delay 1;
note 11
−
Vpdl − 1.0 −
V
V19(th)
voltage threshold for picture tube
cathode warming up
switch-on delay 1
−
4.5
−
V
Vref
internally controlled voltage
during leakage
measurement period
−
2.7
−
V
∆V19
difference between VMEAS (cut-off
measurement voltage) and Vref
−
1.0
−
V
1997 Jun 20
14
mA
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
SYMBOL
PARAMETER
TDA4685
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Cut-off storage (pins 25, 23 and 21)
I21,23,25
charge and discharge currents
during cut-off
measurement lines
−
0.3
−
mA
input currents of storage inputs
outside measurement
time
−
−
0.1
µA
charge and discharge currents
during leakage
measurement period
−
0.4
−
mA
leakage current
outside measurement
time
−
−
0.1
µA
−
2.5
−
V
Storage of leakage information (pin 17)
I17
V17
threshold voltage for reset to
switch-on state
Hue control (under I2C-bus control; subaddress 03H; data byte 3FH for maximum voltage; data byte 20H for
nominal voltage and data byte 00H for minimum voltage); note 13
V26
output voltage
Iint
at 3FH
4.8
−
−
V
at 20H
−
3.0
−
V
at 00H
−
−
1.2
V
500
−
−
µA
current of the internal current source
at pin 26
I2C-bus receiver clock SCL (pin 28)
fSCL
input frequency range
0
−
100
kHz
VIL
LOW-level input voltage
−
−
1.5
V
VIH
HIGH-level input voltage
3.0
−
6.0
V
IIL
LOW-level input current
−
−
−10
µA
IIH
HIGH-level input current
−
−
10
µA
tL
clock pulse LOW
4.7
−
−
µs
tH
clock pulse HIGH
4.0
−
−
µs
tr
rise time
−
−
1.0
µs
tf
fall time
−
−
0.3
µs
I2C-bus
receiver data input/output SDA (pin 27)
VIL
LOW-level input voltage
−
−
1.5
V
VIH
HIGH-level input voltage
3.0
−
6.0
V
IIL
LOW-level input current
−
−
−10
µA
IIH
HIGH-level input current
−
−
10
µA
IOL
LOW-level output current
3.0
−
−
mA
tr
rise time
−
−
1.0
µs
tf
fall time
−
−
0.3
µs
tSU;DAT
data set-up time
0.25
−
−
µs
1997 Jun 20
15
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
Notes to the characteristics
1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal.
2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω.
3. The white potentiometers affect the amplitudes of the RGB output signals.
4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.
5. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages
separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14
exceeds the defined internal threshold voltage.
The internal threshold voltages (control bit SC5 = 0) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for horizontal pulses
6.5 V for the burst key pulse.
The internal threshold voltages (control bit SC5 = 1) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for the burst key pulse.
6. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB
cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component.
In this case, the RGB output signals are blanked until the end of the last measurement line; see Fig.7a. If an extra
vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the end
of the VFB pulse; see Fig.7b. In this case, the output signals are blanked either until the end of the last measurement
line or until the end of the vertical component of the sandcastle pulse, according to which occurs last.
7. If no VFB pulse is applied, pin 18 can be left open-circuit or connected to VP. If pin 18 is always LOW neither
automatic cut-off control nor output clamping can happen.
8. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.
9. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness.
The maximum RGB outputs are determined via the I2C-bus under subaddress 0AH. When an RGB output exceeds
the maximum voltage, peak drive limiting is delayed by one horizontal line.
10. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off
measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black.
Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during
the vertical blanking interval (see Figs 6 and 7).
11. During picture cathode warming up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the
ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the
RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V,
the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control
stabilizes, RGB output blanking is removed.
12. Range of cut-off measurement level at the RGB outputs is 1 to 5 V. The recommended value is 3 V.
13. The hue control output at pin 26 is an emitter follower with current source.
1997 Jun 20
16
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
Table 3
TDA4685
Demodulator axes and amplification factors
PARAMETER
NTSC
PAL
(B − Y)* demodulator axis
0°
0°
(R − Y)* demodulator axis
115°
90°
(R − Y)* amplification factor
1.97
1.14
(B − Y)* amplification factor
2.03
2.03
Table 4
PAL/SECAM and NTSC matrix; note 1
MATRIX
NMEN
PAL/SECAM
0
NTSC
1
Note
1. PAL/SECAM signals are matrixed by the equation: VG − Y = −0.51VR − Y − 0.19VB − Y
NTSC signals are matrixed by the equations (hue phase shift of −5 degrees):
VR − Y* = 1.57VR − Y − 0.41VB − Y; VG − Y* = −0.43VR − Y − 0.11VB − Y; VB − Y* = VB − Y
In the matrix equations: VR − Y and VB − Y are conventional PAL demodulation axes and amplitudes at the output of
the NTSC demodulator. VG − Y*, VR − Y* and VB − Y* are the NTSC modified colour difference signals; this is equivalent
to the demodulator axes and amplification factors shown in Table 3. VG − Y* = −0.27VR − Y* − 0.22VB − Y*.
MHA697
handbook, full pagewidth
(1)
(2)
cut-off measurement line
for red signal
(1) Maximum brightness.
ultra-black
(2) Nominal brightness.
Fig.6 Cut-off measurement pulse.
1997 Jun 20
17
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
handbook, full pagewidth
sandcastle pulse
with vertical
component
R channel
LM
MR
G channel
LM
MG
B channel
LM
MB
MHA698
a. Timing controlled by sandcastle pulse.
vertical
flyback
handbook,
full pagewidth
pulse (VFB)
R channel
LM
MR
G channel
LM
MG
B channel
LM
MB
MHA699
b. Timing controlled by additional vertical flyback pulse (VFB).
LM = leakage current measurement time.
MR, MG, MB = R, G, B cut-off measurement pulses.
Fig.7 Leakage and cut-off current measurement timing diagram.
1997 Jun 20
18
CL
19
CL
+
3
26
diode protection
on all pins except
pins 5, 14, 27 and 28
2
27
CL
4
25
+
5
24
CL
6
23
CL
7
CL
TDA4685
22
8
21
Fig.8 Internal circuits.
handbook, full pagewidth
1997 Jun 20
1
28
9
20
CL
10
19
CL
11
18
CL
12
17
13
16
14
+
MED711
15
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
INTERNAL PIN CONFIGURATION
1997 Jun 20
20
75
Ω
75
Ω
220 µF
22 µH
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
75
Ω
−(R − Y)
Y
10 nF
47 nF
14
13
12
11
BR1(1)
1N4148
15
16
17
18
19
20
21
10
kΩ
BCL
220 nF
220 nF
220 nF
22 µF
1 µF
330 nF
CPDL
CL
VFB
CI
BO
CB
GO
CG
RO
CR
HUE
SDA 100 Ω
SCL 100 Ω
Fig.9 Test and application circuit.
3.9 kΩ
3.9 kΩ
22
23
24
25
26
27
28
TDA4685
10
9
8
7
6
5
4
3
2
1
1N4148
SC
FSW1
B1
G1
10 nF
10 nF
R1
10 nF
GND
−(B − Y)
10 nF
B2
10 nF
VP
G2
10 nF
10 nF
R2
10 nF
FSW2
82
kΩ
SCL SDA
hue
BZX79
C6V2
10
9
8
7
6
5
4
3
2
1
MED712
VFB
(optional)
CON2
CI
Bo
Go
Ro
GND
+12 V
200 V
Video processor with automatic cut-off control
(1) Insert link BR1 if average beam current is not required.
beam
current
information
VP = 8 V
SC
FSW1
B1
G1
R1
Y
−(R − Y)
−(B − Y)
B2
G2
R2
FSW2
handbook, full pagewidth
Philips Semiconductors
Product specification
TDA4685
TEST AND APPLICATION INFORMATION
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
PACKAGE OUTLINE
seating plane
handbook, full
pagewidthdual in-line package; 28 leads (600 mil)
DIP28:
plastic
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.20
0.020
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT117-1
051G05
MO-015AH
1997 Jun 20
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
21
Philips Semiconductors
Product specification
Video processor with automatic cut-off control
TDA4685
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 20
22
Philips Semiconductors
Product specification
Video processor with automatic cut-off
control
NOTES
1997 Jun 20
23
TDA4685
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Tel. +9-5 800 234 7381
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Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
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Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
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Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/05/03/pp24
Date of release: 1997 Jun 20
Document order number:
9397 750 01837