CXA2064M
US Audio Multiplexing Decoder
Description
The CXA2064M is an IC designed as a decoder for
the Zenith TV Multi-channel System. Functions
include stereo demodulation, SAP (Separate Audio
Program) demodulation, dbx noise reduction.
30 pin SOP (Plastic)
Features
• Adjustment free of VCO and filter.
• Audio multiplexing decoder and dbx noise
reduction decoder are all included in a single chip.
Almost any sort of signal processing is possible
through this IC.
• Various built-in filter circuits greatly reduce external
parts.
• This IC is near pin to pin compatible with the
CXA2020M.
Applications
TV, VCR and other decoding systems for US audio
multiplexing TV broadcasting
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC
11
V
• Operating temperature Topr –20 to +75
°C
• Storage temperature
Tstg –65 to +150
°C
• Allowable power dissipation
PD
1000
mW
• STID, SAPID drive current
IO
2 (max.)
mA
Structure
Bipolar silicon monolithic IC
Range of Operating Supply Voltage
9 ± 0.5
V
∗ This device is available only to the licensees of the dbx-TV noise
reduction system.
Standard I/O Level
• Input level
COMPIN (Pin 7)
• Output level
TVOUT-L/R (Pins 23 and 22)
100mVrms (MONO 100Hz 100% mod.)
490mVrms (MONO 100Hz 100% mod.)
VE
VEWGT
SAPOUT
SAPIN
VETC
VEOUT
VCAIN
TVOUT-L
TVOUT-R
VCATC
VCAWGT
MUTE
M1
FOMO
MAININ
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
STIN
SUBOUT
NOISETC
VCC
IREF
GND
COMPIN
SAPTC
VGR
PLINT
STID
SAPID
PCINT2
PCINT1
MAINOUT
Pin Configuration (Top View)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98513-PS
21
20
24
25
29 26
30
1
27
28
19
18
17
11
12
5
VGR
RMSDET
9
SW
LPF
IREF
MODE_DISPLAY
LPF
SAPID
RMSDET
VCA
STID
DETECTION
AMP
(+4dB)
HPF
VE
FOMO
IREF
SAPIND
DeEm
M1
8
LPF
MUTE
SAPTC
NOISE
DET
SAPVCO
SAPOUT
NOISETC 3
BPF
+6dB
SAPIN
GND 6
STIND
LPF
STIN
DeEm
VE
4
–
MATRIX
16
VETC
VEWGT
VCC
LPF
LPF
1/2
15
VEOUT
7
FLT
1/4
SUBOUT
2
MAINOUT
VCAIN
COMPIN
VCO
PCINT2
LFLT
10
PCINT1
PLINT
14 13
MAININ
VCAWGT
–2–
VCATC
Block Diagram
22 TVOUT-R
23 TVOUT-L
CXA2064M
CXA2064M
Pin Description
Pin
No.
Symbol
(Ta = 25°C, VCC = 9V)
Pin
voltage
Equivalent circuit
Description
VCC
1
STIN
23k
4.0V
Input the (L-R) signal from
SUBOUT (Pin 2).
23k
11.7k
147
147
1
27
SAPIN
4.0V
27
18k
Input the (SAP) signal from
SAPOUT (Pin 28).
18k
4V
4V
20k
Vcc
580
2
SUBOUT
2
4.0V
(L–R) signal output pin.
147
580
12k
4k
Vcc
3.3k
8k
10k
1k
3
NOISETC
3.0V
2k
4k
×2
4V
Vcc
3k
Set the time constant for the
noise detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
3k
200k
3
4
VCC
—
Supply voltage pin.
4
–3–
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
Description
VCC
40k
40k
30k
34k
15k
30k
×2
Set the filter and VCO
reference current.
(Connect a 68kΩ (±1%)
resistor between this pin and
GND.)
VCC
5
IREF
1.3V
30p 1.8k
5
147
6.3k
6
GND
16k
6
—
Analog block GND.
VCC
24k
24k
147
7
7
COMPIN
4.0V
Audio multiplexing signal
input pin.
50k
4V
24k
VCC
8k
10k
1k
3k
8
SAPTC
4.5V
VCC
4k
↓ 50µ
8
–4–
Set the time constant for the
SAP carrier detection circuit.
(Connect a 4.7µF capacitor
between this pin and GND.)
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
3k
9
VGR
1.3V
11k
9.7k
Description
147
VCC
19.4k
11k
×4
11k
Band gap reference output
pin.
(Connect a 10µF capacitor
between this pin and GND.)
9
2.06k
VCC
20k
20k
147
10
PLINT
10
5.1V
20k
↓
26µ
20k
20k ↓
50µ
10k
11
11
STID
—
12
68k
12
SAPID
—
15k
Pilot cancel circuit loop filter
integrating pin.
(Connect a 1µF capacitor
between this pin and GND.)
10.5k
–5–
Stereo detection pin.
Open collector output.
Drive current is 2mA (Max.).
SAP detection pin.
Open collector output.
Drive current is 2mA (Max.).
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
Description
VCC
147
13
13
PCINT2
10k
4.0V
10k
2k
×2
4k
Stereo block PLL loop filter
integrating pin.
VCC
147
14
14
PCINT1
30k
4.0V
22k
VCC
15k
×4
VCC
15
MAINOUT
4.0V
147
(L + R) signal output pin.
15
↓
200µ
1k
VCC
10k
VCC
16
MAININ
Input the (L + R) signal from
MAINOUT (Pin 15).
4.0V
147
16
47k
4V
17
17
FOMO
—
19
70k
10.5k
19
MUTE
—
–6–
50k
Mode control switch pin.
This pin has 3 ranges for
input voltage.
Sets forced monoral mode
and also control ST.ID.
Mode control switch pin.
When this pin is set to H level,
TVOUT output is muted.
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
Description
VCC
4V
Mode control switch pin.
This pin has 3 ranges for
input voltage.
Stereo, BOTH, SAP selection
are available.
24k
25k
18
M1
18
—
40k
10.5k
VCC
40k
40k 3p
580
20
VCAWGT
4.0V
20
2.9V
580 147
36k
↓
50µ
4k↓
8µ
30k
Weight the VCA control
effective value detection
circuit.
(Connect a 1µF capacitor
and a 3.9kΩ resistor in series
between this pin and GND.)
8k
VCC
×4
21
VCATC
21
×4
1.7V
↓
50µ
4k
↓
7.5µ
20k
Determine the restoration
time constant of the VCA
control effective value
detection circuit.
(the specified restoration
time constant can be
obtained by connecting a
10µF capacitor between this
pin and GND.)
VCC
3k
22
TVOUT-R
TVOUT right channel output
pin.
4.0V
580
22
23
23
TVOUT-L
580
TVOUT left channel output
pin.
4.0V
–7–
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
Description
VCC
47k
24
VCAIN
20k
4.0V
47k
VCA input pin.
Input the variable
de-emphasis output signal
from Pin 25 via a coupling
capacitor.
VCC
24
Vcc
5P
Variable de-emphasis output
pin.
(Connect a 4.7µF non-polar
capacitor between Pins 25
and 24.)
580
25
VEOUT
4.0V
25
580
10k
Vcc
26
VETC
1.7V
×4
Determine the restoration
time constant of the variable
de-rmphasis control effective
value detection circuit.
(the specified restoration
time constant can be
obtained by connecting a
3.3µF capacitor between this
pin and GND.)
26
×4
20k
↓ 7.5µ
4k
↓ 50µ
Vcc
5P
580
28
SAPOUT
4.0V
580
SAP FM detector output pin.
10k
28
147
24k
↓ 10µ
4k
↓ 50µ
–8–
CXA2064M
Pin
No.
Symbol
Pin
voltage
Eqivalent circuit
Description
Vcc
2.9V
580
29
VEWGT
4.0V
4V
29
147
580
36k
8k
30k
↓ 8µ
Weight the variable
de-emphasis control effective
value detection circuit.
(Connect a 0.047µF capacitor
and a 3kΩ resistor in series
between this pin and GND.)
4k
↓ 50µ
VCC
7.5k
30
VE
4.0V
Variable de-emphasis
integrating pin.
(Connect a 2700pF capacitor
and a 3.3kΩ resistor in series
between this pin and GND.)
147
30
–9–
– 10 –
SNmain
Vsub
FCsub
THDsub
THDsmax
SNsub
CTst
PCsub
Main S/N
Sub output level
Sub LPF frequency
characteristic
Sub distortion
Sub overload distortion
Sub S/N
ST → SAP
Crosstalk
Sub pilot leak
7
8
9
10
11
12
14
13
THDmmax
Main overload distortion
6
FCmain
Main LPF frequency
characteristic
4
THDm
FCdeem
Main de-emphasis
frequency characteristic
3
Main distortion
Vmain
Main output level
2
5
Icc
Signal
Current consumption
Item
ST
SAP
ST
ST
ST
ST
ST
MONO
MONO
MONO
MONO
MONO
MONO
Mode
7
7
7
7
7
7
7
7
7
7
7
7
7
—
Input pin
Min.
1kBPF
fH BPF
20 log
('M1 = L'/
'M1 = H')
0dB = 20mVrms
SUB (L-R) 1kHz,
100% mod., NR ON,
SAP Carrier (5fH)
PILOT (fH) 0dB
15kLPF
20 log
('100%'/'0%')
15kLPF
SUB (L-R) 1kHz,
200% mod., NR OFF
SUB (L-R) 1kHz,
NR OFF
15kLPF
20 log
('12k'/'1k')
SUB (L-R) 1kHz,
100% mod., NR OFF
SUB (L-R) 12kHz,
30% mod., NR OFF
SUB (L-R) 1kHz,
100% mod., NR OFF
15kLPF
15kLPF
Mono 1kHz 200% mod.
Pre-em. ON
Mono 1kHz,
Pre-em. ON
15kLPF
Mono 1kHz 100% mod.
Pre-em. ON
20 log
('100%'/'0%')
22/23
Mono 12kHz 30% mod. 20 log
('12k'/'1k')
Pre-em. ON
2
23
2
2
2
2
2
22/23
22/23
22/23
22/23
Mono 5kHz 30% mod.
Pre-em. ON
20 log
('5k'/'1k')
—
60
56
—
—
–3.0
225
61
—
—
–3.0
–1.2
440
22/23
Output
pin
Mono 1kHz 100% mod.
Pre-em. ON
Filter
15
Measurement
conditions
No signal
Input signal
Main (L + R) (Pre-Emphasis: OFF) = 100mVrms
SUB (L – R) (dbx-TV: OFF) = 200mVrms
Pilot= 20mVrms
SAP Carrier= 60mVrms
fH = 15.734kHz
1
No.
Electrical Characteristics
COMPIN input level
(100% modulation level)
–27
70
64
0.2
0.1
–0.5
275
69
0.15
0.1
–1.0
0
490
23
Typ.
–16
—
—
2.0
1.0
1.0
325
—
0.5
0.5
1.0
1.0
540
31
Max.
dB
dB
dB
%
%
dB
mVrms
dB
%
%
dB
dB
mVrms
mA
Unit
(Ta = 25°C, VCC = 9V)
CXA2064M
SAP
SAP
Vsap
FCsap
THDsap
SNsap
CTsap
SAP output level
SAP LPF frequency
characteristic
SAP distortion
SAP S/N
SAP → ST
Cross talk
SAP ON level
17
18
19
20
21
22
HYsap
STLsep1
STRsep1
STLsep2
STRsep2
SAP ON/OFF hysteresis
ST separation 1 L → R
ST separation 1 R → L
ST separation 2 L → R
ST separation 2 R → L
23
24
25
26
27
THsap
SAP
HYst
Stereo ON/OFF
hysteresis
16
– 11 –
ST
ST
ST
ST
SAP
ST
SAP
ST
THst
Stereo ON level
Mode
15
Signal
Item
No.
SAP 1kHz, NR OFF
7
7
7
7
7
7
7
28
SAP 1kHz 100% mod.
NR OFF
7
15kLPF
15kLPF
ST-R 300Hz 30% mod. 20 log
NR ON
('Rch'/'Lch')
20 log
('Lch'/'Rch')
20 log
('Rch'/'Lch')
ST-L 3kHz 30% mod.
NR ON
ST-R 3kHz 30% mod.
NR ON
15kLPF
15kLPF
20 log (‘on
level’/’off level’)
0dB = 60mVrms
1kBPF
ST-L 300Hz 30% mod. 20 log
NR ON
('Lch'/'Rch')
Change
SAP Carrier (5fH)
Level
SAP 1kHz 100% mod. 20 log ('M1 = H'/
NR ON, Pilot (fH)
'M1 = L')
20 log
('100%'/'0%')
15kLPF
28
SAP 10kHz 30% mod. 20 log
NR OFF
('10k'/'1k')
22/23
22/23
22/23
22/23
12
12
23
28
11
7
20 log (‘on
level'/'off level')
28
11
Output
pin
SAP 1kHz 100% mod.
NR OFF
15kLPF
Filter
7
0dB = 20mVrms
Measurement
conditions
Change
PILOT (fH) Level
Input signal
7
Input pin
23
23
23
23
2.0
–12.0
60
46
—
–3.0
130
2.0
–9.0
Min.
35
35
35
35
4.0
–9.0
70
55
2.5
0
170
6.0
–6.0
Typ.
—
—
—
—
6.0
–6.5
—
—
6.0
2.5
210
10.0
–3.0
Max.
dB
dB
dB
dB
dB
dB
dB
dB
%
dB
mVrms
dB
dB
Unit
CXA2064M
– 12 –
STIN
C19
4.7µ
2
C1
4.7µ
SUBOUT
1
R1
10k
3
C2
4.7µ
4
VCC
V1
9V
SG
ATT
GND
IREF
GND
7
GND
6
R2
68k
METAL
±1%
COMPIN
5
C3
4.7µ
8
C4
4.7µ
9
C5
10µ
10
C6
1µ
11
R3
10k
12
R4
10k
R5
1MEG
R6
C8
100k 0.012µ
C7
5600p
14
VE
13
16
17
18
19
20
S1
21
S2
22
S3
23
C10
1µ
R7
3.9k
VEWGT
C11
10µ
TANTALUM
24
C12
4.7µ
25
C13
4.7µ
26
C14
4.7µ
V2
5V
SAPOUT
V3
2.5V
MEASURES
27
C15
3.3µ
TANTALUM
15kHz LPF
fH BPF
1kHz BPF
FILTERS
SAPIN
28
C16
4.7µ
BUFF
VETC
29
C17
0.047µ
R8
5k
S9
S8
S7
S6
S5
S4
VEOUT
NOISETC
VCAIN
VCC
TVOUT-L
SAPTC
TVOUT-R
VGR
VCATC
PLINT
VCAWGT
STID
MUTE
SAPID
M1
PCINT2
FOMO
PCINT1
MAININ
15
MAINOUT
30
C18
2700P
R9
3.3k
Electrical Characteristics Measurement Circuit
C9
4.7µ
CXA2064M
CXA2064M
Adjustment Method
1. Input level adjustment
1) Connect components as shown in Fig. 1.
2) Set the US MPX encoder output to MONO 100Hz 100% modulation.
3) Adjust the "ATT" so that COMPIN (Pin 7) level goes to 100mVrms (±0.5dB).
2.Separation adjustment
1) Mode control pin are set to FOMO (Pin 17): L, M1 (Pin 18): L, MUTE (Pin 19): L.
2) Set the US MPX encoder ouput to Stereo Lch-only 300Hz 30% modulation, NR-ON.
Then, adjust the variable resistor of SUBOUT (Pin 2) to reduce the TVOUT-R output to the minimum.
3) Next, set the frequency only of the input signal to 3kHz and adjust the variable resistor of VEWGT (Pin 29)
to reduce the TVOUT-R output to the minimum.
4) The adjustments in 2 and 3 above are performed to optimize the separation.
US MPX encoder
CXA2064M
ATT
4.7µ
COMPIN (Pin 7)
Fig. 1. Adjustment setup
∗ Adjust this IC through Tuner and IF when this IC is mounted on the set.
– 13 –
CXA2064M
Description of Operation
The US audio multiplexing system possesses the base band spectrum shown in Fig. 2.
PEAK DEV
kHz
50
AM-DSB-SC
50
L-R
dbx-TV
NR
25
PILOT
25
15
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
L+R
5
50 – 15kHz
2fH
fH
3fH
4fH
TELEMETRY
FM 3kHz
3
5fH
6fH
6.5fH
f
fH = 15.734kHz
Fig. 2. Base band spectrum
2fHL0°
fHL90°
fHL0°
PLL
(VCO 8fH)
ST.ID
PILOT DET
MODE CONTROL
MAIN LPF DE.EM
(COMPIN) STEREO LPF
7
(MAIN IN)
(MAIN OUT)
PILOT
CANCEL
16
15
4.7µ
L+R
SUB LPF
(SUBOUT)
L-R (DSB)
DET
MATRIX
2
(STIN)
10k
1
23
NR SW
4.7µ
SAP BPF
SAP(FM)
DET
SAP LPF
(SAP OUT)
INJ.
LOCK
A
(SAP IN)
28
B
dbx-TV
BLOCK
27
MODE
CONTROL
NOISE
DET
SAP.ID
MODE CONTROL
Fig. 3. Overall block diagram (See Fig. 4 for the dbx-TV block)
(ST IN)
1
NR SW
A
FIXED
DEEMPHASIS
VARIABLE
DEEMPHASIS (VE OUT)
(VCA IN)
25
(SAP IN)
24
4.7µ
27
HPF
RMS
DET
LPF
LPF
RMS
DET
Fig 4. dbx-TV block
– 14 –
B
VCA
(TVOUT-R)
22
4.7µ
SAP
DET
(TVOUT-L)
to MATRIX
CXA2064M
(1) L + R (MAIN)
When the audio multiplexing signal is inputted to COMPIN (Pin 7), the SAP signal and telemetry signal
are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and
SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized)
and input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no
carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM
modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave)
to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency
components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW
circuit.
(3) SAP
SAP is an FM signal using 5fH as a carrier as shown in the Fig. 2. First, the SAP signal only is
extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency
components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal
is input to the dbx-TV block via the NRSW circuit.
(4) Mode discrimination
Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is
performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the
noise near 25kHz after FM detection of SAP signal.
(5) dbx-TV block
Either the L – R signal or SAP signal input respectively from STIN (Pin 1) or SAPIN (Pin 27) is
selected by the mode control and input to the dbx-TV block.
The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external
capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a
current to a voltage using an operational amplifier and then input to the matrix.
The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of
effective value detection circuits. Each of the effective value detection circuits passes the input signal
through a predetermined filter for weighting before the effective value of the weighted signal is
detected to provide the control signal.
(6) Matrix
The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and
SAP signals according to the mode control and whether there is ST / SAP discrimination.
(7) Others
“Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to
the resistor connecting IREF (Pin 5) with GND become the reference current.
– 15 –
CXA2064M
Decoder Output and Mode Control Table
ID
MONO
STEREO
MONO & SAP
STEREO & SAP
Pin
Output
ST
SAP
M1
FOMO
dbx
input
H
H
L
∗
MUTE
L+R
L+R
H
H
M
∗
MUTE
L+R
L+R
H
H
H
∗
MUTE
L+R
L+R
L
H
L
L
L–R
L
R
L
H
L
M
MUTE
L+R
L+R
H
H
L
H
MUTE
L+R
L+R
L
H
M
L
MUTE
L+R
L+R
L
H
M
M
MUTE
L+R
L+R
H
H
M
H
MUTE
L+R
L+R
L
H
H
L
L–R
L
R
L
H
H
M
MUTE
L+R
L+R
H
H
H
H
MUTE
L+R
L+R
H
L
L
∗
MUTE
L+R
L+R
H
L
M
∗
SAP
L+R
SAP
H
L
H
L
SAP
SAP
SAP
H
L
H
M
SAP
L+R
SAP
H
L
H
H
SAP
L+R
SAP
L
L
L
L
L–R
L
R
L
L
L
M
MUTE
L+R
L+R
H
L
L
H
MUTE
L+R
L+R
L
L
M
L
SAP
L+R
SAP
L
L
M
M
SAP
L+R
SAP
H
L
M
H
SAP
L+R
SAP
L
L
H
L
SAP
SAP
SAP
L
L
H
M
SAP
L+R
SAP
H
L
H
H
SAP
L+R
SAP
Input signal mode
Lch
Rch
∗: Don’t care
Regarding ST, SAP, ID
L shows that drive current runs through load register and pin voltage is low.
H shows that drive current doesn't run through load resistor and pin voltage is high.
– 16 –
CXA2064M
Limits of Control Voltage
M1
H
SAP
M
BOTH
L
FOMO
MUTE
4.5V to VCC
2 to 3V (or OPEN)
STEREO 0 to 0.5V
H
STID-H
8.5V to VCC
M
STID-L
3 to 7V
L
STID-L
0 to 0.5V (or OPEN)
H
ON
3V to VCC
L
OFF
0 to 0.5V (or OPEN)
– 17 –
– 18 –
COMP IN
GND
IREF
C3
4.7µ
R10
10k
7
GND
6
R2
68k
METAL
±1%
COMPIN
5
SAPTC
8
C4
4.7µ
VGR
9
C5
10µ
PLINT
10
STID
C6
1µ
STID
11
R3
10k
R4
10k
C7
5600p
PCINT2
R6
C8
SAPID 100k 0.012µ
V2
3 to VCC
12
SAPID
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
R1
10k
VCC
4
V1
9V
VE
STIN
C2
4.7µ
VEWGT
SUBOUT
C1
4.7µ
SAPOUT
NOISETC
14
SAPIN
2
R5
1MEG
VETC
PCINT1
13
VEOUT
1
VCC
VCAIN
3
16
17
18
19
20
21
22
23
C10
1µ
TVOUT-L
C11
10µ
TANTALUM
TVOUT-R
24
C12
4.7µ
VCATC
25
C13
4.7µ
VCAWGT
26
C14
4.7µ
MODE CONTROL SW
MUTE
27
C15
3.3µ
TANTALUM
R7
3.9k
M1
28
C16
4.7µ
TVOUT-L TVOUT-R
FOMO
29
C17
0.047µ
R8
5k
MAININ
30
C18
2700P
R9
3.3k
Application Circuit
MAINOUT
15
C9
4.7µ
CXA2064M
CXA2064M
Input level vs. Distortion characteristics 2 (Stereo)
Input level vs. Distortion characteristics 1 (MONO)
10
Input signal: Stereo L = –R
(dbx-TVNR ON), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF, ST mode
Measurement point: TVOUT-L/R
Distortion [%]
Distortion [%]
1.0
Input signal: MONO (Pre-emphasis on), 1kHz
0dB = 100% modulation level
VCC = 9V, 30kHz using LPF
Measurement point: TVOUT-L/R
1.0
0.1
Standard level (100%)
–10
0
10
Standard level (100%)
Input level [dB]
–10
0
Input level [dB]
Input level vs. Distortion characteristics 3 (SAP)
Distortion [%]
10
Input signal: SAP (dbx-TVNR ON)
1kHz, 0dB = 100% modulation
level
VCC = 9V, 30kHz using LPF, SAP mode
Measurement point: TVOUT-L/R
1.0
Standard level (100%)
–10
0
Input level [dB]
10
– 19 –
10
CXA2064M
Stereo LPF frequency characteristics
Main LPF and Sub LPF frequency characteristics
10
Gain (FC main and FC sub) [dB]
30
Gain [dB]
5
0
–5
20
10
0
–10
–20
–30
–40
–10
–50
0
20
40
60
80
1
100
Frequency [kHz]
100
20
90
5fH
70
60
50
0
40
Group delay [µs]
Gain [dB]
80
Gain
30
–10
20
Group delay
3.8fH
–20
20
40
60
80
5
7
10
20
Frequency [kHz]
SAP frequency characteristics and group delay
10
2
6.2fH
100
10
0
120
Frequency [kHz]
– 20 –
50 70 100
CXA2064M
Package Outline
Unit: mm
30PIN SOP(PLASTIC)
+ 0.4
2.3 – 0.15
+ 0.4
18.8 – 0.1
0.1
30
+ 0.2
0.1 – 0.05
(9.3)
A
0.5 ± 0.2
10.3 ± 0.4
+ 0.3
7.6 – 0.1
16
15
1
0.45 ± 0.1
1.27
0.2
M
+ 0.1
0.2 – 0.05
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SOP-30P-L03
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SOP030-P-0375
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.7g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 21 –