SANYO LC7574NW

Ordering number : EN3586A
CMOS LSI
LC7574NE, 7574NW
1/2 Duty VFD Driver for Frequency Display
Overview
Package Dimensions
The LC7574NE and LC7574NW are 1/2 duty VFD
drivers that can be used for electronic tuning frequency
display and other applications under the control of a
controller. These products can directly drive VFDs with
up to 74 segments.
unit: mm
3156-QFP48E
[LC7574NE]
Features
• 74 segment outputs
• Noise reduction circuits are built into the output drivers.
• Serial data input supports CCB* format
communications with the system controller.
• Switching between digital and analog dimmers under
serial data control
• High generality since display data is displayed without
the intervention of a decoder
• All segments can be turned off with the BLK pin
SANYO: QFP48E
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
unit: mm
3163A-SQFP48
[LC7574NW]
SANYO: SQFP48
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O2095HA (OT)/4032JN No. 3586-1/10
LC7574NE, 7574NW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Maximum supply voltage
Input voltage
Output voltage
Output current
Allowable power dissipation
Conditions
Ratings
Unit
VDD max
VDD
–0.3 to +6.5
V
VFL max
VFL
–0.3 to +21.0
V
VIN1
DI, CL, CE, BLK, DIM
VIN2
OSC
–0.3 to +6.5
V
–0.3 to VDD + 0.3
V
V
VOUT1
S1 to S37, G1, G2
–0.3 to VFL + 0.3
VOUT2
OSC
–0.3 to VDD + 0.3
IOUT1
S1 to S37
IOUT2
G1, G2
Pd max
5
Ta = 85°C (LC7574NE)
Ta = 85°C (LC7574NW)
V
mA
67
mA
250
mW
150
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–50 to +125
°C
Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter
Symbol
Conditions
min
typ
max
Unit
VDD
VDD
4.5
5.0
5.5
V
VFL
VFL
8
12
18
V
Input high level voltage
VIH
DI, CL, CE, BLK
0.8 VDD
5.5
V
Input low level voltage
VIL
DI, CL, CE, BLK
0
0.2 VDD
Supply voltage
V
Guaranteed oscillator range
fOSC
OSC
Recommended external
resistance
ROSC
OSC
12
kΩ
Recommended external
capacitance
COSC
OSC
50
pF
0.4
1.6
3.0
MHz
Low level clock pulse width
tøL
CL: Figure 1
0.5
µs
High level clock pulse width
tøH
CL: Figure 1
0.5
µs
Data setup time
tds
DI, CL: Figure 1
0.5
µs
Data hold time
tdh
DI, CL: Figure 1
0.5
µs
CE wait time
tcp
CE, CL: Figure 1
0.5
µs
CE setup time
tcs
CE, CL: Figure 1
0.5
µs
CE hold time
tch
CE, CL: Figure 1
0.5
µs
BLK switching time
tc
BLK, CE: Figure 3
10
Input voltage range
VIN
DIM
µs
0
+5.5
V
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Conditions
Input high level current
IIH
DI, CL, CE, BLK, DIM: VI = 5.5 V
Input low level current
IIL
DI, CL, CE, BLK, DIM: VI = 0 V
Output high level voltage
min
typ
max
Unit
5
µA
–5
µA
VOH1
S1 to S37: IO = 2 mA
VFL – 0.6
V
VOH2
G1, G2: IO = 25 mA
VFL – 0.6
V
VOH3
G1, G2: IO = 50 mA
VFL – 1.3
Output low level voltage
VOL
S1 to S37, G1, G2: IO = –5 µA, Ta = 25°C
Oscillator frequency
fOSC
ROSC = 12 kΩ, COSC = 50 pF
Hysteresis voltage
VH
DI, CL, CE, BLK
A/D converter linearity error
Err
DIM
Current drain
IDD
Outputs open: fOSC = 1.6 MHz
0.125
V
0.25
0.5
1.6
MHz
0.5
–1/2
V
V
+1/2
LSB
10
mA
No. 3586-2/10
LC7574NE, 7574NW
Pin Assignment
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1
No. 3586-3/10
LC7574NE, 7574NW
Block Diagram
Pin Functions
Pin No.
Handling
when unused
Pin
I/O
Function
4
VFL
—
Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied.
—
1
VDD
—
Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied.
—
46
VSS
—
Ground. Must be connected to the system ground.
—
48
OSC
I/O
47
BLK
I
44
CL
43
DI
42
CE
Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor
to this pin.
Display off control input
BLK = low (VSS): Display off (G1 and G2 = low)
BLK = high (VDD): Display on
Note that serial data can be transferred while the display is turned off.
CL: synchronization clock
DI: transfer data
CE: chip enable
VDD
GND
I
Serial data transfer inputs. These pins must be
connected to the system controller.
DIM
I
When the analog dimmer is selected, the analog voltage applied to this pin controls the duty of the G1
and G2 digit output pins. Since a 6-bit A/D converter is applied to this analog voltage and that result is
input to a decoder that provides a built-in dimmer curve, the relationship between the analog voltage
and the duty can be specified as a mask program. Note that 63/96 · VDD is the full-scale level for the
6-bit A/D converter.
2, 3
G1, G2
O
Digit outputs. The frame frequency fO is (fOSC/4096) Hz
Open
41 to 5
S1 to S37
O
Segment outputs for displaying the display data transferred by serial data input.
Open
45
GND
GND
No. 3586-4/10
LC7574NE, 7574NW
Serial Data Transfer Format
1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 2
CCB address: Transfer 1010B, as shown in Figure 2.
M0:
Digital/analog dimmer selection data
M0 = 0 ....................................Digital dimmer
M0 = 1 ....................................Analog dimmer
DM0 to DM9: Dimmer data
This data controls the duty of the G1 and G2 digit output pins when the digital dimmer is selected.
This data consists of 10 bits, of which DM0 is the LSB. Note that display intensity can be adjusted by
controlling the duty of the G1 and G2 digit output pins. (The DM0 to DM9 dimmer data is ignored
when the analog dimmer is selected.)
SD1 to SD74: Display data
SD1 to SD37...........................Display data for the G1 digit output pin
SD38 to SD74.........................Display data for the G2 digit output pin
SDn (n = 1 to 74) = 1..............Display on
SDn (n = 1 to 74) = 0..............Display off
T0:
Test data
The T0 bit must be set to 0.
No. 3586-5/10
LC7574NE, 7574NW
Serial Data Format
Correspondence between Display Data (SD1 to SD74) and Segment Output Pins
Segment output pin
G1
G2
Segment output pin
G1
G2
S1
SD1
SD38
S20
SD20
SD57
S2
SD2
SD39
S21
SD21
SD58
S3
SD3
SD40
S22
SD22
SD59
S4
SD4
SD41
S23
SD23
SD60
S5
SD5
SD42
S24
SD24
SD61
S6
SD6
SD43
S25
SD25
SD62
S7
SD7
SD44
S26
SD26
SD63
S8
SD8
SD45
S27
SD27
SD64
S9
SD9
SD46
S28
SD28
SD65
S10
SD10
SD47
S29
SD29
SD66
S11
SD11
SD48
S30
SD30
SD67
S12
SD12
SD49
S31
SD31
SD68
S13
SD13
SD50
S32
SD32
SD69
S14
SD14
SD51
S33
SD33
SD70
S15
SD15
SD52
S34
SD34
SD71
S16
SD16
SD53
S35
SD35
SD72
S17
SD17
SD54
S36
SD36
SD73
S18
SD18
SD55
S37
SD37
SD74
S19
SD19
SD56
Example: Segment output pin S11 is controlled as follows:
Display data
SD11
SD48
Segment output pin S11 state
0
0
The segments corresponding to both the G1 and G2 digit output pins are off.
0
1
The segment corresponding to the G2 digit output pin is on.
1
0
The segment corresponding to the G1 digit output pin is on.
1
1
The segments corresponding to both the G1 and G2 digit output pins are on.
No. 3586-6/10
LC7574NE, 7574NW
BLK and the Display Control
Since the LSI internal data (SD1 to SD74 and the control data) is undefined when power is first applied, the display is
off (G1 and G2 = low) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at
power on can be prevented by transferring all 92 bits of serial data from the controller while the display is off and setting
BLK pin high after the transfer completes. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3)
• Power on: Logic block power supply (VDD) on → Driver block power supply (VFL) on
• Power off: Driver block power supply (VFL) off → Logic block power supply (VDD) off
Figure 3
Output Waveforms (S1 to S37)
No. 3586-7/10
LC7574NE, 7574NW
Relation between Segment and Digit Outputs
Figure 4
Descriptions
1. Consider the examples shown in Figure 4, where data is set up so that the segment outputs S1 to S37 output a low
level on the G1 digit output timing and a high level on the G2 digit output timing. (Here, the G2 side being lighted)
2. The digit output G1 and G2 waveforms in Example 1 are output when the 10 bits of dimmer data (DM0 to DM9) are
set to 3FEH. The relation between t1 and the oscillator frequency fOSC is:
t1 = 2/fOSC.
For example, if fOSC = 1.6 [MHz], then
t1 = 2/1.6 [MHz] = 1.25 [µs].
Note that t1 and t2 are the same period in Example 1.
3. The digit output G1 and G2 waveforms in Example 2 are those when the dimmer data (DM0 to DM9) are set to a
smaller value. Although the time t1, which is from the point where digit output falls to segment output changes, does
not change, the time t2, which is from the point where segment output changes to the time the digit output rises,
becomes longer. When the dimmer data (DM0 to DM9) are set to 0FFH and fOSC is 1.6 [MHz], then the frame
frequency fO is:
fO = 1/(t3 × 2)
= fOSC/4096
= 391 [Hz],
and,
t3 = 1.28 [ms].
Therefore,
t2 =
(1.28 [ms] – 1.25 [µs] × 2) × (3FFH – 0FFH)
= 0.96 [ms].
1023
4. When the dimmer data (DM0 to DM9) are set to an even smaller value, the time t2, which is from the point where
segment output changes to the time the digit output rises, becomes even longer, as in Example 3. Note that t1 does
not change here, either.
No. 3586-8/10
LC7574NE, 7574NW
Sample Application Circuit
Usage Notes
1. Notes on the segment and digit waveforms
Figure 5
No. 3586-9/10
LC7574NE, 7574NW
The segment waveform is distorted by the VFD panel used and the wiring, and furthermore, in the case of being used
with essentially no dimming as in the digit waveform 1, as shown in Figure 5, the VFD panel glow dimly. By
carefully considering the segment waveform, it can be seen that this problem can be resolved by applying an
adequate amount of dimming, as shown in Digit waveform 2. When fOSC is 1.6 [MHz], we recommend using 10 bits
of dimmer data in the range 000H to 3E0H.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1995. Specifications and information herein are subject to
change without notice.
PS No. 3586-10/10