OKI ML2110

OKI Semiconductor
ML2110
FEDL2110-01
Issue Date: Mar. 25, 2002
Speech Control Processor
GENERAL DESCRIPTION
The ML2110 is a speech processor LSI device with internal D/A converter. It is optimized for text-to-speech
synthesis.
FEATURES
• Parallel and serial interfaces
• Single 3.3V power supply
• 5V interface available
• Internal 12bit D/A Converter
• Package:
144-pin plastic LQFP (LQFP144-P-2020-0.50-K) (ML2110TC)
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FEDL2110-01
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ML2110
BLOCK DIAGRAM
CLK
CLKENA
CLKEDBL
CLKA
CLKB
TSTM2-0
EXTINT1-0
BR3
BGT3
PD7-0
PACK
PSTB
PCS
PIOA
PIBF
POBF
RST
STBY
PLL
RAM1KNB
RAM1KNB
RAM1KNB
TST
RAM1KNB
CPU
PIO
MFU32
TMR
TMR
TXD
RXD
DTR
DSR
RTS
CTS
SCLK
A23-0
D31-0
ROM
SRAM
RD
WR0-3
AS
SIO
DRAMC
USR
DAC
RAS
CAS3-0
WE
UPORT1-0
DOUT
XSYNC
BCLK
DAO
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ML2110
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54
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52
51
50
49
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46
45
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43
42
41
40
39
38
37
VDD
D24
D23
D22
D21
D20
D19
GND
D18
D17
D16
D15
D14
D13
VDD
D12
D11
D10
D9
D8
D7
GND
D6
D5
D4
D3
D2
D1
VDD
D0
PIOA
PCS
PACK
PSTB
POBF
GND
PIN CONFIGURATION (TOP VIEW)
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98
99
100
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102
103
104
105
106
107
108
PIBF
PD7
PD6
PD5
PD4
PD3
VDD
PD2
PD1
PD0
SCLK
DTR
DSR
GND
RTS
CTS
RXD
TXD
CLKFDBL
CLKB
VDD
CLKA
CLKENA
XO
CLK
RST
STBY
GND
GND
VDD
VDD
DAO
GND
GND
109
110
111
112
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16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EXTINT0
UPORT1
UPORT0
TSTM1
TSTM2
VDD
TSTM0
AS
RD
WR0
WR1
WR2
GND
WR3
WAIT
RAS
CAS0
CAS1
CAS2
VDD
CAS3
WE
ROM
SRAM
GND
GND
EXTINT1
MD
VDD
BCLK
XSYNC
VDD
BR3
BGT3
GND
DOUT
D25
D26
D27
D28
D29
D30
GND
D31
A0
A1
A2
A3
A4
VDD
A5
A6
A7
A8
A9
A10
GND
A11
A12
A13
A14
A15
A16
VDD
A17
A18
A19
A20
A21
A22
A23
GND
144-PIN Plastic LQFP
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FEDL2110-01
OKI Semiconductor
ML2110
PIN DESCRIPTIONS
Symbol
I/O
Description
D 31-0
I/O
32-bit data bus. 8-bit devices are accessed through D31-24. 16-bit devices
are accessed through D31-D16.
A23-0
O
24-bit address bus. DRAM addresses are output from A13-0.
ROM
O
SRAM
O
RD
O
Read signal. RD is active during both 8-bit and 16-bit reads.
WR0-3
O
Write signals. WR0 corresponds to writes from D31-24, WR1 corresponds to
writes from D23-16, WR2 corresponds to writes from D15-8, and WR3
corresponds to writes from D7-0.
RAS
O
Row address strobe.
CAS0-3
O
WE
O
AS
O
Address strobe.
TXD
O
Serial data output.
RXD
I
Serial data input.
DTR
O
Control signal indicating SIO can transmit and receive.
DSR
I
Input signal indicating that modem is in operable state.
RTS
O
SIO transmit request signal.
CTS
I
Input signal indicating that modem can transmit.
SCLK
O
Synchronous transfer clock output.
PD7-0
I/O
Parallel port data input/output.
PACK
I
Parallel port read signal. Set high for Centronics interface.
PSTB
I
Parallel port write signal. Strobe signal for Centronics interface.
PCS
I
Parallel port chip select signal.
PIOA
I
Parallel port address signal. Selects data or status during an access.
POBF
3-state
Output port buffer full. Indicates that data has been set in the output buffer.
PIBF
3-state
Input port buffer full. Indicates that there is data in the input buffer.
Busy output signal for Centronics interface.
ROM select signal. ROM indicates that ROM space is assigned to the
specified address. It is used as a chip select signal.
SRAM select signal. SRAM indicates that SRAM space is assigned to the
specified address. It is used as a chip select signal.
Column address strobe. CAS0 corresponds to accesses from D31-24,CAS1
corresponds to accesses from D23-16, CAS2 corresponds to accesses from
D15-8, and CAS3 corresponds to accesses from D7-0.
Write enable. WE is active during writes to DRAM space as the DRAM write
signal.
UPORT1-0
O
General flag output signal.
XSYNC
I
Synchronous transmit clock.
BCLK
I
Shift clock for DOUT.
DOUT
O
Digital signal output.
DAO
O
D/A Converter output.
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Symbol
ML2110
I/O
Description
CLK
I
Clock input signal.
XO
O
Clock signal. Inverse of CLK.
CLKA
O
Internal clock signal.
CLKB
O
Internal clock signal. Inverse of CLK.
CLKENA
I
Clock change signal.
CLKFDBL
I
Clock cycle change signal.
RST
I
Reset input.
STBY
I
Standby signal. STBY suspends operation and places ML2110 in a standby
state.
EXTINT1-0
I
External interrupt signal.
WAIT
I/O
BR3
I
Cache/BIU test signal.
BGT3
O
Cache/BIU test signal.
MD
I
16/32 bit select signal.
TSTM2-0
I
Test mode select input signal.
Wait signal. Normally, it is pulled up ‘H’ level.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Storage Temperature
Symbol
VDD
Vin
Tstg
Condition
Ta = 25
Ta = 25
—
Rating
–0.3 to 4.5
–0.3 to 5.5
–55 to 125
Unit
V
V
°C
Rating
3.0 to 3.6
–40 to 85
Unit
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
Symbol
VDD
Top
Condition
—
—
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
"H" Input Voltage
"L" Input Voltage
"H" Input Voltage
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Typ.
Max.
Unit
—
—
V
—
0.8
V
—
—
V
Symbol
VIH
VIL
VIH
Condition
Excluding CLK
Excluding CLK
CLK
Min.
2.2
—
0.8 VDD
"L" Input Voltage
VIL
CLK
—
"H" Output Voltage
VOH
IOH = –4 mA
2.4
—
—
V
"L" Output Voltage
VOL
IOL = 4 mA
—
—
0.4
V
—
0.2 VDD
V
Input Leakage Current
ILI
0 < VIN < VDD
–10
+10
µA
Output Leakage Current
ILO
–10
+10
µA
Dynamic Supply Current
IDO
Static Supply Current
D/A Output Relative
Accuracy
D/A Output Impedance
IDS
0 < VOUT < VDD
VDD = 3.6 V,
fOPE = 33 MHz
—
|VDAE|
RDA
—
—
150
mA
—
—
1.5
mA
No load
—
—
10
mV
—
12
20
28
kΩ
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ML2110
AC Characteristics
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Source Oscillation Frequency
Input Clock Low-Level
Minimum Width
Input Clock High-Level
Minimum Width
Operating Period
CLKA Delay Time
XO Delay Time
Required RST Time
A Delay Time
D Setup Time
D Hold Time
D Delay Time
RD Delay Time
fOSC
—
20
—
33
MHz
tW_CLKL
—
13
—
—
ns
tW_CLKH
—
8
—
—
ns
tCYC
tCLK
tXO
—
—
—
—
—
—
—
—
—
Falling
Rising
—
—
30
—
—
1024
—
10
2
—
—
—
—
—
2
—
—
—
—
—
—
—
—
—
—
—
—
—
50
12
7
—
29
—
—
32
25
22
22+0.5 tCYC
23
—
ns
ns
ns
WR Delay Time
UPORT Delay Time
EXTINT Setup Time
tW_RST
tA
tS_D
tH_D
tD
tRD
tWR
tUPORT
tS_EXINT
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
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ML2110
ROM, SRAM Access
Parameter
Symbol
RD Pulse Width
tW_RD
WR Pulse Width
tW_WR
A to RD Time
tW_ARD
A to WR Time
tW_AWR
WR to SRAM Time
tW_WRSRAM
ROM Delay Time
SRAM Delay Time
tROM
tSRAM
ROM Pulse Width
tW_ROM
SRAM Pulse Width
tW_SRAM
WR to D Time
tW_WRD
Condition
ROM, SRAM
3τ to 12τ access
ROM, SRAM
3τ to 12τ access
ROM, SRAM
3τ , 4τ access
ROM, SRAM
5τ to 12τ access
SRAM
3τ to 12τ access
SRAM
3τ to 12τ access
—
—
ROM
3τ to 12τ access
SRAM
3τ to 12τ access
SRAM
3τ access
ROM, SRAM
4τ to 12τ access
Min.
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Typ.
Max.
Unit
2
—
11
tCYC
1.5
—
10.5
tCYC
—
1
—
tCYC
—
2
—
tCYC
—
1
—
tCYC
—
1
—
tCYC
—
—
—
—
21+0.5 tCYC
21+0.5 tCYC
ns
ns
3
—
12
tCYC
3
—
12
tCYC
—
0
—
tCYC
—
1
—
tCYC
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ML2110
DRAM Access
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
tRAS
—
3
1
—
—
—
24
Note 1
—
ns
tCYC
tCYC
—
—
22+0.5tCYC
ns
—
1.5
4
0.5
1.5
1.5
—
3
—
—
—
—
—
—
—
—
—
1
22
2
5
1
2
2
23
Note 1
—
ns
tCYC
tCYC
ns
tCYC
tCYC
ns
tCYC
tCYC
RAS Delay Time
RAS Pulse Width
A to RAS Time
tW_RAS
tW_ARAS
CAS Delay Time
tCAS
CAS Pulse Width
tW_CAS
A to CAS Time
RAS to CAS Time
WE to CAS Time
WE Delay Time
WE Pulse Width
A to WE Time
Required
Precharge Time
CAS to RAS Time
CAS to D Time
tW_ACAS
tW_RASCAS
tW_WECAS
tWE
tW_WE
tW_AWE
—
—
—
2nt access falling
edge
Normal
Normal
Refresh
—
—
—
—
—
—
tW_PREC
—
1
—
Note 2
tCYC
tW_CASRAS
tW_EDO
—
Hyper Mode
—
—
1
—
—
1
tCYC
tCYC
Symbol
Condition
Min.
Typ.
Max.
Unit
tAS
—
—
—
27
ns
General Device Access
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
AS Delay Time
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ML2110
When DS bit = 0
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
AS Pulse Width
A to AS Time
RD Pulse Width
A to RD Time
WR Pulse Width
A to WR Time
D to WR Time
Symbol
tW_AS
tW_AAS
tW_RD
tW_ARD
tW_WR
tW_AWR
tW_DWR
Condition
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
Min.
Typ.
Max.
Unit
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
—
0
—
tCYC
—
0
—
tCYC
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OKI Semiconductor
ML2110
When DS bit = 1
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
Symbol
AS Pulse Width
Note 3
tW_AS
A to AS Time
tW_AAS
RD Pulse Width
A to RD Time
WR Pulse Width
A to WR Time
D to WR Time
tW_RD
tW_ARD
tW_WR
tW_AWR
tW_DWR
Condition
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
4τ to 7τ Access
(X bit = 0)
8τ to 14τ Access
(X bit = 1)
Min.
Typ.
Max.
Unit
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
2
—
tCYC
—
3
—
tCYC
—
1
—
tCYC
—
2
—
tCYC
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ML2110
Serial Interface
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
tRTS
tW_RXD
tS_RXD
tH_RXD
tS_CTS
tH_CTS
tTXD
tW_TXD
tDTR
tSCLK
tW_SCLK
—
—
—
—
—
—
—
—
—
—
—
—
1/bps
0.5/bps
0.5/bps
0
0
—
1/bps
—
—
1/bps
—
—
—
—
—
—
—
—
—
—
—
22
—
—
—
—
—
21
—
23
20
—
ns
s
s
s
ns
ns
ns
s
ns
ns
s
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
PACK to PD Delay Time
PACK to PD Hi Z Delay
Time
PCS Setup Time for
PSTB/PACK
PCS Hold Time for
PSTB/PACK
PIOA Setup Time for
PSTB/PACK
PIOA Hold Time for
PSTB/PACK
Required PACK Time
Required PSTB Time
PD Setup Time for
PSTB
PD Hold Time for PSTB
tPACK
—
—
—
22
ns
tPRDZ
—
—
—
22
ns
tS_PCS
—
0
—
—
ns
tH_PCS
—
0
—
—
ns
tS_PIOA
—
0
—
—
ns
tH_PIOA
—
3
—
—
ns
tW_PACK
tW_PSTB
—
—
30+tCYC
30+2tCYC
—
—
—
—
ns
ns
tS_PD
—
–tCYC
—
—
ns
tH_PD
—
8
—
—
ns
Condition
Min.
RTS Delay Time
Required RXD Time
RXD Setup Time
RXD Hold Time
CTS Setup Time
CTS Hold Time
TXD Delay Time
TXD Pulse Width
DTR Delay Time
SCLK Delay Time
SCLK Pulse Width
Parallel Interface
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Digital Signal Output Interface
(VDD = 3.0 to 3.6 V, Ta = –40 to 85°C)
Parameter
Symbol
Typ.
Max.
Synchronous Clock
tBCYC
—
100
—
—
Cycle
Synchronous Clock
tWSYNC
—
1BCYC
—
—
Width
BCLK to XSYNC Time
tBCKXS
—
0
—
25
DOUT Delay Time
tDOUT
—
—
—
25
Note 1 According to DRAM configuration
Note 2 Depending the DRAM access timing
Note 3 In case of writing, increased by 1 clock when X bit = 0 and by 2 clocks when X bit = 1.
Note 4 Flash memory access timing is the same with the SRAM timing.
Unit
ns
ns
ns
ns
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ML2110
TIMING DIAGRAM
Clock and Reset
tW_CLKL tW_CLKH
tOSC
CLK
tXO
XO
tCYC
tCLKA
CLKA
RST
tW_RST
Note: tOSC = 1/fOSC
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ML2110
ROM Read
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_ROM
tROM
ROM
tROM
tRD
RD
tW_RD
tRD
3τ/4τ Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
ROM
RD
tW_ROM
tROM
tROM
tRD
tW_RD
tRD
5τ/6τ/7τ/8τ/10τ/12τ Access
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ML2110
SRAM Read
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_SRAM
tSRAM
SRAM
tSRAM
tRD
RD
tRD
tW_RD
3τ/4τ Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
SRAM
RD
tW_SRAM
tSRAM
tSRAM
tRD
tW_RD
tRD
5τ/6τ/7τ/8τ/10τ/12τ Access
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ML2110
SRAM Write
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AWR
tW_SRAM
tSRAM
tSRAM
SRAM
tWR
WR
TW_WRSRAM
tWR
tW_WR
3τ Access
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AWR
SRAM
WR
tW_WRD
tW_SRAM
tSRAM
tSRAM
tWR
tWR
tW_WRSRAM
tW_WR
4τ/5τ/6τ/7τ/8τ/10τ/12τ Access
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ML2110
DRAM Read
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tH_D
tS_D
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tW_ACAS
RAS
tRAS
tCAS
CAS
tCAS
tW_CAS
tW_RASCAS
WE
2nτ Access
tOSC
CLK
CLKA
tA
tA
A
D
RAS
CAS
row address
column address
tS_D
tW_ARAS
column address
tS_D
tH_D
tW_PREC
tW_RAS
tRAS
tW_ACAS
tRAS
tCAS
tW_CAS
tH_D
tCAS
tCAS
tW_RASCAS
WE
2nτ Access (Fast Page Mode)
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ML2110
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tH_D
tS_D
D
tW_ARAS
tW_RAS
tW_ACAS
RAS
tW_PREC
tRAS
tW_CAS
tRAS
tCAS
tCAS
CAS
tW_RASCAS
WE
3nτ Access
tOSC
CLK
CLKA
tA
tA
A
row address
column address
column address
tS_D
D
RAS
tW_ARAS
tS_D
tH_D
tH_D
tW_RAS
tRAS
tW_ACAS
tCAS
CAS
tW_PREC
tW_CAS
tW_CAS
tCAS
tCAS
tRAS
tCAS
tW_RASCAS
WE
3nτ Access (Fast Page Mode)
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DRAM Write
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tH_D
tD
D
tW_ARAS
tW_RAS
tW_ACAS
RAS
tW_PREC
tRAS
tRAS
tW_CAS
tCAS
CAS
tW_RASCAS
tW_AWE
WE
tCAS
tWE
tW_WE
tWE
2nτ Access
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tD
D
tW_ARAS
RAS
tD
tW_ACAS
tCAS
tW_AWE
tW_PREC
tW_RAS
tRAS
CAS
WE
column address
tD
tW_CAS
tW_RASCAS
tWE
tRAS
tCAS
tW_WE
tCAS
tW_CAS
tWE
2nτ Access (Fast Page Mode)
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tOSC
CLK
CLKA
tA
tA
column address
row address
A
tH_D
tD
D
tW_ARAS
tW_RAS
tW_ACAS
RAS
tRAS
tW_RASCAS
CAS
tW_PREC
tRAS
tW_CAS
tCAS
tCAS
tW_WECAS
tW_AWE
WE
tWE
tW_WE
tWE
3nτ Access
tOSC
CLK
CLKA
tA
row address
A
column address
column address
tD
tD
tD
D
RAS
tRAS
tW_ACAS
tW_RASCAS
CAS
tW_CAS
tW_AWE
WE
tW_PREC
tW_RAS
tW_ARAS
tWE
tW_CAS
tCAS
tW_CAS
tCAS
tW_WE
tCAS
tRAS
tCAS
tWE
3nτ Access (Fast Page Mode)
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DRAM Refresh
tOSC
CLK
CLKA
ignore
A
ignore
D
tW_RAS
tRAS
RAS
tCAS
CAS
tRAS
tW_CASRAS
tW_CAS
tCAS
WE
2nτ CAS-Before-RAS Refresh
tOSC
CLK
CLKA
ignore
A
ignore
D
tRAS
RAS
CAS
tCAS
tW_RAS
tRAS
tW_CASRAS
tW_CAS
tCAS
WE
3nτ CAS-Before-RAS Refresh
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tOSC
CLK
CLKA
ignore
A
ignore
D
tRAS
RAS
CAS
tCAS
tW_RAS
tRAS
tW_CASRAS
tW_CAS
tCAS
WE
CAS-Before-RAS Self-Refresh
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General Device Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
D
tW_AS
tW_AAS
tAS
tAS
AS
tW_ARD
RD
tRD
tW_RD
tRD
tW_AAS
Bus Read
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AAS
AS
WR
tW_AAS
tW_AS
tAS
tAS
tW_AWR
tWR
tW_WR
tWR
Bus Write (When DS bit in The SCR register is “0”)
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CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AS
tW_AAS
tW_AAS
tAS
AS
tAS
tW_AWR
WR
tW_DWR
tW_WR
tWR
tWR
Bus Write (When DS bit is “1” and X bit is “0”in the SCR register)
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AS
tW_AAS
AS
WR
tW_AAS
tAS
tAS
tW_AWR
tW_DWR
tWR
tW_WR
tWR
Bus Write (When DS bit is “1” and X bit is “1” in the SCR register)
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Parallel Interface
tOSC
CLK
tCLKA
CLKA
tS_PCS
tH_PCS
tS_PCS
tS_PCS
tH_PCS
tH_PCS
PCS
tS_PIOA
PIOA
tS_PIOA
tH_PIOA
tH_PIOA
tW_PACK
tW_PACK
PACK
tS_PIOA
tH_PIOA
tW_PSTB
PSTB
tPACK
tPRDZ
tS_PD
tH_PD
PD
tPACK
tPRDZ
PIBF
tPACK
tPRDZ
POBF
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Serial Interface
tOSC
CLK
tCLKA
CLKA
tS_RXD tH_RXD tS_RXD t
H_RXD
RXD
Start_bit(=0)
bit 0
tW_RXD
tW_RXD
tRTS
RTS
tS_RXD tH_RXD t
bit 1
bit 6
bit 7
tW_RXD
S_RXD tH_RXD
Stop_bit(=1)
tRTS
tW_RXD
tOSC
CLK
tCLKA
CLKA
tTXD
RXD
Start_bit(=0)
tS_CTS
RTS
tH_CTS
tW_TXD
tTXD
tTXD
bit 0
tW_TXD
bit 1
tTXD
tTXD
bit 6
bit 7
tW_TXD
tTXD
Stop_bit(=1)
tW_TXD
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CLK
tCLKA
CLKA
tSCLK
SCLK
tW_SCLK
tW_SCLK
tSCLK
tSCLK
Synchronous Transfer Output
General Port Output
CLK
tCLKA
CLKA
tUPORT
tUPORT
UPORT
General Port Output
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Digital Signal Output
tBCYC
BCLK
tBCKXS
XSYNC
tWSYNC
tDOUT
tDOUT
DOUT
MSD
D2
D15
* BCLK and XSYNC must be synthesized.
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Standby Operation
CLK
XO
CLKA
tW_RST
RST*
tRSTSTBY_H
tRSTSTBY_S
STBY
tSTBYCLKA
CPU Operation
Operating
Suspend
Suspend
Process
Operating
Resume
Process
RAS
CAS
Maintain the pin level on the STBY signal until the CPU has completed its suspend process and clock
Signal CLKA has stopped.
After the STBY signal is released, the CPU will not resume until oscillation has stabilized (1024tCYC).
* The RST signal is not necessary for self-refresh DRAM.
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Interrupt Process
CLK
XO
CLKA
EXTINT
The external interrupt signal EXTINT requests an interrupt to the CPU. The pin level on EXTINT
must be maintained until the CPU accepts the interrupt. Also, be sure to clear the interrupt source
within the interrupt routine.
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FUNCTIONAL DESCRIPTION
CPU Core
1. Features
The SCP (Speech Control Processor) uses a CPU core with an Oki-original 32-bit RISC architecture.
2. Register Configuration
The CPU core registers are configured as 32 words for general registers, 7 words for privileged
registers, and 1 word for a special register.
Privileged Registers
General Register
%r0 (link)
%PSR
%r1 (pre-PC)
%VBA
%r2 (pre-nPC)
%prPSR
%r3 (long-immed.)
%IRR
%r4
%BPA
%r5
%PC
%nPC
Special Register
%r30
%NOP
%r31
2.1 General Registers
The general registers are a set of 32 registers with 32-bit width. Of these registers %r0 to %r3 can be
used as general registers, but they do have special functions pre-assigned by the system. Registers
%r4 to %r31 can be used freely. Contents are undefined after reset.
bit 31
0
GR
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%r0:
ML2110
%r1:
Link register (stores subroutine return address). Also stores %PC+4 during bl instruction
execution.
Stores value of %PC when an exception, interrupt, or trap is accepted.
%r2:
Stores value of %nPC when an exception, interrupt, or trap is accepted.
%r3:
Stores the immediate value of SETLI (Set Long Immediate) instructions.
2.2 Privileged Registers
Reads are allowed at any processor level (PL:Processor Level: 0 = user mode, 1 or above = supervisor
mode), but write accesses are allowed only when the processor level is supervisor mode. The
privileged registers are configured as 7 words, and are used primarily for processor control. If the
processor attempts a write access to a privileged register while in user mode, then the instruction will
not be executed and a privileged instruction exception will be issued.
2.2.1 PSR (Processor Status Register)
This register sets and displays the state of the processor.
bit 31
28 27 26 25 24 23 22 21 20 19 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3
VER
M M
I I N
E E
0 0 0 0 0 F F 0 0 0 0 0 V C N Z 0 C C O 0 0 B M
U U
P L P
P
32 16
0
PL
• bit[31:28] VER: Version (read-only)
Indicates the CPU core version. Currently fixed to "3".
• bit[22] MFU32 (read-only)
Indicates whether the32-bit multiplier unit is present ("1")or not("0"). This is "0"for theML2110.
• bit[21] MFU16 (read-only)
Indicates whether the16-bit multiplier unit is present ("1")or not("0"). This is "1"for theML2110.
• bit[15] V: Overflow (read-only)
Indicates that execution of an addition or subtraction instruction resulted in an arithmetic
overflow.
• bit[14] C: Carry (read-only)
Indicates that execution of an addition or subtraction instruction resulted in an arithmetic carry or
borrow.
• bit[13] N: Negative (read-only)
Indicates that execution of an addition or subtraction instruction resulted in a negative value
(bit[31] is "1").
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• bit[12] Z: Zero (read-only)
Indicates that execution of an addition or subtraction instruction resulted in a zero value (bit[31:0]
are all "0").
• bit[10] ICP: Instruction Cache Purge (read/write)
Invalidates all instruction cache entries. Writing "1" to this bit purges the contents of the instruction
cache. After this process (after one cycle) this bit is automatically cleared to "0" by hardware. The
instruction cache is purged during reset.
• bit[9] ICL: Instruction Cache Lock (read/write)
Freezes all instruction cache entries. After "1" is written to this bit, instruction cache contents are
frozen and then instruction execution continues. This bit will be "1" after reset.
• bit[8] NOP: Non-Operation (read-only)
When set to "1", forces the next instruction to a NOP regardless of the instruction. There is no way
to directly set this bit to "1". This bit will be "0" after reset.
• bit [5] EBP: Breakpoint Trap Enable (read/write)
Enables breaks. If this bit is set to "1", then a trap will occur when the value of the instruction
execution address (%PC) equals the value of the breakpoint address (%BPA). The instruction that
generated the break will not be executed. This bit will be "0" after reset.
• bit[4] EM: Master Enable (read/write)
Disables all exceptions, interrupts, and traps. This bit automatically becomes "0" at the point when
the processor accepts an exception, interrupt, or trap. While this bit is "0", further exceptions,
interrupts or traps will not be accepted, with instruction execution continuing in the normal
instruction sequence. An instruction must be used to return this bit to "1". It will be "0" after reset.
• bit[3:0] PL: Processor Level (read/write)
Sets and provides the processor’s instruction execution level. Processor levels are 0-15. An external
interrupt will be accepted if its level has a higher priority than the processor level at that time.
External interrupt levels are 1-16, so when PL is 0 all external interrupts will be accepted, and when
PL is 1 external interrupts of level 2 and above will be accepted. When an external interrupt is
accepted, the processor level will become the same as the external interrupt level. For example, if
PL is 5 and a level 7 external interrupt is accepted, then PL will transition to 7 at that point. When
PL is restored to its previous state, its saved value in %prPSR will be restored to %PSR.
Alternatively PL can be set to its previous value explicitly by an instruction in the interrupt process
routine. However, %PSR is a privileged register, so writes are only permitted in supervisor mode.
PL will be set to 15 after reset.
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2.2.2 VBA: Vector Base Address (read/write)
This read/write register sets the leading address of the dispatch table (vector table) to exception,
interrupt, and trap process routines.
bit 31
1211
VBA
0
0 0 0 0 0 0 0 0 0 0 0 0
The dispatch table is 256 entries of 4K bytes size, with 16 bytes (4 instructions) save for each entry’s
dispatch routine. Entry points are generated by an OR operation with this register, so they are set
at4K-byte boundaries. As a result, only the upper20bitsof an argument will be written to the VBA
register (the lower 12 bits will be ignored).
Entry_point = VBA[31:12] ||(vector_number << 4)
This register is undefined after reset.
2.2.3 prPSR: Pre-Processor Status Register (read/write)
This read/write register saves the value of %PSR at the time an exception, interrupt, or trap is
accepted. In order to accept overlapping exceptions, interrupts, and traps, the valueof %prPSR must
be pushed on a stack and then EM of %PSR must be set to "1".
28 27 26 25 24 23 22 21 20 19 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3
bit 31
VER
p
M M
p p p p
I
F
F
0 C
0 0 0 0 0
0 0 0 0 0
V C N Z
U U
P
32 16
p
I
C
L
p
p
N
E p
O 0 0 B E
P
P M
0
pPL
The upper 16 bits of %prPSR are always identical to %PSR. Refer to the descriptions of the same bit
positions in %PSR for an explanation of %prPSR bits.
2.2.4 IRR: Interrupt Request Register (read-only)
This register indicates whether there is an interrupt request at each of the 16 levels of external
interrupts. It is read-only, and shows interrupt requests regardless of PL(processor level). The IRR
value will continue until an interrupt source is released.
bit 31
16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0
N I I I I I I
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M R R R R R R
Q Q Q Q Q Q
I 15 14 13 12 11 10
I
R
Q
9
I
R
Q
8
I
R
Q
7
I
R
Q
6
I
R
Q
5
I
R
Q
4
I
R
Q
3
I
R
Q
2
I
R
Q
1
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The ML2110 uses only 7 interrupts of the 16 interrupt levels.
bit 31
16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0
I
I
I
I
I
I
I
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0 Q 0 R 0 R 0 R 0 R 0 R 0 0
Q
Q
Q
Q
Q
Q
9
7
5
3
15 13 11
2.2.5 BPA: Breakpoint Address (read/write)
This read/write register sets and shows the instruction address (byte address) where a breakpoint
Trap occurred. The lowest 2 bits will alwaysbe"0". When EBP of %PSRis"1",a trap will be generated
immediately before execution of the instruction at the breakpoint set by this register. This register
will be undefined after reset.
2 1 0
bit 31
BPA
0 0
2.2.6 PC: Program Counter (read-only)
This read-only register provides the instruction address (byte address) in the execution phase. Its
lowest 2 bits will always be "0".
bit 31
2 1 0
PC
0 0
2.2.7 nPC: Next Program Counter (read-only)
This read-only register provides the instruction address(byte address) in the instruction decode
phase. Its lowest 2 bits will always be "0".
2 1 0
bit 31
nPC
0 0
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2.3 Special Registers
These are not privileged registers, but they are special registers used for specific functions.
2.3.1 NOP: Non-Operation (read/write)
When this register is specified as a destination register, execution results will not be stored anywhere.
When specified as a source register, it will read as an undefined value.
bit 31
0
NOP
3. Data Formats
There are two data format types: one for internal processor core calculations and one for memory
accesses.
3.1 Internal Data Format
The CPU core handles all data as 32 bits (word format). Therefore, when the format of data stored
in memory is byte (8 bits) or half-word (16 bits) it must be used internally as 32-bit data through a
signed load instruction or unsigned load instruction. Similarly when internal core processing results
are stored to memory, a store instruction corresponding to the data format in memory must be
executed. Also, bit addresses specified for bit test instructions and bit manipulation instructions are
shown in the diagram below.
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0
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3.2 Memory Data Format
The following memory data formats are supported: byte (8 bits), half-word (16 bits), and word (32
bits). Memory addresses are always byte addresses regardless of data format. However, half-word
accesses must be on 16-bit boundaries (least significant bit is "0"), and word accesses must be on 32bit boundaries (least significant 2 bits are "00"). If a load or store instruction execution attempts a
memory access that violates these boundaries, then a data address invalid exception will occur.
Memory addressing is big-endian. The diagrams below show memory data formats for byte data
access, half-word data access, and word data access.
Byte Data Access
Address
16 15
24 23
bit 31
8 7
0
byte
byte
byte
byte
n
n+1
n+2
n+3
Half-Word Data Access
bit 31
Address
16 15
0
half word
half word
n
n+1
Word Data Access
0
bit 31
word
Address
n
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3.3 Memory Addressing Modes
Memory addresses are byte addresses, so memory addressing is performed with three types of load
instructions and two types of store instructions. Swap instructions have the same memory
addressing as store instructions.
3.3.1 Load Instruction Addressing
Base + Index
The effective address (EA) is obtained by adding the values of any two general registers %r0-31
specified.
EA = [reg_S1 + reg_S2]
Base + Displacement
The effective address (EA) is obtained by adding the value of any general register %r0-31 specified
and a displacement given by the instruction’s immediate value field.
EA = [reg_S1] + offS
3.3.2 Store Instruction Addressing
Base + Displacement
The effective address (EA) is obtained by adding the value of any general register %r0-31 specified
and a displacement given by the instruction’s immediate value field.
EA = [reg_S1] + offS
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4. Instruction Set
All instructions are fixed 32-bit length
Category
Unconditional branch
Conditional branch
Bit test
Comparison
Trap
Arithmetic/logical
operation
Extend
Shift
Bit manipulation
Instruction
b{,x}?
bl{,x}?
bt{,x/t} S1,?
bf{,x/t} S1,?
jlr {,x} S2,D*
jlrt {,x/t} S1,S2,D*
jlrt {,x/t}S1,S2,D*
rt S2
btst1 S1,S2/immU,D
btst0 S1,S2/immU,D
cmpeq S1,S2/immU,D
cmple S1,S2/immU,D
cmplt S1,S2/immU,D
cmpls S1,S2/immU,D
cmpc S1,S2/immU,D
cmpne S1,S2/immU,D
cmpgt S1,S2/immU,D
cmpge S1,S2/immU,D
cmphi S1,S2/immU,D
cmpnc S1,S2/immU,D
trap vct
add S1,S2/immS9,D
sub S1,S2/immS9,D
adc S1,S2/immS9,D
sbc S1,S2/immS9,D
and S1,S2/immS9,D
or S1,S2/immS9,D
xor S1,S2/immS9,D
sbr S1,S2/immS12,D
extu S1,S2/immU,D
ext S1,S2/immU,D
sl S1,S2/immS,D
rot S1,S2/immS,D
slr S1,S2/immS,D
sar S1,S2/immS,D
brst S1,S2/immU,D
bset S1,S2/immU,D
bnot S1,S2/immU,D
brst %psr,4/5,%psr
brst %psr,4/5,%psr
Function
Unconditional branch
Unconditional branch subroutine
Conditional branch
Conditional branch
Conditional branch to subroutine
Conditional branch to subroutine
Conditional branch to subroutine
Return from subroutine
Bit test
Bit test
Comparison [=]
Comparison [signet: ≤]
Comparison [signet: <]
Comparison [unsigned: ≤]
Comparison [unsigned: <]
Comparison [≠]
Comparison [signed: >]
Comparison [signed: ≥]
Comparison [unsigned: >]
Comparison [unsigned: ≥]
Transfer to trap routine
Add
Subtract
Add with carry
Subtract with carry
Logical AND
Logical OR
Exclusive OR
Subtract
MSB extend
MSB extend
Logical shift
Logical rotate
Logical shift
Arithmetic shift
Set bit to “0”
Set bit to “1”
Invert bit
Set bit to “0”
Set bit to “1”
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Category
Register-register move
Store immediate value
Store
Swap
Load
Multiplication
ML2110
Instruction
mov S,D
movh S1,D’
seti imm17S,D
setih const16.D’
setli const25
sb S2/immS,[S1+offS]
shw S2/immS,[S1+offS]
sw S2/immS,[S1+offS]
swap S2,[S1+offS]
lb [S1+offS].D’
lhw [S1+offS].D’
lw [S1+offS].D’
mul0 S1,S2/immS,D’
Mul16 S1,S2/immS,D’
Mul32 S1,S2/immS,D’
mulu0 S1,S2/immS,D’
Mulu16 S1,S2/immS,D’
Mulu32 S1,S2/immS,D’
Function
Move
Move upper bits
Store immediate value
Store immediate value to upper 16 bits.
Store immediate value left-shifted 7 bitsto %r3
Byte store
Half-word store
Word store
Swap
Bye load
Half-word load
Word load
Signed multiply
Signed multiply
Signed multiply
Unsigned multiply
Unsigned multiply
Unsigned multiply
Multiply instructions need two clocks for execution time.
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5. Exceptions, Traps, and Interrupts
The CPU core of SCP provides error exceptions, traps, external interrupts, and software traps (by
trap instructions). Each type has a corresponding interrupt priority level and instruction dispatch
address.
Source
System reset
CPU reset (INIT)
Instruction access exception
Instruction
address
invalid
exception
Reserved instruction exception
Privileged instruction exception
Data address invalid exception
Data access exception
Reserved
Breakpoint trap
Reserved
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
External interrupt 8
External interrupt 9
External interrupt 10
External interrupt 11
External interrupt 12
External interrupt 13
External interrupt 14
External interrupt 15
External interrupt 16 (NMI)
TRAP instruction
Vector
number
Branch address
Priority
0
1
0x00000000
VBA+0x000
VBA+0x010
0
1
2
Synchronous/asynchronous
(Sense)
Asynchronous (level)
Asynchronous (edge)
Synchronous
2
VBA+0x020
3
Synchronous
3
4
5
6
7
8
VBA+0x030
VBA+0x040
VBA+0x050
VBA+0x060
VBA+0x070
VBA+0x080
VBA+0x090
to VBA+0x200
VBA+0x210
VBA+0x220
VBA+0x230
VBA+0x240
VBA+0x250
VBA+0x260
VBA+0x270
VBA+0x280
VBA+0x290
VBA+0x2a0
VBA+0x2b0
VBA+0x2c0
VBA+0x2d0
VBA+0x2e0
VBA+0x2f0
VBA+0x300
VBA+0x000
to VBA+0xff0
4
5
8
9
Synchronous
Synchronous
Asynchronous (edge)
Asynchronous (edge)
6
Synchronous
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
Asynchronous (level)
7
Synchronous
9 to 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
0 to 255
The system reset vector is at absolute address 0. All others are ORed with VBA as the base address.
Synchronous detection is acceptance of a request within an instruction cycle.
Asynchronous detection is acceptance of a request between instruction cycles or at any point in time
after.
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5.1 RST: System Reset
A system reset resets all states under all circumstances.
Type: Asynchronous hardware reset after RST pin level detection.
Vector address: Absolute address 0 (0x00000000).
Conditions: Non-maskable (unconditional)
PL after interrupt transition: 15
5.2 IAE: Instruction Access Exception
An instruction access exception is generated when an instruction is fetched from an undefined
memory space. If the instruction is converted to a NOP by delayed instruction control (x-bit
manipulation), then no exception will be generated.
Type: Instruction-synchronous exception caused by memory access error during instruction fetch.
Vector number/address: Vector number = 1 / VBA+0x010
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
5.3 IAIE: Instruction Address Invalid Exception
An instruction address invalid exception is generated when a register indirect branch instruction
attempts an instruction fetch at an address that is not on a word boundary. If the instruction is
converted to a NOP by delayed instruction control (x-bit manipulation), then no exception will be
generated.
Type: Instruction-synchronous exception caused by an illegal JLR or RT instruction.
Vector number/address: Vector number = 2 / VBA+0x020
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
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5.4 PIE: Privileged Instruction Exception
A privileged instruction exception is generated when an action that can only be performed in
supervisor mode attempted in user mode: (a) in user mode a privileged register is specified as a
destination, or (b) in user mode a number 64 or below is specified for a TRAP instruction vector. If
the instruction is converted to a NOP by delayed instruction control (x-bit manipulation), then no
exception will be generated.
Type: Instruction-synchronous exception caused by an illegal privileged instruction.
Vector number/address: Vector number = 4 / VBA+0x040
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
5.5 DAIE: Data Address Invalid Exception
A data address invalid exception is generated when a memory access instruction attempts to access
a memory address not on a word boundary.
Type: Asynchronous exception caused by an illegal memory access instruction.
Vector number/address: Vector number = 5 / VBA+0x050
Conditions: EM == 1. However, exception must be maintained until accepted.
Saved address: Address being executed when the exception was accepted.
PL after interrupt transition: 15
5.6 DAE: Data Access Exception
A data access exception is generated when data is accessed in an undefined memory space.
Type: A synchronous exception caused by a memory access instruction error.
Vector number/address: Vector number = 6 / VBA+0x060
Conditions: EM == 1. However, exception must be maintained until accepted.
Saved address: Address being executed when the exception was accepted.
PL after interrupt transition: 15
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5.7 BPT: Breakpoint Trap
A breakpoint trap is generated when the instruction execution address matches the address pointed
to by the %BPA register. However, the EBP bit in the %PSR register must be enabled. The instruction
at the address that causes the trap will not be executed. The trap will be generated even if the
instruction is converted to a NOP by delayed instruction control (x-bit manipulation).
Type: Instruction-synchronous trap caused by hardware.
Vector number/address: Vector number = 8 / VBA+0x080
Conditions: EM == 1 && EBP == 1. Not invalidated by delayed instruction control (x-bit).
Saved address: Address pointed to by the %BPA register.
PL after interrupt transition: 15
5.8 EINT: External Interrupt 1-15
External interrupts are generated by inputs. However, an external interrupt will be accepted only
when its level has higher priority than the current processor level. When an external interrupt is
accepted, the processor level becomes the same as its level.
Type: A synchronous interrupt when level on INT1-INT15 pins is detected.
Vector number/address: Vector number = 33-47 / VBA+0x210-0x2f0
Conditions: EM == 1 && PL < external_interrupt_number
Saved address: Address being executed when the interrupt was accepted.
PL after interrupt transition: External interrupt number
The ML2110 assigns interrupt levels as follows. It does not use other interrupts (including NMI).
Interrupt Source
EXTINT1
D/A Converter
DOUT
EXTINT0
Serial I/O
Parallel I/O
TMR1
Priority
Interrupt Number
1
2
3
4
5
6
7
INT15
INT13
INT11
INT9
INT7
INT5
INT3
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5.9 Return From Interrupt
In order to return from an interrupt process caused by an exception, external interrupt, or software
trap, the pipeline at the time of the interrupt must be regenerated before execution.
There are two types of returns: (1) re-execution of an instruction that was in its execution phase at
the time an exception, external interrupt, or asynchronous trap caused an interrupt, and (2) reexecution of the instruction after the instruction that was in its execution phase at the time a software
trap caused an interrupt. However, if breakpoints are supported by software traps then case (1)
applies.
The return sequence from an interface process is described below.
Also, an rt instruction must not be executed while the EM bit of %PSR is 1 (the state permitting
overlapping interrupts). If an interrupt occurred during the rt instruction in such a case, then the
contents of %PSR would be corrupted.
1. Resume from interrupted instruction
brst
jlr
rt
%psr, 4, %psr
; EM-bit reset
%r1, %nop
; delay slot, branch %r1 (old %PC),
; return address not saved
%r2
; return to %r2 (old %nPC), %prPSR move to %PSR
2. Return from instruction after interrupt
add
brst
jlr
rt
%r2, 4, %r1
; %r2+4 (old %nPC+4)®%r1
%psr, 4, %psr
; EM-bit reset
%r2, %nop
; delay slot, branch %r2 (old %nPC), return address not saved
%r1
; return to %r1 (old %nPC+4), %prPSR move to %PSR
In this case the pNOP bit of %prPSR must be cleared in advance of rt instruction execution. If the
pNOP bit of %prPSR is set and then the rt instruction is executed, then the instruction at the return
point would not be executed.
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Bus Interface Unit
1. Features
The SCP’s bus interface unit (BIU) manages address space and outputs control signals that enable
optimal memory access. This allows ROM, SRAM, DRAM and other general devices to be accessed.
2. Address Space
The address space that can be directly accessed by load/store instructions is 4 gigabytes. The BIU
manages this address space by dividing it into several.
0x00000000
ROM
256MB
SRAM
256MB
DRAM
256MB
0x0FFFFFFF
0x10000000
0x1FFFFFFF
0x20000000
External
0x2FFFFFFF
0x30000000
Reserved
0x3FFFFFFF
0x40000000
General devices
1GB
4GB
0x7FFFFFFF
0x80000000
Reserved
0xBFFFFFFF
0xC0000000
Internal ROM
256MB
0xCFFFFFFF
0xD0000000
Internal
Internal RAM
256MB
Registers
512MB
0xDFFFFFFF
0xE0000000
0xFFFFFFFF
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2.1 ROM Space
ROM space is assigned to 0x00000000-0x0FFFFFFF. When this space is accessed the ROM signal goes
"L".
2.2 SRAM Space
SRAM space is assigned to 0x10000000-0x1FFFFFFF. When this space is accessed the SRAM signal
goes "L".
2.3 DRAM Space
DRAM space is assigned to 0x20000000-0x2FFFFFFF. When this space is accessed the DRAM
controller outputs a signal required for DRAM access.
2.4 General Device Space
General device space is assigned to 0x40000000-0x7FFFFFFF. When this space is accessed the AS
signal goes "L". This space is used to access general devices external to the ML2110.
2.5 Internal ROM Space
Internal ROM space is assigned to 0xC0000000-0xCFFFFFFF. It is used to access internal ROM.
This space is not used by the ML2110. Accesses to this space will cause instruction access
exceptions or data access exceptions.
2.6 Internal RAM Space
Internal RAM space is assigned to 0xD0000000-0xDFFFFFFF. It is used to access internal RAM.
This space is not used by the ML2110. Access to this will cause instruction access exceptions or data
access exceptions.
2.7 Register Space
Register space is assigned to 0xE0000000-0xFFFFFFFF. Within this space, 0xF8000000-0xFFFFFFFF
is assigned for standard I/O and system registers.
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0xF8000000
0xF8FFFFFF
0xF9000000
0xF9FFFFFF
0xFA000000
0xFAFFFFFF
0xFB000000
0xFBFFFFFF
0xFC000000
0xFCFFFFFF
0xFD000000
0xFDFFFFFF
0xFE000000
0xFEFFFFFF
0xFF000000
ML2110
TMR
BSR
BEA
ECR
SCR
SIO
PIO
0xFF000000
0xFF000004
0xFF000008
0xFF00000C
0xFF000010
0xFF000014
0xFF000018
0xFF00001C
0xFF000020
0xFF00003F
0xFFFFFFFF
0xFF000040
0xFF00005F
System Registers
0xFF000080
Test Circuit
0xFF0000FF
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3.Registers
This is a register group used for bus control.
3.1 BEA: Bus Error Address
This register provides the address at the time a bus error occurred.
bit 31
0
BEA
3.2 BSR: Bus Status Register
This register provides bus status information.
bit 31
19 1817 16 15 14
C
XSP S 0
P
12 11
ST
8 7 6
PEB
0
4 3 2 1 0
BES
0 0 H R
• bit[18:17] XSP: Sleep (read/write)
When the STBY signal is "L", these bits either stop the clock without CPU intervention (XSP = 00)
or stop the clock after waiting for the CPU suspend process (XSP = 11).
• bit[16] CSP: CPU Sleep (read/write)
This bit indicates whether the CPU core is operating or suspended. Writing "1" will stop the CPU
core’s clock.
• bit[14:12] ST: Status (read-only)
These bits save the status signals when an access by the CPU core causes a bus error.
• bit[11:8] PEB: Parity Error Byte (read-only)
These bits provide the byte position when a parity error occurs.
• bit[6:4] BES: Bus Error Status (read-only)
These bits provide the source of a bus error.
BES = 000
BES = 001
BES = 010
BES = 100
No error
BIU register privilege violation
Parity error
Invalid space access
These bits will be "000" after reset.
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• bit[1] H: Hold (read/write)
This bit sets whether or not bus rights will be passed upon a CPU core bus rights request. This bit
will be "0" after reset.
3.3 ECR: Extra Configuration Register
This register sets bus operation.
bit 31
11 10 9 8 7 6
O A
P
X X 0 M
4 3 2 1 0
BM
O A D
A V V V
• bit[10] OX: Internal ROM (read-only)
This bit indicates whether or not internal ROM will be accessed in 2 clocks.
ML2110 does not use this bit.
• bit[9] AX: Internal RAM (read-only)
This bit indicates whether or not internal RAM will be accessed in 2 clocks.
ML2110 does not use this bit.
• bit[7] PM: Parity Mode (read/write)
This bit sets parity.
PM = 0
PM = 1
Even parity
Odd parity
This bit will be "0" after reset.
ML2110 does not use parity checking, so it ignores this field.
• bit[3] A: All Internal ROM (read/write)
This bit sets whether or not internal ROM will be accessed instead of external ROM.
ML2110 has no internal ROM, so this bit is always "0".
• bit[2] OV: Internal ROM Valid (read-only)
This bit shows whether internal ROM is enabled or disabled.
This bit is "0" for ML2110.
• bit[1] AV: Internal RAM Valid (read-only)
This bit shows whether internal RAM is enabled or disabled.
This bit is "1" for ML2110.
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3.4 SCR: Space Configuration Register
This register sets ROM space, SRAM space, and general device space.
bit 31
26 25 24 23
A A
C D
21 20
ARW
1817 16 15 14 13 12
O O
AWW AS 0 C D
10 9 8 7 6 5 4 3 2 1 0
D P S
ORW OS S C D X WT
SZ
• bit[25] AC: SRAM Parity Check (read/write)
This bit sets parity checking of SRAM space. It will be "0" after reset.
AC = 0
AC = 1
Ignore parity checks.
Generate a bus error if a parity error is detected.
• bit[24] AD: SRAM Dummy Cycle (read/write)
This bit sets whether or not SRAM space may be accessed continuously after ROM space or DRAM
space has been read.
AD = 0
AD = 1
Continuous access allowed.
Open an interval of at least one clock.
This bit will be "1" after reset.
• bit[23:21] ARW: SRAM Read Wait (read/write)
These bits set the wait count when SRAM space is accessed by a read.
ARW = 000 2t access (1 wait)
ARW = 001 3t access (2 waits)
ARW = 010 4t access (3 waits)
ARW = 011 5t access (4 waits)
ARW = 100 6t access (5 waits)
ARW = 101 8t access (7 waits)
ARW = 110 10t access (9 waits)
ARW = 111 12t access (11 waits)
These bits will be "111" after reset.
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• bit[20:18] AWW: SRAM Write Wait (read/write)
These bits set the wait count when SRAM space is accessed by a write.
AWW = 000 2t access (1 wait)
AWW = 001 3t access (2 waits)
AWW = 010 4t access (3 waits)
AWW = 011 5t access (4 waits)
AWW = 100 6t access (5 waits)
AWW = 101 8t access (7 waits)
AWW = 110 10t access (9 waits)
AWW = 111 12t access (11 waits)
These bits will be "111" after reset.
• bit[17:16] AS: SRAM Device Size (read/write)
These bits set the device size of SRAM space.
AS = 00
AS = 01
AS = 10
AS = 11
No SRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "00" after reset. When this field is "00", attempting to access SRAM space will
cause an instruction access exception or data access exception.
• bit[14] OC: ROM Parity Check (read/write)
This bit sets parity checking for ROM space. It will be "0" after reset.
OC = 0
OC = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the ML2110.
• bit[13] OD: ROM Dummy Cycle (read/write)
This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM
space read.
OD = 0
OD = 1
Consecutive access enabled.
Force an interval of at least one clock.
This bit will be "1" after reset.
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• bit[12:10] ORW: ROM Read Wait (read/write)
These bits set the wait count when ROM space is accessed by a read.
ORW = 000
ORW = 001
ORW = 010
ORW = 011
ORW = 100
ORW = 101
ORW = 110
ORW = 111
2t access (1 wait)
3t access (2 waits)
4t access (3 waits)
5t access (4 waits)
6t access (5 waits)
8t access (7 waits)
10t access (9 waits)
12t access (11 waits)
These bits will be "111" after reset.
• bit[9:8] OS: ROM Device Size (read/write)
These bits set the device size of ROM space.
OS = 00
OS = 01
OS = 10
OS = 11
No ROM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
When this field is "00", attempting to access ROM space will cause an instruction access exception
or data access exception.
• bit[7] DS: Other Data Setup (read/write)
This bit sets whether or not the data setup time to the write strobe signal WR is guaranteed during
writes to general device space.
DS = 0
DS = 1
Not guaranteed.
Guaranteed.
This bit will be "1" after reset.
• bit[6] PC: Other Parity Check (read/write)
This bit sets parity checking for general device space. It will be "0" after reset.
PC = 0
PC = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the ML2110.
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• bit[5] SD: Other Dummy Cycle (read/write)
This bit sets whether or not a general device space access will immediately follow an SRAM space
or DRAM space read.
SD = 0
SD = 1
Consecutive access enabled.
Force an interval of at least one clock.
This bit will be "1" after reset.
• bit[4] X: External Bus Clock Unit (read/write)
This bit sets the operating clock unit for general device space.
X=0
X=1
Use 1 clock as the unit.
Use 2 clocks as the unit.
This bit will be "0" after reset.
• bit[3:2] WT: Other Wait (read/write)
These bits set the wait count when general device space is accessed.
WT = 00
WT = 01
WT = 10
WT = 11
4t access
5t access
6t access
7t access
These bits will be "11" after reset.
• bit[1:0] SZ: Other Device Size (read/write)
These bits set the device size of general device space.
SZ = 00
SZ = 01
SZ = 10
SZ = 11
No general device (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "11" after reset. When this field is "00", attempting to access general device space
will cause an instruction access exception or data access exception.
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3.2 DRAM: DRAM Configuration Register
This register sets DRAM space.
bit 31
29 28 27 26 25 24 23 22 21 20
E
D
0 0 0 DT M TP P MD
1817 16 15
RA
CS
CA
0
13 1211 10 9
R
SZ F
M
REF
After this register has been written, DRAM must not be accessed until the DRAM is operating
properly. Refer to the data sheet of the DRAM used to obtain the required conditions for proper
DRAM operation.
• bit[28:27] DT: Device Type (read/write)
These bits set the DRAM device type.
DT = 00 Fast page mode
DT = 01 Hyper-page mode (EDO DRAM)
These bits will be "00" after reset.
• bit[26] PR: Parity Check (read/write)
This bit sets parity checking for DRAM space. It will be "0" after reset.
PR = 0
PR = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the ML2110.
• bit[25:24] TP: Type (read/write)
This bit sets the DRAM’s RAS signal and byte position control signal.
TP = 00
TP = 01
TP = 10
TP = 11
1 RAS mode, byte position CAS control
2 RAS mode, byte position CAS control
1 RAS mode, byte position WE control
2 RAS mode, byte position WE control
These bits will be "00" after reset.
• bit[23] DP: Data Priority (read/write)
This bit sets the priority of processing when data access is requested by a load/store instruction
during a one-line instruction cache read from DRAM due to an instruction cache miss.
DP = 0
DP = 1
Give priority to the instruction cache read from DRAM.
Give priority to the data access.
This bit will be "0" after reset.
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• bit[22:21] MD: Mode (read/write)
These bits set the number of clocks for a DRAM access.
MD = 01 2n clock access
MD = 10 3n clock access
These bits will be "10" after reset.
• bit[20:18] RA: Row Address (read/write)
These bits set the most significant bit position of the row address.
RA = 000 A17
RA = 001 A18
RA = 010 A19
RA = 011 A20
RA = 100 A21
RA = 101 A22
RA = 110 A23
These bits will be "000" after reset.
• bit[17:16] RS: Row Shift (read/write)
These bits set how many bits to shift the row address to output it as a DRAM address.
RS = 00
RS = 01
RS = 10
RS = 11
8-bit shift
9-bit shift
10-bit shift
11-bit shift
These bits will be "00" after reset.
• bit[15:13] CA: Column Address (read/write)
These bits set the most significant bit position of the column address.
CA = 000 A08
CA = 001 A09
CA = 010 A10
CA = 011 A11
CA = 100 A12
These bits will be "000" after reset.
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• bit[12:11] SZ: Device Size (read/write)
These bits set the device size of DRAM space.
SZ = 00
SZ = 01
SZ = 10
SZ = 11
No DRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "00" after reset. When this field is "00", attempting to access DRAM space will
cause an instruction access exception or data access exception.
• bit[10] RFM: Refresh Mode (read/write)
This bit sets the refresh operation mode.
RFM = 0 CAS-before-RAS refresh
RFM = 1 CAS-before-RAS self-refresh
This bit will be "0" after reset.
• bit[9:0] RFC: Refresh Counter (read/write)
These bits set the initial value of the refresh counter. It should be set as an integer value obtained
by:
[(refresh period) ÷ (clock period) ÷ 16] – 1
These bits will be "0000000000" after reset.
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4. ROM Access
The ML2110 interface with ROM is shown below.
Axx
Axx
ROM
ROM
CS
RD
OE
Dxx
Data
External Bus
ML2110
The ROM signal will become "0" when the address signal and specified ROM space match. Refer to
the timing diagram for basic timing of ROM accesses.
5. SRAM Access
The ML2110 interface with SRAM is shown below.
Axx
SRAM
Axx
SRAM
WE
CS
WE
RD
OE
Dxx
Data
ML2110
External Bus
The SRAM signal will become "0" when the address signal and specified SRAM space match. Refer
to the timing diagram for basic timing of SRAM accesses.
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6. DRAM Access
There are two ML2110 interfaces with DRAM: one when byte position is specified by CAS, and one
when byte position is specified by WE. This is set by the DRAM register’s TP field.
An interface example when byte position is specified by CAS is shown below.
Axx
RAS
CAS[0:3]
WE
Axx
RAS
CAS
DRAM
WE
Dxx
Data
External Bus
ML2110
An interface example when byte position is specified by WE is shown below.
Axx
Axx
RAS
RAS
DRAM
WE
CAS[0:3]
CAS
WE
Dxx
Data
ML2110
External Bus
Refer to the timing chart for basic timing of DRAM accesses.
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The table below shows how address signals are connected for different DRAM configurations.
Configuration
256Kx8
256Kx16
256Kx32
512Kx8
512Kx16
512Kx32
1Mx8
1Mx16
1Mx32
2Mx8
2Mx16
2Mx32
4Mx8
4Mx16
4Mx32
Row
17-09
18-10
18-09
19-11
19-10
18-09
19-10
20-11
19-10
20-11
20-10
20-09
21-12
21-11
21-10
20-10
20-09
21-11
21-10
22-12
22-11
21-11
21-10
22-12
22-11
23-13
23-12
Column
08-00
09-01
08-01
10-02
09-02
08-00
09-01
10-02
09-00
10-01
09-01
08-01
11-02
10-02
09-02
09-00
08-00
10-01
09-01
11-02
10-02
10-00
09-00
11-01
10-01
12-02
11-02
Address lines
A[08:00]
A[09:01]
A[09:01]
A[10:02]
A[11:02]
A[09:00]
A[10:01]
A[11:02]
A[09:00]
A[10:01]
A[11:01]
A[12:01]
A[11:02]
A[12:02]
A[13:02]
A[10:00]
A[11:00]
A[11:01]
A[12:01]
A[12:02]
A[13:02]
A[10:00]
A[11:00]
A[11:01]
A[12:01]
A[12:02]
A[13:02]
CA
000
001
000
010
001
000
001
010
001
010
001
000
011
010
001
001
000
010
001
011
010
010
001
011
010
100
011
RS
01
01
00
01
00
01
01
01
10
10
01
00
10
01
00
10
01
10
01
10
01
11
10
11
10
11
10
RA
000
001
001
010
010
001
010
011
010
011
011
011
100
100
100
011
011
100
100
101
101
100
100
101
101
110
110
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Serial Interface
1. Features
The serial interface (SIO) performs both clock synchronized and start-stop transfers.
2. SIO Functions
2.1 Port Configuration
• Independent transmit and receive circuits
• Double buffer configuration for receive buffer
Because the transmit and receive circuits are independent, start-stop transfers are all full-duplex
communication.
2.2 Transfer Methods
• Start-stop transfer
Data length:
Transfer sequence:
Stop bits:
Parity bit:
Flag bit:
7 bits or 8 bits selectable
LSB first
1 bit or 2 bits selectable
No parity, even parity, or odd parity selectable
Enables inter-processor communication using the serial port.
However, cannot be used together with parity bit.
• Clock synchronized transfer
Data length:
8 bits fixed
Transfer sequence: LSB first
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The chart below shows the data format with start-stop transfers.
7N1
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
1
7N2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
1
1
7F1
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Flag
1
7P1
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Parity
1
7F2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Flag
1
1
7P2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Parity
1
1
8N1(*)
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
1
8N2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
1
1
8F1
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Flag
1
8P1
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity
1
8F2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Flag
1
1
8P2
1
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity
1
1
Stop bits
Flag/parity
Data size
1: 1 Stop Bit, 2: 2 Stop Bits
N: Non, F: Flag, P: Parity
7: 7 Bits, 8: 8 Bits
(*)After reset the format will be 8 bits, no parity, 1 stop bit.
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2.3 Baud Rate
• Internal baud rate generator
• Clock synchronized transfers
B = f/(8 × n × (256 – P))
Where
B : baud rate (bps)
f : processor (SCP) clock frequency (Hz)
n : baud rate parameter
One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.
(Refer to the register description.)
P : baud rate adjustment value (0 ≤ P ≤ 255)
Set by SBR’s SBRV field. (Refer to the register description.)
At a processor (SCP) clock of 20 MHz, the maximum transfer rate is 2.5 Mbps. At 40 MHz, the maximum transfer
rate is 5 Mbps.
• Start-stop transfers
B = f/(16 × n × (256 – SBR))
Where
B : baud rate (bps)
f : processor (SCP) clock frequency (Hz)
n : baud rate parameter
One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.
(Refer to the register description.)
SBR : baud rate adjustment value (0 ≤ SBR ≤ 255)
Set by SBR’s SBRV field. (Refer to the register description.)
2.4 Error Detection
• Parity errors (start-stop transfers)
A parity error will be detected when a parity bit generated from received data does not match the received parity
bit.
• Framing errors (start-stop transfers)
A framing error will be detected when a received stop bit is "0". When 2 stop bits have been selected, only the first
bit received will be checked.
• Overrun errors (start-stop and clock synchronized transfers)
An overrun error will be detected when the next receive frame's stop bit is detected before the receive buffer has
been read.
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2.5 Interrupts
The SIO is the source of the following interrupts.
• Interrupts
- Receive error interrupt
A receive error interrupt will be generated whenever a parity error, framing error, or overrun error is detected.
- Receive buffer full interrupt
A receive buffer full interrupt will be generated whenever the valid receive data has been transferred to the
receive buffer.
- Transmit buffer empty interrupt
A transmit buffer empty interrupt will be generated whenever the transmit buffer becomes empty.
- Transmit end interrupt
A transmit end interrupt will be generated whenever an SIO data transfer ends.
- Modem status interrupt
A modem status interrupt will be generated whenever a change in a modem control input signal (CTS, DSR) is
detected.
• Interrupt enable/disable
Each interrupt source can be independently enabled or disabled. Also, all interrupts can be disabled at once.
• Interrupt requests
Whenever any of the five interrupts above is enabled and its conditions are fulfilled, the CPU will get an SIO
interrupt request.
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3. SIO Registers
These registers control SIO.
3.1 SIB: SIO Input Buffer
This register holds data that has been input externally. It is undefined after reset.
bit 7
0
SIB
3.2 SOB: SIO Output Buffer
This register holds data to be output externally. It is undefined after reset.
bit 7
0
SOB
3.3 SSTS: SIO Status Register
This register provides SIO status.
bit 15
11 10 9 8 7 6 5 4 3 2 1 0
S
O
0 0 0 0 0
V
E
S
F
R
E
S S
S
P 0 M O
S S
T
I T
E
S
I
S
T
S
E
R
I
S
R
X
I
S
T
X
I
S
T
E
I
• bit[10] SOVE
0 : No overrun error
1 : Overrun error generated
This bit can only be written with "0". It will be "0" after reset.
• bit[9] SFRE
0 : No framing error
1 : Framing error generated
This bit can only be written with "0". It will be "0" after reset.
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• bit[8] SPTE
0 : No parity error
1 : Parity error generated
This bit can only be written with "0". It will be "0" after reset.
• bit[6] SMSI
0 : No modem status interrupt
1 : Modem status interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[5] SOST
0 : Transmit buffer full
1 : Transmit buffer empty
This bit can only be written with "0". It will be "1" after reset.
• bit[4] SIST
0 : Receive buffer empty
1 : Receive buffer full
This bit can only be written with "0". It will be "0" after reset.
• bit[3] SERI
0 : No receive error interrupt
1 : Receive error interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[2] SRXI
0 : No receive buffer full interrupt
1 : Receive buffer full interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[1] STXI
0 : No transmit buffer empty interrupt
1 : Transmit buffer empty interrupt requested
This bit is read-only. It will be "0" after reset.
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• bit[0] STEI
0 : No transmit end interrupt
1 : Transmit end interrupt requested
This bit can only be written with "0". It will be "0" after reset.
3.4 SCMD: SIO Command Register
bit 15 14 13 12 11 10
S
S S
S S
E R
R T 0 I R X
E I I
E E
N E E
N N
9
S
T
X
I
E
8 7 6 5 4
S
S S S
T
F F
M
E 0
O B B
I
D M
E
3 2 1 0
S
F
L
S
P
T
Y
S
S
T
P
• bit[15] SREN
0 : Data receive disabled
1 : Data receive enabled
This bit will be "0" after reset.
• bit[14] STEN
0 : Data transmit disabled
1 : Data transmit enabled
This bit will be "0" after reset.
• bit[12] SIEN
0 : Interrupts disabled
1 : Interrupts enabled
This bit will be "0" after reset.
• bit[11] SERIE
0 : Receive error interrupts disabled
1 : Receive error interrupts enabled
This bit will be "0" after reset.
• bit[10] SRXIE
0 : Receive buffer full interrupts disabled
1 : Receive buffer full interrupts enabled
This bit will be "0" after reset.
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• bit[9] STXIE
0 : Transmit buffer empty interrupts disabled
1 : Transmit buffer empty interrupts enabled
This bit will be "0" after reset.
• bit[8] STEIE
0 : Transmit end interrupts disabled
1 : Transmit end interrupts enabled
This bit will be "0" after reset.
• bit[6] SMOD
0 : Start-stop transfer mode
1 : Clock synchronized transfer mode
This bit will be "0" after reset.
• bit[5] SFBM
0 : Clear flag bit mode
1 : Set flag bit mode
This bit will be "0" after reset.
• bit[4] SFB
0 : Flag bit value set to "0"
1 : Flag bit value set to "1"
This bit will be "0" after reset.
• bit[3] SFL
0 : Transfer data length is 8 bits
1 : Transfer data length is 7 bits
This bit will be "0" after reset.
• bit[2:1] SPTY
00 : No parity
10 : Even parity
11 : Odd parity
These bits will be "00" after reset.
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• bit[0] SSTP
0 : 1 stop bit
1 : 2 stop bits
This bit will be "0" after reset.
3.5 SBR: Baud Rate Adjustment Register
This register sets values that adjust the baud rate.
bit 15
11 10
8 7
0 0 0 0 0 SBRP
0
SBRV
• bit[10:8] SBRP
000 : Baud rate parameter n = 1
001 : Baud rate parameter n = 2
010 : Baud rate parameter n = 4
011 : Baud rate parameter n = 8
100 : Baud rate parameter n = 16
101 : Baud rate parameter n = 32
110 : Baud rate parameter n = 64
These bits will be undefined after reset.
• bit[7:0] SBRV
These bits are the baud rate adjustment value. They will be undefined after reset.
3.6 MSTS: Modem Status Register
This register provides the states of modem signals.
bit 15
12 11 10 9
D
0 0 0 0 C
T
S
4 3 2 1 0
D
C D
D 0 0 0 0 0 0 T S 0 0
S
S R
R
• bit[11] DCTS
0 : CTS signal has not changed
1 : CTS signal has changed
This bit is read-only. It will be "0" after reset.
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• bit[10] DDSR
0 : DSR signal has not changed
1 : DSR signal has changed
This bit is read-only. It will be "0" after reset.
• bit[3] CTS
0 : CTS input signal value = "0"
1 : CTS input signal value = "1"
This bit is read-only. It will be the CTS pin input value after reset.
• bit[2] DSR
0 : DSR input signal value = "0"
1 : DSR input signal value = "1"
This bit is read-only. It will be the DSR pin input value after reset.
3.7 MCMD: Modem Command Register
This register enables/disables modem status interrupts and auto-enable mode, and controls RTS and DTR output
signals.
bit 15
10 9
S
M
0 0 0 0 0 0 S
I
E
8 7
2 1 0
S
R D
A 0 0 0 0 0 0 T T
E
S R
N
• bit[9] SMSIE
0 : Disables modem status interrupts
1 : Enables modem status interrupts
This bit will be "0" after reset.
• bit[8] SAEN
0 : Disables auto-enable mode
1 : Enables auto-enable mode
This bit will be "0" after reset.
• bit[1] RTS
0 : Output RTS signal "0"
1 : Output RTS signal "1"
This bit will be "0" after reset.
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• bit[0] DTR
0 : Output DTR signal "0"
1 : Output DTR signal "1"
This bit will be "0" after reset.
3.8 SCNT: SIO Control Register
This register controls SIO.
bit 15
0
C
S
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T
P
• bit[0] CSTP
0 : Enable SIO clock supply
1 : Disable SIO clock supply
This bit will be "0" after reset.
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4. SIO Register Addresses
SIO register addresses for the ML2110 are shown below.
0xFA000000
0xFA000004
0xFA000008
0xFA00000C
0xFA000010
0xFA000014
0xFA000018
0xFA00001C
SIO Input Buffer
SIO Output Buffer
Baud Rate Adjustment Register
SIO Status Register
SIO Command Register
Modem Status Register
Modem Command Register
SIO Control Register
5. SIO Operation
There are two methods of SIO operation: start-stop transfers where communication is performed synchronized to
characters, and clock synchronized transfers where communication is performed synchronized to the clock.
5.1 Clock Synchronized Transfers
Clock synchronized transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "1". In this
mode 8-bit data will be input/output synchronized to the clock output from the SCLK pin.
With clock synchronized transfers, transfer data is only 8 bits, so parity bits and flag bits cannot be
added. The SCMD (Command Register) SFBM bit, SFL bit, and SPTY bits will be set to "0", "0", and
"00" respectively.
5.1.1 Clock Synchronized Transfer Baud Rate
B=
f
8 × n × (256 − P)
where
B : baud rate
f : SCP clock frequency
n : baud rate parameter (set by SBR register’s SBRP bit)
P : baud rate adjustment value (set by SBR register’s SBRV bit)
Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.
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5.1.2 Clock Synchronized Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to
the transmit buffer SOB.
2) Write "0" to SOST to indicate that SOB has valid data.
3) If using SIO interrupts, set the SCMD (Command Register) SIEN bit to "1". If using the transmit buffer empty
interrupt, write "1" to the SCMD STXIE bit. If using the transmit end interrupt, write "1" to the SCMD STEIE bit.
4) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command Register)
STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will start when the SCMD
STEN bit is "1" and the CTS input is "1".
5) SOB (Transmit Buffer) data will be transferred LSB first from the TXD output. Also, a synchronous clock will
be transmitted from the SCLK pin. Data on the TXD output will change synchronous to the falling edge of SCLK.
The receiving device should sample TXD data on the rising edge of SCLK.
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will change from
"0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time, then the SSTS STXI bit
will become "1" and an interrupt request to the CPU will be generated.
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to SOB
(Transmit Buffer) and write "0" to the SOST bit.
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE bit. This will
disable interrupt requests from SIO.
9) When transfer of the eighth bit of data ends, the SSTS (Status Register) SOST bit will become "1" (transmit
buffer SOB is empty), SCLK will stop, and the transmit operation will end. If the SCMD’s STEIE and SIEN bits
are "1" at this time, then the SSTS’s STEI bit will become "1" and an interrupt request to the CPU will be generated.
This interrupt can be released by writing "0" to the SSTS’s STEI bit or the SCMD’s STEIE bit.
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5.1.3 Clock Synchronized Receive Operation
1) The receive operation will begin if the MCMD’s SAEN bit is "0" (auto-enable mode disabled) and the SCMD’s
SREN bit is "1" (data receive enabled).
2) When the receive operation begins, a synchronous clock will be output from SCLK.
3) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set SCMD’s
SRXIE bit to "1".
4) The transmitting device should input the data to be transferred on RXD on the falling edge of SCLK, LSB first.
The SIO will sample RXD data on SCLK’s rising edge, shifting it into the Receive Shift Register.
5) When the eighth bit of data has been received, the receive shift register’s data is transferred to SIB.
However, it will not be transferred to SIB if an overrun error occurs.
6) After data has transferred from the receive shift register to the receive buffer SIB, SIST will change from "0" to
"1", indicating that there is valid data in the receive buffer SIB. If SCMD’s SRXI bit and SIEN bit are both "1" at
this time, an interrupt request to the CPU will be generated.
7) To continue receiving data, read the SIB data after SIS becomes "1", and then write "0" to SIST.
8) To end the receive operation, write "0" to SCMD’s SREN bit. At the time "0" is written to SREN, data currently
being received will be transferred to SIB and the receive operation will end.
9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred from the
receive shift register to the receive buffer, the SIO will assume that an overrun error (receipt of further data before
the value of the receive buffer SIB is read) has occurred.
SSTS’s SOVE bit will then be set to "1". In this case the receive shift register value will not be transferred to the
receive buffer SIB. If SCMD’s SERIE bit and SIEN bit are "1", then SSTS's SERI bit will be set to "1" and an
interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s SOVE bit or to
SCMD’s SERIE or SIEN bit.
Start-Stop Transfers
Start-stop transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "0". In this mode data
is output LSB first from TXD, and input LSB first from RXD.
5.2.1 Start-Stop Transfer Baud Rate
B=
f
16 × n × (256 − P)
where
B : baud rate
f : SCP clock frequency
n : baud rate parameter (set by SBR register’s SBRP bit)
P : baud rate adjustment value (set by SBR register’s SBRV bit)
Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.
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5.2.2 Start-Stop Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to the transmit
buffer SOB. Next write "0" to SOST to indicate that SOB has valid data.
2) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command Register)
STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will start when the SCMD
STEN bit is "1" and the CTS input is "1".
3) For start-stop transmit operation, a start bit "0" will be output from TXD. Then the data written in SOB will be
output LSB first. If SCMD’s SFL bit is "0", then 8 bits of data will be output. If the SFL bit is "1", then 7 bits will
be output.
4) When SCMD (Command Register) SFBM bit is "0", a parity bit will be output after the SOB data.
The parity will be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit is "1" and
SPTY is "00", then the value set in SCMD’s SFB bit will be output after the SOB data.
If SCMD’s SFBM bit is "0" and the SPTY field is "0", then neither a parity bit nor flag bit will be output after SOB
data.
5) Finally, one stop bit will be output if the SCMD (Command Register) SSTP bit is "0", or two stop bits will be
output if the SSTP bit is "1". This will end the transfer of one frame of data.
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will change from
"0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time, then the SSTS STXI bit
will become "1" and an interrupt request to the CPU will be generated.
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to SOB
(Transmit Buffer) and write "0" to the SOST bit. This will disable interrupt requests from SIO.
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE bit. The will
disable interrupt requests from SIO.
9) When transfer of the stop bit ends, the transmit operation will end if the SOST bit is "1". If the SCMD's STEIE
and SIEN bits are "1" at this time, then the SSTS's STEI bit will become "1" and an interrupt request to the CPU
will be generated. This interrupt can be released by writing "0" to the SSTS's STEI bit or the SCMD's STEIE or
SINT bit.
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5.2.3 Start-Stop Receive Operation
1) The receive operation can begin if the MCMD’s SAEN bit is "0" and the SCMD’s SREN bit is "1".
SCMD’s SRXIE bit to "1". If using the receive error interrupt, set SCMD’s SERIE bit to "1".
2) The SIO receive operation will start when a falling edge is detected on RXD. The first bit of data is received as
the start bit. If the received value is "1", then it will not be recognized as a start bit, the receive operation will be
suspended, and the device will wait for another RXD falling edge to be detected. If the received value is "0", then
data will continue to be received.
3) When the start bit is received, receive of data will start. If SCMD’s SFL bit is "0", then 8 bits of data will be
input serially into the receive shift register. If the SFL bit is "1", then 7 bits of data will be input.
4) When SCMD (Command Register) SFBM bit is "0", a parity bit will be received after the data. The parity will
be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit is "1" and SPTY is "00",
one flag bit will be received. If SCMD’s SFBM bit is "0" and the SPTY field is "00", then neither a parity bit nor
flag bit will be received.
5) Finally one stop bit will be received. Even if SCMD’s SSTP bit is "1", only the first stop bit will be received.
6) When all bits have been received, the data input in the receive shift register will be transferred to the receive
buffer SIB. However, if either of the following two conditions applies, then data will not be transferred to SIB, and
SIB will retain its previous value.
1. SCMD’s SFBM bit is "1", its SPTY field is "00", and the received flag bit does not match SCMD’s SFB bit.
2. An overrun error occurred.
7) When data has been transferred from the receive shift register to the receive buffer SIB, SSTS’s SIST will
change from "0" to "1". If SCMD’s SRXIE and SIEN bits are both "1", then SSTS’s SRXI bit will become "1" and
an interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s SIST bit or to
SCMD’s SRXIE or SIEN bit.
8) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred from the
receive shift register to the receive buffer, the SIO will assume that an overrun error (receipt of further data before
the value of the receive buffer is read) has occurred. SSTS’s SOVE bit will then be set to "1".
9) If the received stop bit is "0", then it will be considered indication of a framing error. SSTS’s SFRE bit will then
be set to "1".
10) When SCMD’s SPTY field is "10" or "11", a mismatch between parity generated from the receive data and the
parity bit will be considered a parity error. SSTS’s SPTE bit will then be set to "1".
11) If one or more of the SOVE, SFRE, and SPTE bits are "1" and the SCMD' s SERIE and SIEN bits are "1", then
SSTS's SERI bit will be set to "1" and an interrupt request to the CPU will be generated.
12) To release the interrupt for any error, write "0" to all of SSTS’s SOVE, SFRE, and SPTE bits, or write "0" to
SCMD’s SERIE or SIEN bits.
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Parallel Interface
1. Features
The parallel interface (PIO) inputs and outputs 8-bit wide parallel data. It has three data transfer
methods: software control mode where input/output is specified with 1-bit ports, handshake
control mode through strobe/acknowledge signals and flags indicating buffer status, and bus
control mode through read/write signals.
2. PIO Functions
2.1 PIO Data Size
• 8 bits
2.2 PIO Control Modes
• Software control mode
In software control mode, the PIO controls input and output of bits in accordance with the value
written in the direction register. If a direction register bit is "0", then the corresponding pin level will
be an input. If "1", then the value in the corresponding output buffer will be output to the pin.
• Handshake control mode
In handshake control mode, the PIO inputs external data through a handshake using a strobe signal
(PSTB) and input buffer full signal (PIBF). It outputs data externally through a handshake using an
output buffer full signal (POBF) and acknowledge signal (PACK).
• Bus control mode
In bus control mode, the PIO controls data input/output with a chip select signal (PCS), flag/buffer
select signal (PIOA), read signal (PACK), and write signal (PSTB).
2.3 PIO Interrupts
Interrupts to the CPU core are available when handshake control mode or bus control mode is
selected.
• Input buffer full interrupts
When PCMD’s PIEN bit is "1", writing "0" to the PIIE bit will disable input buffer full interrupts, and
writing "1" will enable them. When the PIEN bit is "0", input buffer full interrupts will be disabled
regardless of the value of the PIIE bit.
If input buffer full interrupts are enabled, then one will be generated whenever the input buffer is
written from an external device.
To release input buffer full interrupts, write "0" to the status register PSTS’s PIST bit, to the command
register PCMD’s PIIE bit, or to PCMD’s PIEN bit.
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• Output buffer empty interrupts
When PCMD’s POENbitis"1", writing"0"tothe POIE bit will disable output buffer empty interrupts,
and writing "1" will enable them. When the POEN bit is "0", output buffer empty interrupts will be
disabled regardless of the value of the POIE bit.
If output buffer empty interrupts are enabled, then one will be generated whenever the output buffer
is read by an external device.
To release output buffer empty interrupts, write "0" to the status register PSTS’s POST bit, to the
command register PCMD’s POIE bit, or to PCMD’s POEN bit.
PIO Registers
These registers control the PIO.
3.1 PIB: PIO Input Buffer
This buffer saves data input from an external device. It will be undefined after reset.
bit 7
0
PIB
3.2 POB: PIO Output Buffer
This buffer saves data to be output to an external device. It will be undefined after reset.
bit 7
0
POB
3.3 PDIR: PIO Direction Register
This register specifies under software control whether each parallel port bit is input or output. It will
be "00000000" after reset.
bit 7
0
PDIR
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3.4 PSTS: PIO Status Register
This register provides the PIO status.
bit 7 6 5 4 3 2 1 0
0 0
P
I
N
T
I
P
I
N
T
O
P
A
C
K
P
O
S
T
P P
S I
T S
B T
• bit[5] PINTI
0 : No input buffer full interrupt
1 : Input buffer full interrupt occurred
This bit will be "0" after reset.
• bit[4] PINTO
0 : No output buffer empty interrupts
1 : Output buffer empty interrupt occurred
This bit will be "0" after reset.
• bit[3] PACK
0 : No acknowledge
1 : Acknowledge
This bit will be undefined after reset.
• bit[2] POST
0 : Output buffer full
1 : Output buffer empty
This bit can only be written with "0". It will be "1" after reset.
• bit[1] PSTB
0 : No strobe
1 : Strobe
This bit will be undefined after reset.
• bit[0] PIST
0 : Input buffer empty
1 : Input buffer full
This bit can only be written with "0". It will be "0" after reset.
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3.5 PCMD: PIO Command Register
This register specifies the parallel port mode and specifies whether interrupts are enabled or
disabled. It will be "00000000" after reset.
bit 7 6 5 4 3 2 1 0
P
M
O
D
P
O
E
N
P
P P
I 0 0 O I
E
I I
N
E E
• bit[7:6] PMOD
00 : Bus control mode
01 : Handshake control mode
1x : Software control mode
• bit[5] POEN
0 : Output operation disabled
1 : Output operation enabled
• bit[4] PIEN
0 : Input operation disabled
1 : Input operation enabled
• bit[1] POIE
0 : Output buffer empty interrupts disabled
1 : Output buffer empty interrupts enabled
• bit[0] PIIE
0 : Input buffer full interrupts disabled
1 : Input buffer full interrupts enabled
4. PIO Register Addresses
For the ML2110, PIO register addresses are listed below.
0xFB000000
0xFB000004
0xFB000008
0xFB00000C
0xFB000010
PIO Input Buffer
PIO Output Buffer
PIO Direction Register
PIO Status Register
PIO Command Register
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5. PIO Operation
5.1 Software Control Mode
In software control mode data input/output and control signals are all controlled by software.
5.1.1 Data Input from External Device
1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is acceptable).
2) Read the input buffer PIB to read the parallel port’s pin levels at that time.
5.1.2 Data Output to External Device
1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is acceptable).
2) Write a value to the output buffer POB.
3) Write "1" to the bits in PDIR (Direction Register) that correspond to parallel port pins that will be outputs. This
starts to drive the parallel port for data to be output.
4) If "0" is written to any bits in PDIR, then the corresponding parallel port pins will stop being driven.
5.2 Handshake Control Mode
In handshake control mode data input is controlled by handshake using a strobe (PSTB), input buffer
full (PIBF), acknowledge (PACK), and output buffer full (POBF) for input/output.
5.2.1 Data Input from External Device
(A) SCP operation
1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to enable input
operation.
2) When data is written to the input buffer PIB from the external device, the PSTS (Status Register) PIST bit will
become "1" to indicate that there is valid data in PIB. When PSTS’s PIST bit becomes "1", the input buffer full
output (PIBF) will become "1".
3) If PSTS’s PIST bit is "1" and input buffer full interrupts have been enabled (PCMD’s PIIE bit is "1"), then a PIO
interrupt to the CPU core will be generated.
4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and reads the input
buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.
5) When PSTS’s PIST bit becomes "0", the input buffer full output (PIBF) also becomes "0".
6) Repeat the operation from step 2).
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(B) External operation
1) Verify that the input buffer full output (PIBF) is "0".
2) Drive the parallel input/output bus (PD[7:0]) with input data.
3) Set the strobe input (PSTB) to "1". This writes the data to the input buffer PIB.
4) When the input buffer full output (PIBF) becomes "1", stop driving the parallel input/output bus and set the
strobe input (PSTB) to "0".
5) Repeat the operation from step 1).
5.2.2 Data Output to External Device
(A) SCP operation
1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to enable
output operation.
2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is empty.
3) Write data to the output buffer POB.
4) Write "0" to PSTS’s POST bit. When POST becomes "0", the output buffer full output (POBF) will become
"1".
5) If PSTS’s POST bit is "1" and output buffer full interrupts have been enabled (PCMD’s POIE bit is "1"), then a
PIO interrupt to the CPU core will be generated. This interrupt will be released by writing "0" to PSTS’s POST bit
or writing "0" to PCMD’s POIE bit.
6) Write data to the output buffer POB and repeat the operation from step 4).
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(B) External operation
1) Verify that the output buffer full output (POBF) is "1".
2) Set the acknowledge input (PACK) to "1". When the acknowledge input is set to "1", the PIO will output the
value of the output buffer (POB) to the parallel input/output bus (PD[7:0]).
3) Verify that the output buffer full output (POBF) is "0".
4) Read the value on the input/output bus.
5) Set the acknowledge input (PACK) to "0". When the acknowledge input becomes "0", the PIO will stop driving
the input/output bus.
6) Repeat the operation from step 1).
5.3 Bus Control Mode
In bus control mode data input/output is controlled externally by the chip select input (PCS), flag/buffer select
input (PIOA), read input (PACK), and write input (PSTB).
(A) SCP operation
1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to enable input
operation.
2) When an external device writes data to the input buffer PIB, the PSTS (Status Register) PIST bit will become
"1", indicating that there is valid data in the input buffer PIB.
3) If PCMD’s PIIE bit is "1", then a PIO interrupt to the CPU core will be generated.
4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and reads the input
buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.
5) Repeat the operation from step 2).
(B) External operation
1) Read the input buffer full output (PIBF).
Chip select input
Flag/buffer select input
Read input
Write input
PCS
PIOA
PACK
PSTB
0
0
0
1
2) Verify that the input buffer full output (PIBF) is "0".
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3) Write data to the input buffer (PIB).
Chip select input
Flag/buffer select input
Read input
Write input
Input/output bus
PCS
PIOA
PACK
PSTB
PD[7:0]
0
1
1
0
Write data
4) Repeat the operation from step 1).
5.3.2 Data Output to External Device
(A) SCP operation
1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to enable
output operation.
2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is empty.
3) Write data to the output buffer POB.
4) Write "0" to PSTS’s POST bit. When POST is "0", the output buffer full output (POBF) will become "1".
5) When POST becomes "1" and PCMD’s POIE bit is "1", then a PIO interrupt to the CPU core will be generated.
This interrupt will be released by writing "0" to PSTS’s POST bit or by writing "0" to PCMD’s POIE bit.
6) Repeat the operation from step 3).
(B) External operation
1) Read the output buffer full output (POBF).
Chip select input
Flag/buffer select input
Read input
Write input
PCS
PIOA
PACK
PSTB
0
0
0
1
2) Verify that the output buffer full output (POBF) is "1".
3) Read the output buffer (POB).
Chip select input
Flag/buffer select input
Read input
Write input
Input/output bus
PCS
PIOA
PACK
PSTB
PD[7:0]
0
1
0
1
Read data
4) When the output buffer is read, PSTS's POST bit will become "1".
5) Repeat the operation from step 1).
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Timer Unit
1. Features
The timer unit (TMR) is a 16-bit programmable timer. It has two modes: an interval timer mode
which requests interrupts to the CPU core, and a clock division mode which generates a 50% duty,
frequency divided clock.
2. TMR Functions
2.1 Counter
• 16-bit up counter
2.2 Counter Clock Period
• φ (SCP operating frequency × 1)
• 4φ (SCP operating frequency × 4)
• 16φ (SCP operating frequency × 16)
• 64φ (SCP operating frequency × 64)
2.3 Interval Timer Interrupts
When the counter overflows (counter value changes from 0xFFFF to 0x0000), it will request an
interrupt to the CPU core.
2.4 Divided Clock Generation
When the counter overflows (counter value changes from 0xFFFFto0x0000),it will invert the value
currently being output.
3. TMR Registers
3.1 TIR: Timer Initial Value Register
This register saves the counter’s initial value. When this register is written, the same value will be
written to the Timer Value Register (TCR). This register will be undefined after reset.
0
bit 15
TIR
3.2 TCR: Timer Value Register
This register provides the counter’s current value. It will be undefined after reset.
bit 15
0
TCR
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3.3 TSTS: Timer Status Register
This register provides TMR status.
bit 7
1 0
T T
0 0 0 0 0 0 D C
A A
T
• bit[1] TDAT
0 : No timer interrupt request occurred (interval timer mode)
Divided clock output is "0" (divided clock mode)
1 : Timer interrupt request occurred (interval timer mode)
Divided clock output is "1" (divided clock mode)
• bit[0] TCA
0 : Timer counter operation is suspended
1 : Timer counter is operating
3.4 TCMR: Command Register
This register sets TMR operation.
bit 7 6 5 4 3 2 1 0
T
T
C 0 M
O
G
D
T
C 0 0
A
I
T
C
S
• bit[7] TCG
0 : Disable timer counter operation
1 : Enable timer counter operation
This bit will be "0" after reset.
• bit[5] TMOD
0 : Interval timer mode
1 : Divided clock mode
This bit will be "0" after reset.
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• bit[4] TCAI
0 : Disable auto-initialization of timer value register
1 : Enable auto-initialization of timer value register
This bit will be "0" after reset.
• bit[1:0] TCS
00 : Count clock Φ
01 : Count clock 4 Φ
10 : Count clock 16 Φ
11 : Count clock 64 Φ
These bits will be "00" after reset.
4. TMR Register Addresses
The ML2110 has two timers. The register addresses for each are listed below.
TMR1
TMR2
Timer Initial Value Register
Timer Value Register
Timer Status Register
Timer Command Register
Timer Initial Value Register
Timer Value Register
Timer Status Register
Timer Command Register
0xF8000000
0xF8000004
0xF8000008
0xF800000C
0xF8000010
0xF8000014
0xF8000018
0xF800001C
5. TMR Operation
5.1 Interval Timer Mode
In interval timer mode counting begins from the value set in the Timer Initial Value Register, and a
timer interrupt is generated to the CPU when the counter overflows.
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "0", setting interval timer mode as the operating mode
4) To generate periodic interrupts set TCMR’s TCAI bit to "1", which will set the counter to be loaded with the
value of the Timer Initial Value Register each time the counter overflows. For a one-shot interrupt set the TCAI bit
to "0".
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will simultaneously
write the same value to the Timer Value Register TCR.
6) Write "1" to TCMR’s TCG bit to start counting. An interrupt will be generated when the counter overflows.
7) To release the interrupt set the TSTS (Status Register) TDAT bit to "0" in software.
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5.2 Divided Clock Mode
In divided clock mode counting begins from the value set in the Timer Initial Value Register, and the divided clock
output value inverts when the counter overflows.
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "1", setting divided clock mode as the operating mode.
4) To generate a periodic divided clock set TCMR’s TCAI bit to "1", which will set the counter to be loaded with
the value of the Timer Initial Value Register each time the counter overflows. For a one-shot divided clock set the
TCAI bit to "0".
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will simultaneously
write the same value to the Timer Value Register TCR.
6) Write "1" to TCMR’s TCG bit to start counting and generating a divided clock.
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Speech Data Registers
1. Features
This is a register group and control circuit used for speech output.
2. Speech Data Registers Functions
2.1 Speech Output Registers
These are 12-bit registers that store speech output data. There are two registers and one output
register configured to operate at the speech sampling frequency.
Use of two registers reduces the frequency of interrupt generation during waveform output, which
lightens the CPU load. The output stage is provided in the register, which corrects the inaccuracies
in the sampling frequencies that are caused by interrupts.
DATA
CLK
DATA
Interrupt to
D WR CPU
12-bit REG
(DAREG1)
TMR2 output
12-bit REG
(DAREG2)
1
1/2
12-bit REG
(DAREGO)
DAC
The two registers are in parallel, continuously written with D/A conversion data. The output
register reads the data from the two registers alternately in every sampling cycle.
The output level registers' clock is generated by TMR2. This clock is multiplied by 1/2 to output
interrupt signals. The interrupt signals are used to write the waveform output data to the speech
output registers.
Note the following when the MSM7576 mode (described later) is not used when using the speech
output registers :
– The TMR2 must be set to the divided clock mode.
– To write data to DAC1 and DAC2, write to DAC2 first, then DAC1.
– Do not clear the status register of the TMR2. If it is cleared by an interrupt routine, the sampling
frequency for the speech output will change.
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TMR2 output
0xxxx
DAREG0
0x0001
0x0001
0x0002
DAREG1
0x0001
0x0003
DAREG2
0x0000
0x0002
Interrupt to
CPU
2.2 MSM7576 Mode
This mode forces operation to be the sameasMSM7576operation. Interrupt signalsfromTMR2are
output directly as interrupts to the CPU.
DATA
CLK
TMR2 output
Interrupt to CPU
12-bit REG
DAC
2.3 Digital Signal Output
There are 16-bit registers that store digital signal output data. There are two registers and one output register.
Use of two registers reduces the frequency of interrupt generation during digital signal output, which lightens
the CPU load.
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DATA
DATA
CLK
Interrupt to
XSYNC
D WR CPU
16-bit REG
(ULAW_REG1)
16-bit REG
(ULAW_REG2)
1
1/2
16-bit REG
(DOUT_REG)
Shifter
BCLK
DOUT
The two registers are in parallel, continuously written with digital signal output data. The output register
reads the data from the two registers alternately in XSYNC.
The output register’s clock is XSYNC. This clock is multiplied by 1/2 to output interrupt signals. The interrupt
signals are used to write the digital signal output data to two registers.
Interrupt to CPU
(XSYNC/2,CLKA synchronous)
ULAW_REG1
ULAW_REG2
0x0001
0x0003
0x0000
0x0002
XSYNC
0xxx
DOUT_REG
DOUT
0xxx
0x0000
0x0000
0x0001
0x0001
0x0002
0x0002
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3. Speech Data Registers Details
3.1 DAC1: Speech Output Register 1
This register stores speech output data. It will be "000000000000" after reset.
bit 15
12 11
0
0 0 0 0
DAC1
3.2 DAC2: Speech Output Register 2
This register stores speech output data. It will be "000000000000" after reset.
bit 15
12 11
0
0 0 0 0
DAC2
3.3 DACO: D/A Conversion Register
This register stores data to be input to the D/A converter. It will be "000000000000" after reset.
bit 15
12 11
0
0 0 0 0
DACO
3.4 USTAT: Status Register
This register indicates whether or not the speech output registers/circuits have generated an
interrupt to the CPU.
Writing "0" to this register releases the interrupt from the speech output registers/circuits. In
MSM7576 mode USTAT will become "0" when the TMR2 interrupt is released.
0 0 0 0 0 0
USTAT
2 1 0
ULAWINT
bit 7
• bit[1] ULAWINT: Interrupt during digital signal output.
• bit[0] USTAT:
Interrupt during speech data output with D/A converter.
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3.5 UPORT: General Register
This is a general register. It will be "0" after reset.
1 0
0 0 0 0 0 0 0
UPORT1
0 0 0 0 0 0 0
UPORT0
9 8 7
bit 15
3.6 UCOM: Command Register
This register sets operation mode of speech data register control.
4
0 0 0 0 0
0
DOINT
DADO
MODE
bit 7
• bit[2]: DOINT
This is allows interrupts during digital signal output.
0: Interrupt disable
1: Interrupt signal output
• bit[1]: DADO
This bit switches speech output with D/A converter or digital signal output.
0: Speech output with D/A converter
1: Digital signal output
• bit[0]: MODE7576
This bit sets MSM7576 mode.
3.7 ULAWREG1: Digital Signal Output Register 1
This register stores digital signal output data. It will be “0000000000000000” after reset.
0
bit 15
ULAWREG1
3.8 ULAWREG2: Digital Signal Output Register 2
This register stores digital signal output data. It will be “0000000000000000” after reset.
0
bit 15
ULAWREG2
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4. Speech Output Registers Address Configuration
The addresses used by the speech output registers/circuits are assigned at 0x80000000. Accesses to
this space will be 3τ access.
Speech Output Register 1
Speech Output Register 2
D/A Conversion Register
Status Register
Command Register
General Register
Digital Signal Output Register 1
Digital Signal Output Register 2
Digital Signal Output Register
DAC1
DAC2
DACO
USTAT
UCOM
UPORT
ULAWREG1
ULAWREG2
DOUTREG
0x80000000
0x80000004
0x80000008
0x8000000C
0x80000010
0x80000020
0x80000014
0x80000018
0x8000001C
Speech Output
1. Output Waveform from DAO1
The speech output pin directly outputs the output of the DA converter.
The output waveform from DAO1 will be a staircase synchronized to the sampling frequency.
Maximum output amplitude will be (4095/4096 × VDD).
2. Output Filter
Because the output from DAO1 is a staircase described above, add a low-pass filter. The diagram
below shows a reference circuit for a Butterworth low-pass filter.
1200p
2
3
+
1
8
R
2200p
0.1µ
R
R
15
14
1K
1000p
300p
+
R
4
R
11
12
16
13
220p
-
10
+ 9
6
5
+
7
1K
MC14573P
Butterworth low-pass filter
R=47k, f=4.8kHz (95 model: for 12kHz sampling)
R=36k, f=6.4kHz (96 model: for 16kHz sampling)
R=27k, f=9.6kHz (97 model: for 22kHz sampling)
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Oscillation Circuit
There are two methods to generate the ML2110 system clock: adding an external crystal oscillator
or supplying an external clock.
1. Crystal Oscillator
The diagram below shows a connection example for a crystal oscillator.
22pF
CLK
ML2110
Crystal
1MΩ
22pF
XO
GND
2. External Clock
The diagram below shows an example using an external clock.
ML2110
External Clock
CLK
Open
XO
The external clock is input on the CLK pin. Leave the XO pin open.
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1
2
A
+
AVCC
10uF/16V
CE3
C4
+
VCC
CE7
10uF/16V
1
3
D1
LED
R5
270
I
IN
+
1
OUT
/CONFIG
3
CP4
0.1uF
CE2
100uF/25V
U2
LM3940IT-3.3
C17
1uF/50V
U3
DLC
O
CP3
0.1uF
1
1 2 3
CE6
33uF/16V
2
2
SW SPDT
S2
3
O
I
13
12
+
CE4
5
4
3
2
1
1
74LVC32
11
U8D
+
+
C1
10uF/16V
JP1
JUMPER
CE1
10uF/16V
PWRCON
5
4
3
2
1
CN1
U23
DLC
+
+
10uF/16V
3.3V 1A
CE5
33uF/16V
+
R1
10K
1
2
C3
1uF/50V
C2
1uF/50V
7
1
14
+3.3V
B1
B2
B3
B5
B7
B9
B10
B13
B14
B20
B29
B31
A
CP2
0.1uF
1
2
1
2
1
2
3
4
1
1
2
3
4
HL3
HL2
HL1
HL0
8
7
6
5
2
3
4
5
6
7
8
9
/UPORT1
R3
10K
VCC
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
R4
10K
AEN
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
8
7
6
5
HL3
HL2
HL1
HL0
SW DIP-4
S1
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
10K
MR1
SW DIP-4
S3
PCXTCON
GNDA
RESETDRV
VCC+5A
VCC-5
VCC-12
VCC+12
GNDB
IOW
IOR
CLK
VCC+5B
GNDC
U1
A+3.3V
CP1
0.1uF
VCC
74LVC14
2
I
G
0.01uF
O
0.1uF
C3P2
I
G
C3P1
O
U11A
3
3
+3.3V
1
19
2
4
6
8
11
13
15
17
74LVT244
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
U13
R8
10K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA8
SA0
SA2
SA3
SA4
SA5
SA6
SA7
SA1
VCC
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1
3
5
7
9
12
14
16
18
2
4
6
8
11
13
15
17
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0
P1
P2
P3
P4
P5
P6
P7
U9
VCC
GND
P=Q
20
10
18
16
14
12
9
7
5
3
74HC688
G
VCC
GND
Y0
Y1
Y2
Y3
3
3
20
10
19
2
1
3
3
I
G
96/101
I
G
0.01uF
O
0.1uF
C3P12
O
C3P11
16
8
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
GND
74LVC138
G1
G2A
G2B
A
B
C
U4
74LVC139
G
A
B
U5A
SA1
1
2
3
6
4
5
1
2
3
3
3
I
G
I
G
+3.3V
1
2
1
2
I
G
I
G
U8A
1
2
1
2
3
3
3
VCC
0.01uF
O
0.1uF
C3P6
O
C3P5
3
3
I
G
I
G
0.01uF
O
0.1uF
C3P4
O
C3P3
1
2
1
2
I
G
I
G
0.01uF
O
0.1uF
C3P10
O
C3P9
+3.3V
74LVC32
0.01uF
O
0.1uF
C3P8
O
C3P7
16
8
15
14
13
12
11
10
9
7
+3.3V
1
2
1
2
+3.3V
1
2
1
2
U11B
7
5
14
1
LED
D2
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
19
1
2
3
4
5
6
7
8
9
2
VCC
GND
270
R6
9
10
B1
B2
B3
B4
B5
B6
B7
B8
74LVT245
G
DIR
A1
A2
A3
A4
A5
A6
A7
A8
U12
74LVC14
6
U11C
74LVC14
5
7
4
4
3
15
14
13
U5B
VCC
GND
Y0
Y1
Y2
Y3
1
2
+3.3V
20
10
18
17
16
15
14
13
12
11
U6B
3
3
I
G
I
G
+3.3V
1
2
1
2
/PACK
/PSTB
0.01uF
O
0.1uF
C3P16
O
R7
10K
VCC
C3P15
74LVC32
8
U6C
74LVC32
6
16
8
12
11
10
9
+3.3V
1
2
74LVC139
G
A
B
I
G
0.01uF
O
U6A
3
I
G
0.1uF
C3P20
74LVC32
3
14
2
1
14
7
O
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
R2
10K
3
3
I
G
I
G
0.01uF
O
0.1uF
C3P18
O
C3P17
1
2
1
2
+3.3V
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
7
13
14
1
11
3
4
7
8
13
14
17
18
14
7
3
2
VCC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q
Q
U7A
PD[0..7]
D[0..31]
9
10
20
10
2
5
6
9
12
15
16
19
74LVC74
6
5
74LVC14
12
U11F
74LVC374
OC
CLK
D0
D1
D2
D3
D4
D5
D6
D7
U10
VCC
GND
CLK
D
3
3
I
G
I
G
74LVC32
8
U8C
0.01uF
O
0.1uF
C3P14
O
C3P13
PD[0..7]
13
12
7
9
14
14
7
C3P19
4
PR
CL
1
1
3.3V 1A
3
1
2
1
2
1
2
1uF/50V
2
1
2
+
1
2
1
2
2
G
1
2
1
2
1
2
1
2
1
2
14
7
14
7
G
2
1
+
VCC
2
1
2
2
G
14
7
U11D
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
2
1
2
+3.3V
D31
D30
D29
D28
74LVC32
11
U6D
74LVC14
8
7
11
14
5
4
14
7
11
12
U11E
VCC
GND
D[0..31]
Q
Q
74LVC14
10
CLK
D
/PCS
PIOA
10
PR
CL
13
+3.3V
14
+
1
74LVC32
6
U8B
74LVC74
8
9
U7B
/RST
OKI Semiconductor
7
14
7
14
7
3
FEDL2110-01
ML2110
SYSTEM CONFIGURATION EXAMPLE
From page 96 to page 98 is indicated the circuit diagram of a text-to-speech printed circuit board conforming to
ISA for PCs that uses the ML2110.
97/101
HEADER 3
3
2
1
HEADER 3
JP3
3
2
1
JP4
HEADER 7
1
2
3
4
5
6
7
CN3
R22
10K
+3.3V
R21
10K
R13
10K
/EXTINTSB
R12
10K
R20
10K
C5
22p
/UPORT1
R23
10K
+3.3V
A[0..23]
1M
R10
33MHz
Y1
TPIN
1
TP1
/RST
/STBY
/RTS
/CTS
TXD
RXD
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C6
22p
A
1
2
2
4
5
136
138
139
141
142
144
12
13
14
15
17
18
11
10
135
109
113
112
115
110
111
19
20
25
24
22
21
26
107
106
105
104
103
102
101
99
98
97
96
95
94
92
91
90
89
88
87
85
84
83
82
81
3
3
NC
NC
DAO
MD
BCLK
XSYNC
BR3
BGT3
DOUT
X1/CLK
X2
CLKENA
CLKA
CLKB
CLKFDBL
RST
STBY
EXINT1
EXINT0
TEST2/TSTM2
TEST1/TSTM1
TEST0/TSTM0
UPORT1
UPORT0
TXD
RXD
DTR
DSR
RTS
CTS
SCLK
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0.01uF
I O
G
0.1uF
C3P24
I O
G
A
3
2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ROM
SRAM
AS
RD
WR3
WR2
WR1
WR0
RAS
CAS3
CAS2
CAS1
CAS0
WE
WAIT
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRD
PWR
PCS
PA
POBF
PIBF
+
-
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
1
8
9
23
37
51
65
79
93
108
121
133
134
143
1
2
6
7
16
30
44
58
72
86
100
114
128
137
140
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C3P23
4
A
13
A+3.3V
3
I
G
I
G
U16
0.01uF
O
0.1uF
C3P26
1
2
1
2
3
3
I
G
I
G
1
2
1
2
A
I
G
I
G
100K
R15
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0.01uF
O
0.1uF
C3P28
O
1
2
1
2
A
C11
680pF
100K
R16
I
G
I
G
0.01uF
O
0.1uF
C3P30
O
C3P29
1
1
/CAS1
/CAS0
/WE
/ROM
/SRAM
/AS
/RD
/WR3
/WR2
/WR1
/WR0
/RAS
/PACK
/PSTB
/PCS
PIOA
100K
R17
1
2
1
2
C12
56pF
R14
10K
D[0..31]
PD[0..7]
+3.3V
3
3
A
I
G
I
G
2
C7
56pF
1300pF
C8
11pF
C14
2
D[0..31]
1
2
1
2
C13
56pF
R15~R19
0.01uF
O
0.1uF
C3P32
O
C3P31
PD[0..7]
3
3
3
3
I
G
0.01uF
O
TP2
+
-
SOCKET
5
6
TPAD
1
TP3
TPAD
1
I
G
0.1uF
C3P34
O
C3P33
1
2
1
2
I
G
I
G
0.01uF
O
0.1uF
C3P36
O
C3P35
LT1212CS
7
U15B
3
3
100K
R18
1
2
1
2
+3.3V
100K
R19
1
1
2
2200pF
C9
130pF
C16
2
A
C10
18pF
TXD
/RTS
RXD
/CTS
C15
11pF
2
1
3
20
8
10
17
13
14
12
11
T1IN
T2IN
R1OUT
R2OUT
V+
VV-
C1+
C1-
+
-
7
VCC
C3P27
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
3
3
AVCC
LT1212CS
1
U15A
0.01uF
O
0.1uF
C3P38
O
C3P37
ML2110(LQFP144)
131
132
116
117
122
120
119
118
124
129
127
126
125
130
123
80
78
77
76
75
74
73
71
70
69
68
67
66
64
63
62
61
60
59
57
56
55
54
53
52
50
49
48
47
46
45
43
40
39
41
42
38
36
35
34
33
32
31
29
28
27
8
A[0..23]
1
2
1
2
4
13
O
1
2
4
13
GND
GND
6
9
9
C3P25
1
2
1
8
O
T1OUT
T2OUT
R1IN
R2IN
LT1212CS
10
I
G
VCC
1
2
1
2
MAX233ACWP
5
18
4
19
16
11
12
15
U14
0.01uF
C2C2-
U15C
I
G
0.1uF
C3P22
C2+
C2+
3
O
C3P21
14
15
+
-
4
13
3
1
2
1
2
1
2
LT1212CS
16
U15D
5
9
4
8
3
7
2
6
1
A
20K(VR)
2
R11
CONNECTOR DB9
P1
A
CON2
1
2
CN2
OKI Semiconductor
2
3
1
3
FEDL2110-01
ML2110
9
HEADER 3
1
2
3
JP9
A[0..23]
98/101
1
2
3
+3.3V
74LVC139
G
A
B
U21A
A22
VCC
GND
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
+3.3V
Y0
Y1
Y2
Y3
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
+3.3V
16
8
4
5
6
7
A23
A22
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
+3.3V
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
3
3
I
G
I
G
0.01uF
O
0.1uF
C3P40
O
C3P39
33
14
12
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
33
14
12
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
33
14
12
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
33
14
12
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
1
2
VSS
VSS
VCC
D15/A-1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VSS
VCC
D15/A-1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VSS
VCC
D15/A-1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
/AS
MR27V6452D-SOP
BYTE/VPP
OE
CE
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MR27V6452D-SOP
U20
BYTE/VPP
OE
CE
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MR27V6452D-SOP
U19
BYTE/VPP
OE
CE
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
+3.3V
1
2
VSS
VSS
VCC
D15/A-1
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MR27V6452D-SOP
U18
BYTE/VPP
OE
CE
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U17
13
32
23
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
13
32
23
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
13
32
23
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
13
32
23
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
I
G
I
G
I
G
I
G
O
I
G
0.1uF
C3P44
O
C3P43
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
0.01uF
O
0.1uF
C3P46
O
C3P45
0.01uF
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
O
0.1uF
C3P48
I
G
C3P47
O
15
14
13
3
3
I
G
I
G
1
2
1
2
VCC
GND
Y0
Y1
Y2
Y3
+3.3V
1
2
1
2
+3.3V
1
2
1
2
+3.3V
1
2
74LVC139
G
A
B
+3.3V
1
2
U21B
0.01uF
O
0.1uF
C3P42
O
C3P41
0.01uF
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
3
3
3
3
3
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
16
8
12
11
10
9
/DBCS
/WE
/RAS
/CAS1
/CAS0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
U22
WE
OE
RAS
LCAS
UCAS
NC
NC
NC
NC
NC
NC
NC
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VSS
VSS
VSS
VCC
VCC
VCC
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
/CONFIG
MSM51V18165D/DSL-TSOP
17
33
18
35
34
11
15
16
19
20
36
40
32
31
30
29
28
27
24
23
22
21
26
45
50
1
6
25
49
48
47
46
44
43
42
41
10
9
8
7
5
4
3
2
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
3
3
3
3
3
3
I
G
I
G
I
G
I
G
I
G
0.01uF
O
0.1uF
C3P54
O
C3P53
0.01uF
O
0.1uF
C3P52
O
C3P51
0.01uF
O
0.1uF
C3P50
I
G
C3P49
O
+3.3V
1
2
1
2
+3.3V
1
2
1
2
+3.3V
1
2
1
2
/SRAM
/RD
/WR0
/WR1
/WR2
/WR3
/RST
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/DBINT
CON40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J1
HEADER 2
1
2
JP8
HEADER 3
1
2
3
JP7
HEADER 3
1
2
3
JP6
+3.3V
+3.3V
+3.3V
+3.3V
/EXTINTSB
HEADER 3
1
2
3
JP5
D[0..31]
R30
10K
R29
10K
R28
10K
R27
10K
R26
10K
R25
10K
R24
10K
CON40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J2
/STBY
D24
D25
D26
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+3.3V
D[0..31]
OKI Semiconductor
/ROM
/RD
A[0..23]
FEDL2110-01
ML2110
FEDL2110-01
OKI Semiconductor
ML2110
PACKAGE DIMENSIONS
(Unit: mm)
LQFP144-P-2020-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.37 TYP.
5/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
99/101
FEDL2110-01
OKI Semiconductor
ML2110
REVISION HISTORY
Document
No.
Date
Version 1
Dec. 2000
PEDL2110-01
Apr. 2001
FEDL2110-01
Mar. 25, 2002
Page
Previous Current
Edition
Edition
Description
–
–
Version 1
–
–
Preliminary first edition
3
3
6
6
7
7
8
8
9
9
12
12
13
13
71
70
–
96 to 98
Partially changed the pin configuration.
Changed as follows:
• The Max. value of Parameter “Dynamic
Supply Current” from 120 to 150 according to
a change of the condition.
• Symbol “|VDAE|” from VDAE to |VDAE|.
Changed the Min. and Max. values from 25 and
50 to 20 and 33, respectively, by a change of
Parameter “Source Oscillation Period” to
“Source Oscillation Frequency”.
Changed as follows:
• The Min. value of Parameter “Operating
Period” from 25 to 30.
• The Max. value of Parameter “A Delay Time”
from 22 to 29.
• The Min. value of Parameter “D Setup Time”
from 2 to 10.
• The Min. value of Parameter “D Hold Time”
from 6 to 2.
• The Max. value of Parameter “D Delay Time”
from 25 to 32.
• The Min. value of Parameter “RD Delay Time”
from 20 to 25.
• The Max. value of Parameter “UPORT Delay
Time” from 20 to 23.
Changed the Max. values of Parameters “ROM
Delay Time” and “SRAM Delay Time” from 20 +
0.5 tCYC to 21 + 0.5 tCYC.
Changed as follows:
• The Max. value of Parameter “RAS Delay
Time” from 18 to 24.
• The Max. value of Parameter CAS Delay
Time” from 18 + 0.5 tCYC to 22 + 0.5 tCYC and
from 18 to 22.
• The Max. value of Parameter “WE Delay
Time” from 20 to 23.
Changed the Max. Value of Parameter “AS
Delay Time” from 18 to 27.
Changed as follows:
• The Max. value of Parameter “RTS Delay
Time” from 20 to 22
• The Max. value of Parameter “TXD Delay
Time” from 20 to 21.
• The Max. value of Parameter “DTR Delay
Time” from 20 to 23
Added Note.
Changed the field names in the MCMD register
of Section 3.7.
Added the circuit diagrams.
100/101
FEDL2110-01
OKI Semiconductor
ML2110
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
101/101