19-2125; Rev 2; 7/03 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface Features ♦ Ultra-Low Power Consumption 112µA at VDD = +3.6V 135µA at VDD = +5.5V The 20MHz, 3-wire SPI™, QSPI™, MICROWIRE™ and DSP-compatible serial interface saves board space and reduces the complexity of opto- and transformerisolated applications. The MAX5721 on-chip power-on reset (POR) circuit resets the DAC outputs to zero and loads the output with a 100kΩ resistor to ground. This provides additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5721’s software-controlled powerdown reduces supply current to less than 0.3µA and provides software-selectable output loads (1kΩ, 100kΩ, or high impedance) while in power-down. The MAX5721 is specified over the -40°C to +125°C automotive temperature range ♦ Three Software Selectable Power-Down Impedances (100kΩ, 1kΩ, Hi-Z) ♦ Wide +2.7V to +5.5V Single-Supply Range ♦ Tiny 8-Pin µMAX Package ♦ 0.3µA Power-Down Current ♦ Guaranteed 10-Bit Monotonicity (±1LSB DNL) ♦ Safe Power-Up Reset to Zero Volts at DAC Output ♦ Fast 20MHz, 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface ♦ Rail-to-Rail Output Buffer Amplifiers ♦ Schmitt-Triggered Logic Inputs for Direct Interface to Optocouplers ♦ Wide -40°C to +125°C Operating Temperature Range Applications Automatic Tuning Ordering Information PART TEMP RANGE PIN-PACKAGE Gain and Offset Adjustment MAX5721EUA -40°C to +85°C 8 µMAX Power Amplifier Control MAX5721AUA -40°C to +125°C 8 µMAX Process Control I/O Boards Battery-Powered Instruments VCO Control Pin Configuration TOP VIEW Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. VDD 1 8 OUTB GND 2 7 OUTA 3 6 REF SCLK 4 5 DIN MAX5721 CS µMAX ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5721 General Description The MAX5721 dual 10-bit, low-power, buffered voltageoutput, digital-to-analog converter (DAC) is packaged in a space-saving 8-pin µMAX package (5mm ✕ 3mm). The wide supply voltage range of +2.7V to +5.5V and 112µA supply current accommodate low-power and low-voltage applications. DAC outputs employ on-chip precision output amplifiers that swing Rail-to-Rail®. The MAX5721’s reference input accepts a voltage range from 0 to VDD. In power-down the reference input is high impedance, further reducing the system’s total power consumption. MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V) Maximum Continuous Current Into Any Pin......................±50mA Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.6 mW/°C above +70°C) ............362mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature .....................................................+150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note 1) Resolution N 10 Intergral Nonlinearity Error INL (Note 2) Differential Nonlinearity Error DNL Guaranteed monotonic (Note 2) Zero-Code Error OE Code = 000 GE Code = 3FF hex ±0.5 0.4 Zero-Code Error Tempco Gain Error ±4 LSB ±1 LSB 1.5 % of FS ±3 % of FS 2.3 Gain-Error Tempco Power-Supply Rejection Ratio Bits PSRR Code = 3FF hex, ∆VDD = ±10% ppm/°C 0.26 ppm/°C 58.8 dB REFERENCE INPUT Reference Input Voltage Range VREF Reference Input Impedance RREF Reference-Down Reference Current 0 In operation 64 VDD 90 In power-down mode 2 In power-down mode (Note 3) 1 126 V kΩ MΩ 10 µA DAC OUTPUT Output Voltage Range No load (Note 4) DC Output Impedance Code = 200 hex 0.8 VDD = +3V 15 VDD = +5V 48 VDD = +3V 8 VDD = +5V 8 Short-Circuit Current Wake-Up Time Output Leakage Current 2 Power-down mode = output high impedance 0 VDD ±18 _______________________________________________________________________________________ V Ω mA µs nA 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are VDD = +5V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH VDD = +3V, +5V Input Low Voltage VIL VDD = +3V, +5V Input Leakage Current IIN Digital inputs = 0 or VDD 0.7 x VDD V ±0.1 Input Capacitance 0.3 x VDD V ±1 µA 5 pF 0.5 V/µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Voltage-Output Settling Time 100 hex to 300 hex (Note 5) 4 10 Digital Feedthrough All digital inputs from 0 to VDD 0.1 nV-s Digital-Analog Glitch Inpulse Major carry transition (code 1FF hex to code 200 hex) 12 nV-s DAC-to-DAC Crosstalk µs nV-s POWER REQUIREMENTS Supply Voltage Range VDD Supply Current with No Load IDD Power-Down Supply Current IDDPD 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 112 205 All digital inputs at 0 or VDD = 5.5V 135 215 All digital inputs at 0 or VDD = 5.5V 0.29 1 µA TYP MAX UNITS 20 MHz µA TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN SCLK Clock Frequency f SCLK 0 SCLK Pulse Width High tCH 25 ns SCLK Pulse Width Low tCL 25 ns CS Fall to SCLK Rise Setup Time tCSS 10 ns SCLK Fall to CS Rise Setup Time ns tCSH 10 DIN to SCLK Fall Setup Time tDS 15 ns DIN to SCLK Fall Hold Time tDH 0 ns tCSW 80 ns CS Pulse Width High Note 1: Note 2: Note 3: Note 4: Note 5: DC specifications are tested without output loads. Linearity guaranteed from code 29 to code 995. Limited with test conditions. Offset and gain error limit the FSR. Guaranteed by design. _______________________________________________________________________________________ 3 MAX5721 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (VREF = VDD, TA = +25°C, unless otherwise noted.) 0.20 0.15 2 0.10 DNL (LSB) 0 -1 VDD = +5V -0.05 -0.15 -3 -4 -9 -14 VDD = +3V AND +5V -19 -0.20 -24 -0.25 -4 256 512 768 1024 0 256 512 768 0 1024 256 512 768 CODE CODE CODE INTEGRAL NONLINEARITY vs. CODE, TA = +40°C DIFFERENTIAL NONLINEARITY vs. CODE, TA = -40°C TOTAL UNADJUSTED ERROR vs. CODE, TA = -40°C 0.15 2 0.10 VDD = +5V DNL (LSB) 1 0 -1 VDD = +3V 0.05 0 -0.05 -0.10 -2 -0.15 -3 1 1024 MAX5721 toc06 3 0.20 TOTAL UNADJUSTED ERROR (%) 0.25 MAX5721 toc04 4 MAX5721 toc05 0 -4 VDD = +3V AND +5V -9 -14 -19 -0.20 -0.25 -4 256 512 768 -24 0 1024 256 512 768 0 1024 256 512 768 CODE CODE CODE INTEGRAL NONLINEARITY vs. CODE, TA = +125°C DIFFERENTIAL NONLINEARITY vs. CODE, TA = +125°C TOTAL UNADJUSTED ERROR vs. CODE, TA = +125°C 0.25 MAX5721 toc07 4 3 0.20 0.15 2 0.10 VDD = +3V DNL (LSB) 1 0 -1 VDD = +5V 0.05 0 -0.05 -0.10 -2 -0.15 -3 1 1024 MAX5721 toc09 0 TOTAL UNADJUSTED ERROR (%) INL (LSB) 0 -0.10 -2 -4 VDD = +3V AND +5V -9 -14 -19 -0.20 -24 -0.25 -4 0 256 512 CODE 4 0.05 MAX5721 toc08 INL (LSB) VDD = +3V 1 1 MAX5721 toc03 3 TOTAL UNADJUSTED ERROR vs. CODE, TA = +25°C MAX5721 toc02 0.25 MAX5721 toc01 4 DIFFERENTIAL NONLINEARITY vs. CODE, TA = +25°C TOTAL UNADJUSTED ERROR (%) INTEGRAL NONLINEARITY vs. CODE, TA = +25°C INL (LSB) MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface 768 1024 0 256 512 768 1024 0 256 CODE _______________________________________________________________________________________ 512 CODE 768 1024 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +3V) 2.5 0 -1 MINIMUM DNL 1.5 -2 -4 0 20 40 60 80 4 6 8 10 12 14 ISOURCE/SINK (mA) SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 100 80 60 40 20 16 0 2.7 3.2 3.7 4.2 4.7 MAX5721 toc14 250 200 150 100 10 12 14 16 700 600 VDD = +5V 500 400 300 VDD = +3V 100 0 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE FULL-SCALE SETTLING TIME (VDD = +5V) 0 1 2 3 4 5 CS INPUT VOLTAGE (V) FULL-SCALE SETTLING TIME (VDD = +5V) MAX5721 toc17 MAX5721 toc16 140 8 200 SUPPLY VOLTAGE (V) 160 6 800 50 2.7 5.2 4 SUPPLY CURRENT vs. CS INPUT VOLTAGE 0 0 2 900 SUPPLY CURRENT (µA) CODE = 3FF HEX CODE = 000 SINKING CURRENT INTO OUT_ 0.5 ISOURCE/SINK (mA) 300 POWER-DOWN SUPPLY CURRENT (nA) MAX5721 toc13 120 CODE = 100 HEX, SINKING CURRENT INTO OUT_ 0 2 TEMPERATURE (°C) 140 SUPPLY CURRENT (µA) CODE = 000 SINKING CURRENT INTO OUT_ 0 100 120 160 SUPPLY CURRENT (µA) 1.5 0 -40 -20 CODE = 300 HEX, SOURCING CURRENT FROM OUT_ 2.5 1.0 0.5 -3 3.0 2.0 CODE = 100 HEX, SINKING CURRENT INTO OUT_ 1.0 MINIMUM INL 4.0 3.5 CODE = 300 HEX, SOURCING CURRENT FROM OUT_ 2.0 MAXIMUM INL CODE = 3FF HEX, SOURCING CURRENT FROM OUT_ 4.5 VOUT (V) MAXIMUM DNL 1 VOUT (V) INL AND DNL (LSB) 2 5.0 MAX5721 toc12 3 CODE = 3FF HEX, SOURCING CURRENT FROM OUT_ MAX5721 toc11 3.0 MAX5721 toc10 4 SOURCE-AND-SINK CURRENT CAPABILITY (VDD = +5V) MAX5721 toc15 WORST-CASE INL AND DNL vs. TEMPERATURE MAX5721 Typical Operating Characteristics (continued) (VREF = VDD, TA = +25°C, unless otherwise noted.) MAX5721 toc18 VSCLK 5V/div VSCLK 5V/div VOUT_ 1V/div VOUT_ 1V/div VDD = +5.5V 120 100 VDD = +3.6V 80 60 40 CODE 000 TO 3FF HEX RL = 5kΩ CL = 200pF 20 CODE 3FF HEX TO 000 RL = 5kΩ CL = 200pF 0 -40 -20 0 20 40 60 80 100 120 1µs/div 1µs/div TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface Typical Operating Characteristics (continued) (VREF = VDD, TA = +25°C, unless otherwise noted.) HALF-SCALE SETTLING TIME (VDD = +3V) HALF-SCALE SETTLING TIME (VDD = +3V) MAX5721 toc19 MAX5721 toc20 VSCLK 5V/div VSCLK 5V/div VOUT_ 1V/div VOUT_ 1V/div CODE 300 HEX TO 100 HEX RL = 5kΩ CL = 200pF CODE 100 HEX TO 300 HEX RL = 5kΩ CL = 200pF 1µs/div 1µs/div EXITING POWER-DOWN (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) MAX5721 toc22 MAX5721 toc21 VSCLK 5V/div CODE 200 HEX VOUT_ 1V/div CODE 1FF HEX TO 200 HEX 5µs/div 1µs/div DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +5V) MAX5721 toc23 CODE 1FF HEX TO 200 HEX 1µs/div 6 SCLK, fSCLK = 500kHz 2V/div VOUT_ AC-COUPLED, 20mV/div MAX5721 toc24 SCLK, fSCLK = 500kHz, 2V/div SCLK, fSCLK = 500kHz, 2V/div VOUT_ AC-COUPLED, 50mV/div VOUT_ AC-COUPLED, 50mV/div CODE 200 HEX TO 1FF HEX 1µs/div _______________________________________________________________________________________ 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface POWER-ON RESET, FAST RISE TIME (VDD = +5V) DIGITAL-TO-ANALOG GLITCH IMPULSE (VDD = +3V) MAX5721 toc26 MAX5721 toc25 SCLK, fSCLK = 500kHz, 1V/div CODE 200 HEX TO 1FF HEX VDD 2V/div VOUT_ AC-COUPLED, 20mV/div 20µs/div 1µs/div POWER-ON RESET, FAST RISE TIME (VDD = +3V) POWER-ON RESET, SLOW RISE TIME (VDD = +5V) MAX5721 toc28 MAX5721 toc27 VDD RISE TIME = 76µs VDD 2V/div VDD 2V/div VDD RISE TIME = 20µs VOUT_ AC-COUPLED, 10mV/div VOUT_ AC-COUPLED, 2mV/div 20µs/div 40µs/div POWER-ON RESET, SLOW RISE TIME (VDD = +3V) CLOCK FEEDTHROUGH (VDD = +5V) MAX5721 toc30 MAX5721 toc29 VDD 2V/div SCLK, 2V/div VDD RISE TIME = 72µs VOUT_, AC-COUPLED 1mV/div VOUT_ AC-COUPLED, 2mV/div 40µs/div VOUT_ AC-COUPLED, 10mV/div VDD RISE TIME = 20µs 100ns/div fSCLK = 1MHz _______________________________________________________________________________________ 7 MAX5721 Typical Operating Characteristics (continued) ( VREF = VDD, TA = +25°C, unless otherwise noted.) MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface Typical Operating Characteristics (continued) ( VREF = VDD, TA = +25°C, unless otherwise noted.) LINE TRANSIENT RESPONSE (VDD = +5V) CLOCK FEEDTHROUGH (VDD = +3V) MAX5721 toc32 MAX5721 toc31 SCLK, 2V/div VDD, AC-COUPLED, 100mV/div VOUT_, AC-COUPLED 1mV/div VOUT_ AC-COUPLED, 10mV/div 20µs/div 100ns/div fSCLK = 1MHz LINE TRANSIENT RESPONSE (VDD = +3V) CROSSTALK (VDD = +5V) MAX5721 toc34 MAX5721 toc33 VDD, AC-COUPLED, 100mV/div VOUTA, 2V/div CODE 2FF HEX TO 008 HEX VOUTB, AC-COUPLED 1mV/div VOUT_ AC-COUPLED, 10mV/div 4µs/div 20µs/div Pin Description 8 PIN NAME 1 VDD Power-Supply Input FUNCTION 2 GND Ground 3 CS 4 SCLK Serial Clock Input 5 DIN Serial Data Input 6 REF External Reference Voltage Input 7, 8 OUTA, OUTB Chip-Select Input DAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connects OUT to GND with 100kΩ resistor. _______________________________________________________________________________________ 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface The MAX5721 contains two 10-bit, voltage-output, lowpower digital-to-analog converters (DACs). Each DAC employs a resistor string architecture that converts a 10-bit digital input word to an equivalent analog output voltage proportional to the applied reference voltage. The MAX5721 shares one reference input (REF) between both DACs. The MAX5721 includes rail-to-rail output buffer amplifiers for each DAC, and input logic for simple microprocessor (µP), and CMOS interfaces. The power-supply range is from +2.7V to +5.5V (Functional Diagram). The MAX5721’s reference input accepts a voltage range from 0 to VDD. In power-down mode the reference input is high impedance. The MAX5721 is compatible with the 3-wire SPI, QSPI, MICROWIRE, and DSP serial interface with Schmitt-triggered logic inputs. Reference Input and DAC Output Range The reference input accepts positive DC and AC signals. The voltage at REF sets the full-scale output voltage of both DACs. The reference input voltage range is 0 to VDD. The impedance at REF is 90kΩ. The voltage at REF can vary from GND to VDD. The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF ✕ D) / 210 where D is the decimal equivalent of binary DAC input code ranging from 0 to 1023. VREF is the voltage at REF. Output Buffer Amplifiers All DACs are internally buffered at the output. The buffer amplifiers have both rail-to-rail common mode and (GND to VREF) output voltage range. The buffers are unity-gain stable with CL = 200pF and RL = 5kΩ. Buffer amplifiers are disabled during power-up and individual DAC outputs are shorted to GND through a 100kΩ resistor. Buffer amplifiers can individually or altogether be powereddown by programming the input register control bits. During power down, contents of the input and DAC registers remain the same. On wake-up all DAC outputs are restored to their pre-power-down voltage values. Power-Down Mode In power-down mode, the DAC outputs are programmed to one of three output states, 1kΩ, 100kΩ, or floating (Table 1). The REF input is high impedance (2MΩ typ) to conserve current drain from the system reference; therefore, the system reference does not have to be powered-down. The DAC outputs return to the values contained in the registers when brought out of power-down. The recovery time, from total power- down to power-up, is 8µs. This extra time is needed to allow the internal bias to wake-up. Power-down mode reduces current consumption to 0.5µA. 3-Wire Serial Interface The MAX5721 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP interfaces. The chip-select input (CS) frames the serial data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and latched into the input register on the falling edge of the serial clock input (SCLK). After 16 bits have been loaded into the serial input register, it transfers its contents to the DAC latch. CS may then either be held low or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a write sequence is initiated on a falling edge of CS. Not keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle either high or low between transitions. The MAX5721 has two internal registers per DAC, the input register and the DAC register. The input register holds the data that is waiting to be shifted to the DAC register. Both input registers can be loaded without updating the output. This function is useul when both outputs need to be updated at the same time. The input register can be made transparent. When the input register is transparent, the data written into DIN loads directly to the DAC register and the output is updated. The DAC output is not updated until data is written to the DAC register. See Table 2 for a list of serial-interface programming commands. Power-On Reset (POR) The MAX5721 has an internal POR circuit. At power-up all DACs are powered-down and OUT_ is terminated to GND through 100kΩ resistors. Contents of input and DAC registers are cleared to all zero. An 8µs recovery time after issuing a wake-up command is needed before writing to the DAC registers. Power-down mode control commands can be applied immediately with no recovery time. C3-C0 are control bits. The data bits D9 to D0 are in straight binary format. Set bits S1 and S0 to zero. All zeros correspond to zero scale and all ones correspond to full scale. Digital Inputs The digital inputs are compatible with CMOS logic. In order to save power and reduce input to output coupling, SCLK and DIN input buffers are powered down immediately after completion of shifting 16 bits into the input shift register. A high to low transition at CS powers up SCLK and DIN input buffers. _______________________________________________________________________________________ 9 MAX5721 Detailed Description MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface Table 1. Power-Down Mode Control EXTENDED CONTROL DATA BITS DESCRIPTION FUNCTION C3 C2 C1 C0 D9–D3 D2 D1 D0 S1 S0 1 1 1 1 X 0 0 0 0 0 DAC A DAC O/P, wake-up 1 1 1 1 X 0 0 0 0 1 DAC A Floating output 1 1 1 1 X 0 0 0 1 0 DAC A Output is terminated with 1kΩ 1 1 1 1 X 0 0 0 1 1 DAC A Output is terminated with 100kΩ 1 1 1 1 X 0 0 1 0 0 DAC B DAC O/P, wake-up 1 1 1 1 X 0 0 1 0 1 DAC B Floating output 1 1 1 1 X 0 0 1 1 0 DAC B Output is terminated with 1kΩ 1 1 1 1 X 0 0 1 1 1 DAC B 1 1 1 1 X 1 0 0 0 0 DAC A-B DAC O/P, wake-up 1 1 1 1 X 1 0 0 0 1 DAC A-B Floating output 1 1 1 1 X 1 0 0 1 0 DAC A-B Output is terminated with 1kΩ 1 1 1 1 X 1 0 0 1 1 DAC A-B Output is terminated with 100kΩ Output is terminated with 100kΩ X = Don’t Care CONTENTS OF INPUT SHIFT REGISTER D15 (MSB) C3 C2 D0 (LSB) C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 1. 16-Bit Input Word tCH SCLK tCL tCSW tCSS tCSH tDH tDS CS DIN C3 SO Figure 2. Timing Diagram 10 ______________________________________________________________________________________ S1 S0 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface CONTROL DATA BITS DAC FUNCTION C3 C2 C1 C0 D9–D0 S1–S0 0 0 0 0 X X A Input register transparent, data shifted directly to DAC register, OUTA updated 0 0 0 1 X X B Input register transparent, data shifted directly to DAC register, OUTB updated 0 1 0 0 X X A Data shifted to input register, OUTA unchanged 0 1 0 1 X X B Data shifted to input register, OUTB unchanged 1 0 0 0 X X A Shift data from input register to DAC register, OUTA updated 1 0 0 1 X X B Shift data from input register to DAC register, OUTB updated 1 1 0 0 X X A-B Input registers transparent, data shifted directly to DAC registers, OUTA and OUTB updated 1 1 0 1 X X A-B Data shifted to input registers, OUTA and OUTB unchanged 1 1 1 0 X X A-B Shift data from input registers to DAC registers, OUTA and OUTB updated X = Don’t Care Applications Information Unipolar Output The typical application circuit (Figure 3) shows the MAX5721 configured for a unipolar output, where the output voltages and the reference inputs have the same polarity. Table 3 lists the unipolar output codes. Bipolar Output The MAX5721 can be configured for bipolar operation using a dual supply op amp (Figure 4). The transfer function for bipolar operation is: where DB is the decimal value of the DACs binary input code. Table 4 shows digital codes (offset binary) and corresponding output voltages for the circuit in Figure 4. Power Supply and Layout Considerations Careful PC board layout is important for optimal system performance. To reduce noise injection and digital feedthrough, keep analog and digital signals separate. Ensure that that the return path from GND to the supply ground is short and low impedance. Use a ground plane. Bypass VDD to GND with a 0.1µF capacitor as close as possible to VDD. 2D VOUT = VREF − 1 1024 R1 +2.7V to +5.5V R2 V+ +2.7V to +5.5V VDD REF VDD REF VOUT OUT IN OUT_ DAC_ OUT_ DAC_ MAX6050 V- GND GND MAX5721 Figure 3. Typical Operating Circuit, Unipolar Output GND MAX5721 R1 = R2 Figure 4. Bipolar Output Circuit ______________________________________________________________________________________ 11 MAX5721 Table 2. Serial-Interface Programming Commands MAX5721 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface Table 3. Unipolar Code Table Table 4. Bipolar Code Table DAC CONTENTS ANALOG OUTPUT DAC CONTENTS ANALOG OUTPUT 1111 1111 1100 1023 + VREF 1024 1111 1111 1100 511 + VREF 512 1000 0000 0100 513 + VREF 1024 1000 0000 01000 1 + VREF 512 1000 0000 0000 0 1000 0000 0000 V + REF 2 0111 1111 11100 − VREF 511 + VREF 1024 0000 0000 0100 − VREF 0111 1111 1100 0000 0000 0100 1 + VREF 1024 0000 0000 0000 0 1 512 0000 0000 0000 Chip Information TRANSISTOR COUNT: 7737 PROCESS: BiCMOS 12 ______________________________________________________________________________________ 511 512 − VREF 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface VDD REF INPUT REGISTER A DAC REGISTER B 10-BIT DAC A OUTPUT BUFFER OUTA RESISTOR NETWORK INPUT REGISTER B DAC REGISTER B 10-BIT DAC B OUTPUT BUFFER OUTB RESISTOR NETWORK INPUT CONTROL LOGIC AND SHIFT REGISTER POWER-DOWN CONTROL LOGIC MAX5721 CS SCLK DIN GND ______________________________________________________________________________________ 13 MAX5721 Functional Diagram 10-Bit, Low-Power, Dual, Voltage-Output DAC with Serial Interface 8 INCHES DIM A A1 A2 b E ÿ 0.50±0.1 H c D e E H 0.6±0.1 L 1 1 α 0.6±0.1 S BOTTOM VIEW D MIN 0.002 0.030 MAX 0.043 0.006 0.037 0.010 0.014 0.005 0.007 0.116 0.120 0.0256 BSC 0.116 0.120 0.188 0.198 0.016 0.026 6∞ 0∞ 0.0207 BSC 8LUMAXD.EPS 4X S 8 MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95 0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0∞ 6∞ 0.5250 BSC TOP VIEW A1 A2 A α c e b L SIDE VIEW FRONT VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 8L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0036 REV. J 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5721 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)