CMX991/CMX992 CML Microcircuits COMMUNICATION SEMICONDUCTORS RF Quadrature Transceiver and RF Quadrature Receiver D/991_992/7 May 2009 Advance Information This document describes two separate, high performance, RF ICs covering the range: 100MHz to 1GHz. The CMX991 is an RF Quadrature Transceiver and the CMX992 is an RF Quadrature Receiver. Features Applications • • • • • • • • • • 1 Rx (CMX991 and CMX992) o RF mixer with output select o 1st IF input select o Selectable low IF outputs (450kHz/455kHz) o 1st IF Variable Gain Amplifier (VGA) o 1st IF Signal Level Indicator (SLI) o Two-mode demodulator o I/Q Zero-IF with differential outputs Tx (CMX991 only) o I/Q modulator to IF o Image-reject up-converter o IF and RF outputs IF (CMX991 and CMX992) o IF LO synthesiser o IF VCO negative resistance amplifier 3.3V low power operation • • • • • • • Analogue/digital multimode radio Software Defined Radio (SDR) Portable, mobile and base station terminals Data telemetry modems TETRA (CMX992) ETSI: EN 300 113, EN 301 166, EN 302 561, EN 300 220, TS 102 361 (DMR) Automatic Identification System (AIS) transponders Constant envelope and linear modulation Compatible with CMX998 (CMX992 only) Narrowband: e.g. 25kHz, 12.5kHz, 6.25kHz Wideband: up to 2MHz APCO Project 25 (P25) Phase 1 and Phase 2 TDMA: TIA-102.CAAB Satellite communications Brief Description The CMX991 is a single-chip, high performance, RF transceiver that provides the core functions required to implement a full-featured radio transmitter and receiver. It operates from 100MHz to 1GHz and its I/Q architecture supports multiple modulation types and bandwidths with a single radio design. The half-duplex CMX991 integrates Tx modulators, Rx demodulators, IF PLL and IF VCO subsystems to minimise the external circuits needed when implementing a complete transceiver. User-selected modes suit different application requirements. The Tx path includes an I/Q modulator to accurately generate modulation at the IF frequency, which may then be translated to the final RF frequency by an integrated image-reject up-converter system. The I/Q modulator IF output is also made available for conversion to RF via external circuits, if desired. The Rx path includes an integrated 1st Rx mixer having two outputs to support two external 1st IF filter choices, then an integrated 2:1 input mux followed by VGA and wideband signal level measurement functions, to support AGC implementation. The 1st IF signal is then either I/Q demodulated to Zero-IF or mixed to a Low IF output. The CMX991 provides differential and single-ended Rx output options and differential amplifiers for flexible signal conditioning. The CMX992 is a single-chip, high performance, RF receiver that includes the core RF and IF receive functions of the CMX991 above and can be used in a wide range of narrowband and wideband wireless products, including multi-mode analogue/digital terminals. The CMX991/CMX992 can be used where highly linear modulations are being used, e.g. for applications such as TETRA, where a typical transmitter solution would include the CMX998 Cartesian Feedback Transmitter. Both devices operate from a single 3.3V supply over a temperature range of -40°C to +85°C and are available in 48-pin VQFN (Q3) packages. © 2009 CML Microsystems Plc RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 IF Output Tx I/Q Input T/R Power Amplifier Differential Amplifiers Div (VC)TCXO Integer-N PLL LO Input Power Supply External Resonator & Varactors Control Registers C-BUS LO Input /4 Div CMX991 LNA Rx Lev 2 x IF (e.g 455kHz) Outputs or IQ Outputs IF Filters Figure 1 CMX991 – RF Quadrature Transceiver Integer-N PLL Power Supply Differential Amplifiers External Resonator & Varactors Control Registers C-BUS LO Input /4 Div CMX992 T/R SLI From Transmitter 2 x IF (e.g 455kHz) Outputs or IQ Outputs IF Filters Figure 2 CMX992 – RF Quadrature / Low IF Receiver © 2009 CML Microsystems Plc 2 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 CONTENTS Page Section 0H1 Brief Description .....................................................................................................3 1H1.1 History..............................................................................................................5 2H2 Block Diagrams ......................................................................................................6 3H3 Signal List...............................................................................................................7 4H3.1 Signal Definitions .............................................................................................8 5H4 External Components.............................................................................................9 6H4.1 Power Supply Decoupling ...............................................................................9 7H4.2 Receiver (CMX991 and CMX992) .................................................................10 8H4.3 Transmitter (CMX991 only) ...........................................................................14 9H4.4 Main Local Oscillator .....................................................................................15 10H4.5 IF Local Oscillator (CMX991 and CMX992) ..................................................16 11H5 General Description .............................................................................................18 12H5.1 Overview ........................................................................................................18 13H5.2 Receiver.........................................................................................................18 14H5.3 Transmitter (CMX991 only) ...........................................................................20 15H5.4 Local Oscillators ............................................................................................21 16H5.5 VBIAS ............................................................................................................22 17H5.6 Data Interface ................................................................................................22 18H6 C-BUS Interface and Register Description ..........................................................23 19H6.1 General Reset Command (CMX991/CMX992) .............................................25 20H6.2 General Control Register (CMX991/CMX992) ..............................................25 21H6.3 Rx Control Register (CMX991/CMX992).......................................................26 22H6.4 Rx Mode Register (CMX991/CMX992) .........................................................27 23H6.5 Tx Control Register (CMX991 only)...............................................................28 24H6.6 Tx Mode Register (CMX991 only) .................................................................29 25H6.7 Tx Gain Register (CMX991 only)...................................................................29 26H6.8 IF PLL M Divider (CMX991/CMX992) ...........................................................30 27H6.9 PLL N Divider (CMX991/CMX992) ................................................................31 28H7 Application Notes .................................................................................................32 29H7.1 General ..........................................................................................................32 30H7.2 Using the CMX992 with the CMX998 ............................................................32 31H7.3 Typical Gain Distribution................................................................................32 32H7.4 IF Output Matching ........................................................................................32 33H7.5 IF Input Matching ...........................................................................................33 34H7.6 Signal Level Indicator (SLI) ...........................................................................33 35H7.7 Receiver Spurious Rejection Performance ...................................................34 36H7.8 Modulation Accuracy .....................................................................................35 37H8 Performance Specification ...................................................................................37 38H8.1 Electrical Performance ..................................................................................37 39H8.2 Packaging ......................................................................................................45 Table Table 1 Table 2 Table 3 Table 4 Table 5 Page Pin List................................................................................................................... 8 Definition of Power Supply and Reference Voltages ............................................8 Decoupling Components.......................................................................................9 Typical Rx 1st Mixer Input Matching Components for 455MHz...........................10 1st IF Filtering Components for 45MHz ...............................................................12 © 2009 CML Microsystems Plc 3 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 Table 6 Rx I/Q Differential to Single Ended Amplifier Components.................................12 Table 7 Rx Low IF (455kHz) Components.......................................................................13 Table 8 Transmitter Components ....................................................................................14 Table 9 I/Q Modulator Output Matching Components .....................................................15 Table 10 Rx LO Input Components .................................................................................15 Table 11 IF VCO LO Internal VCO Amplifier Tank Circuit for 180MHz Operation .......... 17 Table 12 IF LO 3rd Order Loop Filter Circuit for 180MHz Operation................................17 Table 13 Typical Receiver Gain Partitioning....................................................................32 Table 14 Noise Figure and Gain of IF Amp, VGA, I/Q Mixer and Baseband Filters........ 33 Table 15 Symbol/Error Table for the Tx with 9.6kbps GMSK from an EV9100...............36 Figure Page Figure 1 CMX991 – RF Quadrature Transceiver...............................................................2 Figure 2 CMX992 – RF Quadrature / Low IF Receiver......................................................2 Figure 3 CMX991 Block Diagram ......................................................................................6 Figure 4 CMX992 Block Diagram ......................................................................................6 Figure 5 Recommended Power Supply Connections and Decoupling.............................. 9 Figure 6 Example External Components – Receive 1st Mixer Input ................................10 Figure 7 Example External Components – Receive 1st IF Section ..................................11 Figure 8 Example External Components – Receive I/Q Output ......................................12 Figure 9 Example External Components – Receive Low IF Output ................................13 Figure 10 Example External Components – Transmitter.................................................14 Figure 11 Example External Components – I/Q Modulator Output .................................15 Figure 12 Example External Components – Rx LO Input................................................15 Figure 13 Example External Components – IF LO VCO External Tank Circuit............... 16 Figure 14 Example External Components – IF LO Loop Filter ........................................17 Figure 15 DC Offset Calibration Mode.............................................................................19 Figure 16 CMX991 Transmitter Architecture ...................................................................20 Figure 17 CMX991/CMX992 IF Local Oscillator ..............................................................21 Figure 18 C-BUS Transactions ........................................................................................24 Figure 19 Typical SLI Performance .................................................................................33 Figure 20 Typical SLI Performance in an Application Circuit (EV9920B)........................34 Figure 21 IF Output Response with and without blocking signal present........................35 Figure 22 Tx Output with 9.6kbps GMSK from an EV9100 .............................................36 Figure 23 C-BUS Timing ..................................................................................................44 Figure 24 Q3 Mechanical Outline: ...................................................................................45 © 2009 CML Microsystems Plc 4 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 1.1 CMX991/CMX992 History Version 6 7 Changes • Original published document for both the CMX991 and CMX992 devices. • Updated with enhanced application information. Date Mar 2009 May 2009 It is always recommended that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com]. Note: This is Advance Information; changes and additions will be made to this specification. Items marked TBD or left blank will be included in later issues. Items which are highlighted or greyed out should be ignored. These will be clarified in later issues of this specification. © 2009 CML Microsystems Plc 5 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver TXOUTN TXOUTP TXLON TXLOP Block Diagrams TXIFOUT 2 CMX991/CMX992 Divide by 2 or 4 TXIP TXIN TXQP TXQN Select VDDIO FREF DVDD DOIF Control Registers Interger-N PLL NRESET RDATA Limiting VCO Amp External Resonator & Varactors C-BUS VCON VCOP MIXLON Divide by 2 or 4 Enable DGND VCC_SYNTH LNA Control LNAON MIXLOP SCLK CDATA CSN Divide by 4 Divide by 4, 2 or 1 VCC_IF Power Supply Select / Bypass VCC_RF sin VBIAS MIXINP AGND MIXINN cos IAMPN QAMPO RXIN RXIP QAMPN RXQN RXQP QAMPP IAMPO SLI IFP2 IFINN MIXOUT1 MIXOUT2 IFP1 SLI Figure 3 CMX991 Block Diagram VDDIO FREF DVDD DOIF Control Registers Integer-N PLL NRESET RDATA Limiting VCO Amp External Resonator & Varactors C-BUS VCON VCOP Enable MIXLON DGND VCC_SYNTH LNAON MIXLOP SCLK CDATA CSN LNA Control Divide by 4 Divide by 4, 2 or 1 Power Supply Select / Bypass sin VCC_IF VCC_RF VBIAS MIXINP AGND MIXINN cos IAMPN RXIN RXIP IAMPP QAMPO QAMPP RXQN RXQP QAMPN IAMPO SLI IFINN IFP2 IFP1 MIXOUT2 MIXOUT1 SLI Figure 4 CMX992 Block Diagram © 2009 CML Microsystems Plc 6 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 3 CMX991/CMX992 Signal List Package Q3 Pin No. 1 Signal Name (CMX991) Signal Name (CMX992) Signal Type VCC_IF VCC_IF Power O/P 2 TXOUTP NC 3 TXOUTN NC 4 NC NC NC 5 NC NC NC 6 TXLON NC 7 TXLOP NC 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 MIXINN MIXINP MIXLON MIXLOP VCC_RF MIXOUT1 MIXOUT2 IFIP1 IFIP2 IFINN SLI RXQN RXQP QAMPP QAMPN QAMPO RXIN RXIP IAMPP IAMPN IAMPO DGND MIXINN MIXINP MIXLON MIXLOP VCC_RF MIXOUT1 MIXOUT2 IFIP1 IFIP2 IFINN SLI RXQN RXQP QAMPP QAMPN QAMPO RXIN RXIP IAMPP IAMPN IAMPO DGND I/P I/P I/P I/P Power O/P O/P I/P I/P I/P O/P O/P O/P I/P I/P O/P O/P O/P I/P I/P O/P Power 30 CSN CSN I/P 31 RDATA RDATA T/S 32 SCLK SCLK I/P 33 CDATA CDATA I/P 34 35 36 NRESET DVDD VDDIO NRESET DVDD VDDIO I/P Power Power NC O/P NC I/P NC I/P © 2009 CML Microsystems Plc NC 7 Description Supply for IF circuits CMX991: Tx section positive output CMX992: Do not connect to this pin, reserved for future use CMX991: Tx section positive output CMX992: Do not connect to this pin, reserved for future use Do not connect to this pin, reserved for future use Do not connect to this pin, reserved for future use CMX991: Tx local oscillator negative input CMX992: Do not connect to this pin, reserved for future use CMX991: Tx local oscillator positive input CMX992: Do not connect to this pin, reserved for future use Rx mixer negative input Rx mixer positive input Rx mixer local oscillator negative input Rx mixer local oscillator positive input Supply for RF circuits Rx mixer output 1 Rx mixer output 2 Rx IF positive input 1 Rx IF positive input 2 Rx IF negative input Receiver Signal Level Indicator (SLI) output RxQ negative output RxQ positive output RxQ amplifier positive input RxQ amplifier negative input Low IF output or RxQ amp output RxI negative output RxI positive output RxI amplifier positive input RxI amplifier negative input RxI amplifier output Digital ground C-BUS chip select (active low), used to enable a C-BUS data read or write operation on the chip C-BUS serial data 3-state output (reply data) to host C-BUS clock input from the host C-BUS serial data input (command data) from the host C-BUS reset (low for reset condition) Supply to digital circuits Supply to C-BUS circuits D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Package Q3 Pin No. 37 38 39 40 41 42 Signal Name (CMX991) LNAON VCC_SYNTH FREF DOIF VCOP VCON Signal Name (CMX992) LNAON VCC_SYNTH FREF DOIF VCOP VCON CMX991/CMX992 Signal Type Description O/P Power I/P O/P I/P I/P Control line to enable/disable Rx LNA Supply to IF integer N PLL Reference frequency input IF PLL charge pump output IF PLL VCO positive input IF PLL VCO negative input Bandgap generated bias voltage – 43 VBIAS VBIAS O/P measurement output I/P CMX991: TxQ negative input 44 TXQN NC CMX992: Do not connect to this pin, reserved NC for future use I/P CMX991: TxQ positive input 45 TXQP NC CMX992: Do not connect to this pin, reserved NC for future use I/P CMX991: TxI negative input 46 TXIN NC CMX992: Do not connect to this pin, reserved NC for future use I/P CMX991: TxI positive input 47 TXIP NC CMX992: Do not connect to this pin, reserved NC for future use O/P CMX991: Tx IF output 48 TXIFOUT NC CMX992: Do not connect to this pin, reserved NC for future use The exposed metal pad must be electrically EXPOSED AGND AGND Power METAL PAD connected to analogue ground Total = 49 Pins (48 pins and central, exposed metal ground pad) Table 1 Pin List I/P = Input O/P = Output 3.1 T/S = 3-state NC = Not Connected Signal Definitions Signal Name AVDD DVDD VDDIO Pins VCC_IF, VCC_RF, VCC_SYNTH DVDD VDDIO VBIAS VBIAS DVSS AVSS DGND AGND Usage Power supply for analogue circuits. Power supply for digital circuits. Power supply voltage for digital interface (C-BUS). Bandgap generated bias voltage used as a reference for differential amplifier stages. Decoupling is optional but, if used, a capacitor of >200nF should be connected between VBIAS and AVSS. Ground for digital circuits. Ground for analogue circuits. Table 2 Definition of Power Supply and Reference Voltages © 2009 CML Microsystems Plc 8 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4 External Components 4.1 Power Supply Decoupling CMX991/CMX992 The CMX991/CMX992 has separate supply pins for the analogue and digital circuitry: a 3.3V nominal supply is recommended for all circuits but a different voltage for VDDIO may be used (see section 5.6). DVDD DVDD R5 VDDIO R4 VCC_RF R3 AVDD VCC_IF R2 VCC_SYNTH R1 C5 C4 C3 C2 C1 GND Plane for: AGND GND GND for: DGND Figure 5 Recommended Power Supply Connections and Decoupling C1 C2 C3 C4 C5 10nF 10nF 10nF 10nF 10nF R1 R2 R3 R4 R5 3.3 Ω 3.3 Ω 3.3 Ω 10 Ω 10 Ω Table 3 Decoupling Components Notes: 1. Maximum Tolerances: Resistors ±5%, capacitors ±20% unless otherwise stated 2. It is expected that any low frequency interference on the 3.3 Volt supply will be removed by active regulation; a large capacitor is an alternative but may require more board space and so may not be preferred. It is particularly important to ensure that there is no interference from the VDDIO (which supplies the digital I/O) or from any other circuit that may use the DVDD supply (such as a microprocessor), to sensitive analogue supplies (AVDD). It is therefore advisable to use separate power supplies for the digital and analogue circuitry. 3. The supply decoupling shown is intended for RF noise suppression. It is necessary to have a small series impedance prior to the decoupling capacitor for the decoupling to work well; this may be cost effectively done with the resistor and capacitor values shown. The use of resistors results in small DC voltage drops (up to approx 0.1V). Choosing resistor values approximately inversely proportional to the DC current requirements of each supply ensures the DC voltage drop on each supply are reasonably matched. In any case, the DC voltage change that results is well within the design tolerance of the device. If higher impedance resistors are used (not recommended) then greater care will be needed to ensure the supply voltages are maintained within tolerance, even when parts of the device are enabled or disabled. 4. It is advisable to have separate ground planes for the analogue and digital circuits. © 2009 CML Microsystems Plc 9 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4.2 CMX991/CMX992 Receiver (CMX991 and CMX992) The receiver relies on an external LNA, filtering and a Transmit/Receive switch; details can be found in section 5.2. 4.2.1 Rx 1st Mixer The Rx 1st Mixer has a differential input with a nominal impedance of 300Ω. To ensure optimum performance a balun is required when driving from typical single-ended (un-balanced) LNAs or filters. The balun may be a transformer type or implemented using LC networks. A typical matching circuit to the Rx 1st Mixer is shown in Figure 6. CMX991 CMX992 R1 L1 C3 Input MIXINP T1 L2 C4 MIXINN R2 Figure 6 Example External Components – Receive 1st Mixer Input L1 C3 C4 27nH 1nF 1nF L2 T1 R1 and R2 33nH TC1-1-13M+ NF Table 4 Typical Rx 1st Mixer Input Matching Components for 455MHz © 2009 CML Microsystems Plc 10 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4.2.2 CMX991/CMX992 Rx 1st IF Filtering The output of the CMX991/CMX992 first receive mixer can be switched between MIXOUT1 and MIXOUT2 to support two different external 1st IF filters for different receiver operating modes. The IF output should be in the range 10MHz to 150MHz. The integrated IF amplifier that follows external 1st IF filters has two switchable inputs. It is recommended that an IF filter (e.g. crystal or SAW type) be placed between the mixer output and IF amplifier input stages to protect the IF amplifier and subsequent stages from off-channel signals. Matching arrangements will vary with the particular filter used however an example of a typical configuration for a 45MHz IF is given in Figure 7. The configuration shown only utilises one possible combination of the two 1st Mixer outputs and two IF amplifier inputs; the other input and output (IFIP2 and MIXOUT2 respectively) could be configured to use a SAW filter or operate with a different IF frequency or bandwidth, for example. The MIXEROUT1 and MIXEROUT2 pins should have a DC blocking capacitor, as should the IF amplifier inputs IFIP1 and IFIP2. IFINN should be ac coupled to the IF filter ground. For additional information see section 5.2.2. CMX991 CMX992 MIXINN MIXINP IFIP1 MIXOUT2 C8 R2 MIXOUT1 C1 IFIP2 C6 IFINN C7 F1 L1 C5 C2 C3 C4 R1 L2 Figure 7 Example External Components – Receive 1st IF Section © 2009 CML Microsystems Plc 11 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver C1 C2 C3 C4 C5 C6 CMX991/CMX992 1nF 15pF 3.9pF // 4.7pF 4.7pF 22pF 1nF C7 C8 L1 L2 R1 R2 F1 1nF 18pF 1µH 1µH 1200Ω 220Ω 45G15B1 Table 5 1st IF Filtering Components for 45MHz 4.2.3 4.2.3.1 Rx Output I/Q Output Amplifiers The CMX991/CMX992 includes uncommitted differential amplifiers, which may be used to convert the differential I and Q output signals to a single ended output. A typical configuration of the amplifier on the Q channel (the I channel is identical) is shown in Figure 8. This circuit has a linear gain of 1.5 and is not optimum for rejection of common mode signals however in practice performance is generally satisfactory. Users should note that the gain and bandwidth of this stage can be adjusted by altering the component values and should be configured to suite a particular application. C1 R1 RXQN Pin19 QAMPP Pin 21 R2 RXQP Pin 20 QAMPO Pin 23 QAMP QAMPN Pin 22 R3 C2 Figure 8 Example External Components – Receive I/Q Output C1 C2 NF NF R1 R2 R3 10kΩ 10kΩ 10kΩ Table 6 Rx I/Q Differential to Single Ended Amplifier Components © 2009 CML Microsystems Plc 12 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4.2.3.2 CMX991/CMX992 Low IF Output The I/Q demodulator output bandwidth is a minimum of 1MHz (see section 8.1.3.2) so the output of each I and Q demodulator mixer can be configured to mix down to a low 2nd IF and use a demodulator output amplifier to provide gain. A typical configuration for the Q channel is shown in Figure 9. C2 R2 RXQP Pin 20 QAMPP VBIAS F1 Pin 21 C1 R1 QAMP R3 QAMPN QAMPO Pin 23 Pin 22 25k Ceramic Filter R4 C3 Figure 9 Example External Components – Receive Low IF Output C1 C2 C3 F1 100nF 47nF 33pF CFWL455KEFA-B0 R1 R2 R3 R4 1.5kΩ 1.5kΩ 1.5kΩ 4.7kΩ Table 7 Rx Low IF (455kHz) Components The components above specify a particular ceramic filter that would be used in a 25kHz channel Rx mode with an IF frequency of 455kHz. The other component values specified (e.g. R1, R3) are determined by the input/output impedance of the filter used. The filter and other components can be easily changed to allow for other bandwidths or any 2nd IF output up to 1MHz. A different external 2nd IF filter, of different bandwidth, could similarly be connected to the I channel output to support a second modulation bandwidth mode, e.g. to receive a 6.25kHz channel signal. The channel to be used is selectable via the general control register ($11), section 6.2. © 2009 CML Microsystems Plc 13 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4.3 Transmitter (CMX991 only) 4.3.1 Transmitter CMX991/CMX992 Details of the transmitter are contained in the Transmitter description, section 5.3. The components used around the CMX991 will depend on application requirements, however a typical configuration is shown in Figure 10. VCC_RF TXOUTP Tx Output R1 AVDD CMX991 C1 T1 TXOUTN VCC_RF Figure 10 Example External Components – Transmitter C1 R1 10nF (note 1) 3.3Ω T1 4:1 balun with centre tap (note 2) Table 8 Transmitter Components Notes: 1 2 3 4.3.2 Value of C1 is dependant on frequency of operation. At higher frequencies an additional low value decoupling capacitor in parallel (e.g. 33pF) may be required for optimum performance. C1 should be located as close to the centre tap of T1 as possible. Example component for T1 is Mini-Circuits TC4-14+. Additional components may be required at theT1 output for optimum match to 50Ω. IF I/Q Modulator Output The I/Q modulator can be used on its own, without the up-conversion mixers, by switching the I/Q modulator output to the output pin, TXIFOUT (pin 48) – see section 6.5. A typical configuration for this output is shown in Figure 11. © 2009 CML Microsystems Plc 14 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 CMX991 TXIP I Inputs TXIN IF LO 90° TXIFOUT + C1 I/Q Modulator Output TXIF Filter TXQP Q Inputs TXQN Figure 11 Example External Components – I/Q Modulator Output C1 1nF Table 9 I/Q Modulator Output Matching Components 4.4 Main Local Oscillator 4.4.1 Receiver LO Input (CMX991 and CMX992) The main local oscillator input is differential, but the normal configuration will be single ended, with the other input ac coupled to ground as shown in Figure 12. To prevent signals present on the local ground affecting the LO, the ground associated with capacitor C2 should be the same ground that is used for the LO source. In this way any ground noise will be common mode at the inputs A and B and will be rejected. CMX991 CMX992 C1 A LO Input Divider B C2 A = MIXLOP B = MIXLON Figure 12 Example External Components – Rx LO Input C1 1nF C2 1nF Table 10 Rx LO Input Components © 2009 CML Microsystems Plc 15 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 4.4.2 CMX991/CMX992 Transmitter LO Input (CMX991 only) Exactly the same configuration can be used for the CMX991 Tx LO input as for the receiver (Figure 12, Table 10). For the transmitter, ‘A’ in the diagram is pin TXLOP and ‘B’ is pin TXLON. 4.5 IF Local Oscillator (CMX991 and CMX992) A typical configuration for using the internal VCO negative resistance amplifier at 180MHz is shown in Figure 13. The other external components required to complete the PLL are the loop filter components, see Figure 14 – which shows a 3rd order loop filter, for which typical values are given in Table 12. CMX991 CMX992 Enable VCO Negative Resistance (NR) Amplifier VCO Output Buffer Amplifier Enable VCOP VCON L1 L1 should have a Q>30 C1 C2 C3 CV2 CV1 R1 R2 Input from Loop Filter Figure 13 Example External Components – IF LO VCO External Tank Circuit © 2009 CML Microsystems Plc 16 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver L1 C1 C2 C3 CMX991/CMX992 33nH (Note 1) 6.8 pF (Note 2) 27 pF 27 pF CV1 CV2 R1 R2 JDV2S08S JDV2S08S 10kΩ 10kΩ Note 1: Tolerance of 2% or better recommended Note 2: Tolerance of 5% or better recommended Table 11 IF VCO LO Internal VCO Amplifier Tank Circuit for 180MHz Operation DOIF (pin 40) Output to Tank Cct R2 C1 R1 C3 C2 Figure 14 Example External Components – IF LO Loop Filter C1 C2 C3 22nF 470nF 1nF R1 R2 430Ω 12kΩ Table 12 IF LO 3rd Order Loop Filter Circuit for 180MHz Operation © 2009 CML Microsystems Plc 17 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 5 General Description 5.1 Overview CMX991/CMX992 The CMX991/CMX992 are RF Quadrature Transceiver and Receiver ICs respectively. Each incorporates a superheterodyne receiver section along with IF local oscillator circuits. The CMX991 has an I/Q modulator with image-rejecting up-converter. The CMX991/CMX992 I/Q architecture supports a wide range of modulation types and various selectable functions maintain the performance across multiple modulations and bandwidths. The demodulator outputs are analogue signals with a quadrature (I/Q) Zero-IF signal format that simplifies connection to external ADCs. The receiver analogue signal interface also supports a low IF output mode. The transmitter interface is analogue I/Q format. Control of the CMX991/CMX992 is via the serial CBUS (see section 6). 5.2 Receiver The CMX991/CMX992 has a flexible multi-standard receiver designed to support multiple digital and analogue radio systems of both constant envelope and linear modulation types. It is expected that the applied input signal will have been amplified by an external Low Noise Amplifier (LNA). The user must determine the need for, and design of, any external image reject filtering. The CMX991/CMX992 design is optimised for an LNA gain of about 13dB 1. It is assumed there is some insertion loss prior to the LNA but an overall noise figure of 4dB and gain of 8dB (approx.) should be provided by the circuits preceding the CMX991/CMX992. A digital control signal is available from the chip, which can be used to enable/disable the LNA. Use of this signal is recommended as it simplifies I/Q calibration of dc-offsets. A differential input signal to the first mixer on the chip is recommended. The receiver architecture is a superheterodyne type with a 1st IF allowed in the range 10MHz to 150MHz, some typical 1st IFs being 10.7MHz, 21.4MHz, 45MHz, 70MHz and 150MHz. The CMX991/CMX992 provides a 1st down converter mixer with excellent linearity and noise figure. The design is intended to meet the challenging requirements of typical PMR/LMR radio systems. 5.2.1 Rx 1st Mixer and IF Filtering The Rx 1st Mixer has a differential input with a nominal impedance of 300Ω and nominal input frequency range of 100MHz to 1GHz. The 1st mixer has selectable LO input dividers: these are /1, /2 and /4 to allow common LO structures with the various Tx architectures, including use of the CMX998 with the transmitter. The mixer RF LO input is differential but the normal configuration is single ended with the other input ac coupled to ground (see section 4.4.1). The mixer has two selectable outputs to allow the connection of two different 1st IF filters, crystal or SAW type, that may be separately enabled under host control. The type of filter used is dependant on the application. The filter should provide rejection of blocking and intermodulation test tones for the subsequent IF stages. This 1st IF filter may also provide some useful adjacent channel filtering, but it is likely that the majority of the adjacent channel rejection will come in subsequent stages. 5.2.2 IF Variable Gain Amplifier (VGA) and I/Q Down-converter Mixer There are two selectable inputs to the IF amplifier, which is low noise and controlled through the C-BUS serial interface (See section 6). The inputs are differential with a common inverting input (pin IFINN) which should be decoupled locally to the ground plane used for the external IF elements. The IF inputs are high impedance (see section 8.1.3.2) and this allows straightforward matching to IF filter components. A typical configuration is shown in section 4.2.2, Figure 7 where the resistor R1 is used to define the resistive load for the filter. The 1 The precise gain will depend on application and is often a trade-off between intermodulation performance and receiver noise figure. See also section 7.3. © 2009 CML Microsystems Plc 18 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 suggested value of 390Ω can be varied depending on requirements, noting the trade-off between voltage gain and Q of the matching arrangements. The input impedance varies slightly with VGA setting but the effect of this is minimised by use of the terminating resistor R1. The variable gain may be adjusted by a host processor based on the measured Signal Level Indicator (SLI) value or on other criteria such as I/Q vector magnitude. The SLI output is an analogue output which is single ended and referenced to ground. Following the IF amplifier there is a pair of mixers that perform the final down-conversion either to an I/Q or low IF output. The I/Q demodulator has an output bandwidth of 1MHz which allows a low IF output of up to 1MHz; typical values may be 450kHz, 455kHz or 465kHz. 5.2.3 I/Q Filters The I/Q outputs include two filters that provide continuous time rejection to serve as anti-alias filters for external ADCs. The default filter will give an I/Q bandwidth of 1MHz. A narrower filter of 100kHz bandwidth is selectable to improve analogue rejection for narrow-band systems and guarantees image rejection for typical (e.g. sigma-delta) ADC solutions. Rx Mode Register ($13,b4) ‘Cal En’ = ‘1’. Acquire I/Q Offset CMX991 CMX992 Div MIXINN MIXINP Switch Circuitry disabled during Acquire I/Q DC Offset MIXOUT 1 MIXOUT 2 Figure 15 DC Offset Calibration Mode 5.2.4 DC Offset Correction The CMX991/CMX992 does not provide direct compensation of DC offsets in the I/Q outputs from the receiver, however it does provide a mode that allows the I/Q signals to be measured externally to support easy compensation. To allow optimum measurement of DC offsets it is desirable to remove the input signal to allow fast averaging of the output i.e. without the need to consider the possibility of modulation being present. In this mode the areas of the CMX991/CMX992 that can generate DC offsets remain enabled. The CMX991/CMX992 ‘Cal En’ mode (Rx Mode register $13, b4, see section 6.4.1) disables the early stages of the receiver, as shown in Figure 15. © 2009 CML Microsystems Plc 19 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 5.3 CMX991/CMX992 Transmitter (CMX991 only) The transmitter requires analogue I and Q (baseband) signal inputs. This I/Q input is up-converted by quadrature modulator(s) to a suitable IF (TxIF). This is the modulated signal with the desired modulation but at an IF of typically 45MHz or 90MHz, i.e. lower than the final desired (RF) transmit frequency. The TxIF signal is available at the TXIFOUT pin or can be up-converted to final frequency using the CMX991 image reject up-mixer. The TxIF signal can be optimised by selecting the correct setting of the IFH bit (register $11, b5 see section 6.2.1) for IFs above or below 75MHz. The IF LO input applied to the IF I/Q modulator(s) is generally developed internally (see section 5.4). The LO is divided by either 2 or 4 to generate the quarature signals used in the modulator. The main LO, used in image-reject up-converter, is generated off-chip. 5.3.1 Image-Reject Up-converter The CMX991 transmitter architecture is shown in Figure 16. The image rejection process involves generating TxIF signals with a quadrature phase relationship. The TxIF signals pass through filters to remove harmonic content – this substantially reduces the spurious content of the final output. The bandwidth of the filters is selectable as 45MHz, 60MHz, 90MHz or 120MHz. The signals are then used in a modulator stage which upconverts to the final frequency. The process results in image cancellation of the unwanted mixing sideband with default operation being high side mixing as follows: frf = flo - fTxIf fimage = flo + fTxIF (wanted) (rejected) TXLON TXLOP TXIFOUT Which mixing product is the wanted and which the unwanted image can be selected, see section 6.6. Divide by 2 or 4 TXIP TXOUTP Tx Output TXIN AVDD Select -6dB, 0dB, +6dB TXOUTN TXQP C1 T1 TXQN IF Local Oscillator Divide by 2 or 4 CMX991 Figure 16 CMX991 Transmitter Architecture The image-reject function reduces the need for filtering following the modulator to remove spurious products, however it is likely that some filtering will still be required to meet spurious emissions limits, hence the additional filter as shown in Figure 16. 5.3.2 Direct I/Q IF Output Tx Mode As shown in Figure 16 the filtered TxIF output from the I/Q modulator can be made available on the TXIFOUT pin. This can then be translated up to RF frequency via user-supplied external circuits or in some cases used © 2009 CML Microsystems Plc 20 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 directly for VHF operation. When this mode is selected the image-reject up-converter should be powersaved (register $14, b6 – see section 6.5.1): this disables unused circuits and saves power. 5.4 Local Oscillators 5.4.1 IF Local Oscillator The CMX991/CMX992 provides an integer-N PLL that can be used to create the IF Local oscillator, see Figure 17. The CMX991/CMX992 provides a VCO negative resistance amplifier, so only a tank circuit needs to be implemented externally. Alternatively, this amplifier can be bypassed and an external VCO can be used in the range 40 to 600 MHz. LO to I/Q Rx mixers (and Tx IF section in CMX991) CMX991 CMX992 VCO NR Amplifier NR Control N Divider (Feedback) 2 - 16383 Enable M Divider (Reference) 1 - 8192 FREF VCO Output Buffer Phase Detector Lock Detect Enable VCOP VCON DOIF VCO Tank & Varactors Figure 17 CMX991/CMX992 IF Local Oscillator The integer-n PLL has programmable M and N dividers as shown in Figure 17. The phase detector provides a charge pump output which requires a suitable loop filter to convert this signal into a control voltage for a VCO. The phase detector can be turned off (high impedance mode) and the PLL section disabled if an external LO is to be used, see section 6.8 for control details. In the case of an external LO it is necessary for the VCO Output buffer to remain enabled (section 6.2, register $11, b1) however the VCO amplifier must be disabled (Register $11, b0). The PLL has a lock-detect function that can be evaluated using register $21, b6 (section 6.8.2). The VCO amplifier is a negative resistance amplifier requiring an external tank circuit (see section 4.5). The amplifier has two control bits available in the general control register (section 6.2, register $11, b2 - b3). These bits can be used to optimise performance for a particular tank circuit depending on its Q value. © 2009 CML Microsystems Plc 21 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 5.4.2 CMX991/CMX992 RF Local Oscillator The main LO for both the transmitter and the receiver are not provided on the CMX991/CMX992 and must be supplied from an external source (see section 4.4). Independent selectable internal dividers for Tx and Rx sections are provided to work with the external source, see Figure 3 or Figure 4. 5.5 VBIAS The VBIAS pin provides a 1.6V bandgap reference-derived bias voltage (VBIAS) that may be used as a reference voltage for differential amplifier stages (e.g. in the receiver output). The VBIAS pin can be decoupled to ground but a capacitor greater than 200nF should be used to ensure stability. 5.6 Data Interface The CMX991/CMX992 is controlled via a three wire C-BUS. A fourth pin (RDATA) is required if register readback is to be used. A further pin (NRESET) is provided which, when ‘low’, generates a reset signal (see section for 6.1 further details). The pin should be pulled to the VDDIO supply with a suitable resistor if not used. The data interface can run at a lower voltage than the rest of the IC by setting the VDDIO supply to the required interface voltage, in the range 1.6V to 3.6V. Full details of the control register structure are given in section 6. © 2009 CML Microsystems Plc 22 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 6 CMX991/CMX992 C-BUS Interface and Register Description The C-BUS serial interface supports the transfer of control or status information between the CMX991/CMX992s’ internal registers and an external host. Each C-BUS transaction consists of the host sending a single Register Address byte, which may then be followed by zero or more data bytes that are written into the corresponding CMX991/CMX992 register, as illustrated in Figure 18. Data sent from the host to the Command Data (CDATA) pin is clocked into the CMX991/CMX992 on the rising edge of the Serial Clock (SCLK) input. The C-BUS interface is compatible with common µC/DSP serial interfaces and may also be easily implemented with general purpose I/O pins controlled by a simple software routine. Section 8.1.3.5 gives the detailed C-BUS timing requirements. Whether a C-BUS register is of read or write type is fixed for a given C-BUS register address, thus one cannot both read and write the same C-BUS register address. In order to provide ease of addressing when using this device with the CMX998, the C-BUS addresses shown below are arranged so as not to overlap those used on the CMX998. Thus, a common Chip Select (CSN) signal can be used, as well as common CDATA, RDATA and SCLK signals. Also note that the General Reset ($10) command on the CMX991/CMX992 differs from other CML devices (such as CMX998), which use $01 for this General Reset function. The following C-BUS register addresses are used in the CMX991/CMX992: Write Only register; General Reset Register (Address only, no data) General Control Register, 8-bit write only. Rx Control Register, 8-bit write only. Rx Mode Register, 8-bit write only. Tx Control Register, 8-bit write only. Tx Mode Register, 8-bit write only. Tx Gain Register, 8-bit write only IF PLL M Divider Register, 8-bit write only IF PLL N Divider Register, 8-bit write only Address $10 Address $11 Address $12 Address $13 Address $14 Address $15 Address $16 Address $20-$21 Address $22-$23 Read Only register; General Control Register, 8-bit read only. Rx Control Register, 8-bit read only. Rx Mode Register, 8-bit read only. Tx Control Register, 8-bit read only. Tx Mode Register, 8-bit read only. Tx Gain Register, 8-bit read only IF PLL M Divider Register, 8-bit read only IF PLL N Divider Register, 8-bit read only Address $E1 Address $E2 Address $E3 Address $E4 Address $E5 Address $E6 Address $D0-$D1 Address $D2-$D3 Notes: • • All registers will retain data if DVDD and VDDIO pins are held high, even if all other power supply pins are disconnected. If clock and data lines are shared with other devices DVDD and VDDIO must be maintained in their normal operating ranges otherwise ESD protection diodes may cause a problem with loading signals connected to SCLK, RDATA and CDATA pins, preventing correct programming of other devices. Other supplies may be turned off and all circuits on the device may be powered down without causing this problem. © 2009 CML Microsystems Plc 23 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 Figure 18 C-BUS Transactions © 2009 CML Microsystems Plc 24 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 6.1 General Reset Command (CMX991/CMX992) 6.1.1 General Reset Command (no data) C-BUS address $10 This command resets the device and clears all bits of all registers. The General Reset command places the device into powersave mode. Whenever power is applied to the DVDD pin, a built in power-on-reset circuit ensures that the device powers up into the same state as follows a General Reset command. The NRESET pin on the device will also reset the device to the same state. 6.2 General Control Register (CMX991/CMX992) 6.2.1 General Control Register: 8-bit write-only C-BUS address $11 This register controls general features of the device. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 En Bias IFH Chan Sel Rx Mode VCO_NR2 VCO_NR1 VCO_Buff En VCO_NR En General Control Register b7, b1 and b0 These bits control power up/power down of the various blocks of the IC. In all cases ‘1’ = power up, ‘0’ = power down. b7 b1 b0 Enable bias generator. Enable VCO buffer Enable VCO NR amplifier. (When disabled the amplifier is bypassed to support the application of an external IF LO signal.) General Control Register b6 IF Control bit, this applies to Tx and Rx intermediate frequencies: for IF > 75MHz then set IFH = ‘1’, for IF < 75MHz use IFH = ‘0’. General Control Register b5 and b4 Output Mode Control These bits control the output mode of the receiver. The Rx Mode bit determines if the output mode is I/Q or IF. In I/Q mode both receiver output channels are enabled and the Chan Sel bit has no effect. In IF mode only one of the receiver output channels is enabled, as selected by the Chan Sel bit. NOTE: In IF Mode the I or Q baseband amplifier is also selected by the Chan Sel bit, i.e. only one of the baseband differential amplifiers can be powered up using the Amp Pwr bit in the Rx Control Register. © 2009 CML Microsystems Plc 25 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Bit: b5 x b4 0 0 1 1 1 CMX991/CMX992 I/Q Mode: I and Q channel can be enabled by bits in Rx Control Register. IF Mode: only the I channel output and I channel differential amplifier can be powered up using the Rx Control Register. IF Mode: only the Q channel output and Q channel differential amplifier can be powered up using the Rx Control Register. General Control Register b3 and b2 VCO amplifier Negative Resistance (NR) control for optimum phase noise performance. These bits control the NR (magnitude of the negative transconductance) of the on-chip VCO NR amplifier. The NR minimum mode would thus be used with the lowest Q external tank circuit and NR maximum with the highest Q one. Bit: 6.2.2 b3 0 0 1 1 b2 0 1 0 1 NR maximum NR intermediate value NR intermediate value NR minimum General Control Register 8-bit read-only C-BUS address $E1 This register reads the value in register $11, see section 6.2.1 for details of bit functions. 6.3 Rx Control Register (CMX991/CMX992) 6.3.1 Rx Control Register: 8-bit write-only C-BUS address $12 This register controls general features of the receiver such as Powersave. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 Mix Pwr I/Q Pwr Amp Pwr SLI Pwr LNA DIV2 DIV1 VBIAS Rx Control Register b7 - b3 and b0 These bits control power up/power down of the various blocks of the IC. In all cases ‘1’ = power up, ‘0’ = power down. b7 b6 b5 b4 b3 b0 © 2009 CML Microsystems Plc Enable receiver 1st mixer Enable IF amplifier/VGA stage, I/Q mixers, baseband filters Enable baseband differential amplifiers Enable SLI amplifier Enable LNA control signal (output pin LNAON) Enable VBIAS (bias voltage on pin 43) 26 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 Rx Control Register b2 and b1 RF LO Divider control. Bit: 6.3.2 b2 0 0 1 1 b1 0 1 0 1 RF MIXLO input divide by 2 RF MIXLO input no division RF MIXLO input divide by 4 Reserved – do not use Rx Control Register 8-bit read-only C-BUS address $E2 This read-only register mirrors the value in register $12; see section 6.3.1 for details of bit functions. 6.4 Rx Mode Register (CMX991/CMX992) 6.4.1 Rx Mode Register: 8-bit write-only C-BUS address $13 This register controls operational modes of the receiver such as gain setting. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 IFin Mix Out I/Q Filter Cal En VGA4 VGA 3 VGA 2 VGA 1 Rx Mode Register b7 and b6 Mixer and IF Amplifier signal routing. b7 selects the IF input, b7 = ‘0’ selects IFIP1 and b7 = ‘1’ selects IFIP2. b6 selects the IF output of the Rx 1st Mixer, b6 = ‘0’ selects MIXOUT1 and b6 = ‘1’ selects MIXOUT2. Bit: b7 0 0 1 1 b6 0 1 0 1 Mixer output on MIXOUT1; IF input on IFIP1 and IFINN Mixer output on MIXOUT2; IF input on IFIP1 and IFINN Mixer output on MIXOUT1; IF input on IFIP2 and IFINN Mixer output on MIXOUT2; IF input on IFIP2 and IFINN Rx Mode Register b5 Writing b5 = ’1’ I/Q Filter BW = 1MHz; Writing b5 = ’0’ I/Q Filter BW = 100kHz. Rx Mode Register b4 Enable Calibration Mode: disable LNA and 1st Mixer when b4 = ’1’; normal operation when b4 = ’0’. For further details see section 5.2.4. Rx Mode Register b3 - b0 VGA Control. Bit b3 1 0 0 0 0 0 b2 0 1 1 1 1 0 b1 0 1 1 0 0 1 © 2009 CML Microsystems Plc b0 0 1 0 1 0 1 VGA= -48dB VGA = -42dB VGA = -36dB VGA = -30dB VGA = -24dB VGA = -18dB 27 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Bit 6.4.2 b3 0 0 0 b2 0 0 0 b1 1 0 0 b0 0 1 0 Rx Mode Register: 8-bit read-only CMX991/CMX992 VGA = -12dB VGA = -6dB VGA = 0dB (Maximum gain) C-BUS address $E3 This read-only register mirrors the value in register $13; see section 6.4.1 for details of bit functions. 6.5 Tx Control Register (CMX991 only) 6.5.1 Tx Control Register: 8-bit write-only C-BUS address $14 This register controls transmitter features including Powersave modes. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 0 TxMix Pwr 0 I/QMod Pwr 0 0 Freq I/Q Out Tx Control Register b7 - b4 These bits control power up/power down of the various blocks of the IC. In all cases ‘1’ = power up, ‘0’ = power down. b7 b6 b5 b4 Reserved set to ‘0’. Enable image-reject up-converter Reserved set to ‘0’. Enable I/Q modulator, filters and its input circuits Tx Control Register b3 and b2 Reserved set to ‘0’. Tx Control Register b1 Controls internal operating mode for LO circuits, set b1 = ’0’ for frequency below 600MHz; set b1 = ’1’ for frequencies above 600MHz. Tx Control Register b0 With b0 = ’0’ the output of the I/Q modulator is connected to the image-reject up-converter; with b0 = ’1’ the output of the I/Q modulator is connected to the TXIFOUT output pin. 6.5.2 Tx Control Register 8-bit read-only C-BUS address $E4 This read-only register mirrors the value in register $14; see section 6.5.1 for details of bit functions. © 2009 CML Microsystems Plc 28 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 6.6 Tx Mode Register (CMX991 only) 6.6.1 Tx Mode Register: 8-bit write-only C-BUS address $15 This register controls transmitter features. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 0 0 IF_Filter BW2 IF_Filter BW1 0 HiLo TxRFDiv TxIFDiv Tx Mode Register b7 and b6 Reserved set to ‘0’. Tx Mode Register b5 and b4 These bits select the Tx IF filter bandwidth: Bit: b5 0 0 1 1 b4 0 1 0 1 Tx IF filter bandwidth 45MHz 60MHz 90MHz 120MHz Tx Mode Register b3 Reserved set to ‘0’. Tx Mode Register b2 This bit controls the mixing arrangements in the image-reject up-converter as follows: b2 = ’0’ frf = flo - fif b2 = ‘1’ frf = flo + fif Tx Mode Register b1 Controls the divider for the RF Local Oscillator: b1 = ’0’ selects RF LO divided by 2 mode and b1 = ’1’ selects RF LO divided by 4 mode. Tx Mode Register b0 Controls the divider for the IF Local Oscillator: b0 = ’0’ selects IF LO divided by 4 mode and b0 = ’1’ selects IF LO divided by 2 mode. 6.6.2 Tx Mode Register 8-bit read-only C-BUS address $E5 This read-only register mirrors the value in register $15; see section 6.6.1 for details of bit functions. 6.7 Tx Gain Register (CMX991 only) 6.7.1 Tx Gain Register: 8-bit write-only C-BUS address $16 This register controls transmitter gain features. All bits of this register are cleared to ‘0’ by a General Reset command. Bit: 7 6 5 4 3 2 1 0 Gain2 Gain1 0 0 0 0 0 0 © 2009 CML Microsystems Plc 29 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 Tx Gain Register b7 and b6 I/Q Input Gain Control: These bits control the internal gain applied to input I/Q signals before they are sent to the I/Q modulator. Bit: b7 0 0 1 1 B6 0 1 0 1 I/Q input gain = 0dB I/Q input gain = -6dB I/Q input gain = +6dB Reserved, do not use. Tx Gain Register b5 - b0 Reserved set to ‘0’. 6.7.2 Tx Gain Register 8-bit read-only C-BUS address $E6 This read-only register mirrors the value in register $16, see section 6.7.1 for details of bit functions. 6.8 IF PLL M Divider (CMX991/CMX992) 6.8.1 PLL M Divider C-BUS Addresses $21 and $20 8-bit write-only These registers set the M divider value for the PLL (Reference divider – see Figure 17). The PLL dividers are not updated until both registers ($21 and $20) have been written. The order of writing these registers is not important. Bits also control the enable of the PLL and charge-pump blocks and these control bits are active as soon as $21 is written. $21 Bit: $20 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 E LD_Synth CP M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 M12 - M0 Phase Locked Loop M divider value. CP $21, b5 = ’1’ enables the Charge Pump, $21 b5 = ’0’ puts the Charge Pump into high impedance mode. LD_Synth Only write ‘0’ to b6 of $21 (when read, this shows the integer N PLL lock status). E $21, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL – in this mode an external local oscillator can be supplied to the IC. 6.8.2 PLL M Divider C-BUS Addresses $D1 and $D0 8-bit read-only These registers read the respective values in registers $20 and $21 ($D0 reads back $20 and $D1 reads back $21), see section 6.8.1 for details of bit functions. NOTE: $21 b6 indicates the lock status. If set to '1' then the PLL is locked. © 2009 CML Microsystems Plc 30 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 6.9 PLL N Divider (CMX991/CMX992) 6.9.1 PLL N Divider 8-bit write-only C-BUS Addresses $23 and $22 These registers set the N divider value for the PLL (Feedback divider – see Figure 17). The PLL dividers are not updated until both registers ($23 and $22) have been written. The order of writing these registers is not important. $23 Bit: $22 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 N14 - N0 Phase Locked Loop N divider value. $23, b7 Reserved, set to ‘0’. 6.9.2 PLL N Divider 8-bit read-only C-BUS Addresses $D3 and $D2 These registers read the respective values in registers $22 and $23 ($D2 reads back $22 and $D3 reads back $23), see section 6.9.1 for details of bit functions. © 2009 CML Microsystems Plc 31 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 7 Application Notes 7.1 General CMX991/CMX992 The CMX991/CMX992 chips are RF systems designed for digital wireless applications. These devices address the needs of various data systems, both product standards and regulatory requirements, including TETRA (EN 300 392-2, EN 300 394-1, EN 302 561) and DMR (EN 300 113). APCO Project 25 (TIA102.CAAB). 7.2 Using the CMX992 with the CMX998 The CMX998 device linearises an external RF PA and is an ideal complement to the CMX992. To simplify CMX992+CMX998 designs the CMX992 uses the same physical interface architecture as the CMX998 (SDI is equivalent to CDATA, SDO to RDATA). The C-BUS registers of the two devices are also compatible and allow the CMX992 and CMX998 to be connected to the same C-BUS interface pins, including Chip Select (CSN), assuming the drive capabilities of the host are adequate. 7.3 Typical Gain Distribution The detailed design of a receiver for any particular application will vary. The gain of the receiver depends on the matching arrangements and impedances. A typical design partition is shown in Table 13. The impedances of the later stages are shown as equal which is to ensure that the correct result is presented - the signal can be considered as a voltage at this point in the receiver. Thus if a –80dBm signal is presented to the mixer input with the matching arrangements in Figure 6 (mixer) and Figure 7 (IF filter matching), the signal at each I and Q channel output should be ~40mVp-p differential. Power Impedance Input Match Mixer Match Filter Match Resistor IF Stages -80 -81 -77.5 -83.5 -86.5 -87 -87 -36 dBm 720 ohms 50 300 600 180 650 650 720 Voltage (rms) 2.24E-05 4.88E-05 0.000103 2.84E-05 3.81E-05 3.6E-05 3.79E-05 0.013448 V V (p-p) 6.32E-05 0.000138 0.000292 8.02E-05 0.000108 0.000102 0.000107 0.038037 V -1 3.5 -6 -3 -0.5 0 51 dB 6.781513 6.5103 -11.2288 2.576409 -0.5 0.444191 51 dB Stage Gain Stage Voltage Gain Cumulative Gain 55.58 dB Table 13 Typical Receiver Gain Partitioning 7.4 IF Output Matching In a typical implementation, the MIXOUT pin(s) will require matching from around 500Ω // 4pF to the input of a crystal filter. The impedance of such a filter will often only be specified within the pass-band; it will be very different outside the pass-band. Careful broad band termination of the MIXOUT port is therefore critical in achieving the optimum intermodulation and spurious response performance from the system. The use of a shunt resistive element at MIXOUT is a compromise between system gain and IMD. Values between 1,000 ohms and 120 ohms can be used in practice. Some shunt capacitance at MIXOUT also helps in suppressing harmonics of the RF and LO inputs that may appear at the port, so a Pi network is recommended. With the matching network of Figure 7, the rejection of the half IF response has been found to be optimum using high side mixing. © 2009 CML Microsystems Plc 32 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 7.5 CMX991/CMX992 IF Input Matching The configuration of the IF input has a significant effect on the measured performance. This is demonstrated in Table 14, where the receiver is measured with a 50 ohm source and three different input conditions. The typical input impedance of the IFIP1 or IFIP2 port is ~1.8kΩ//7.8pF. A matched network provides the best noise figure and maximum gain, however intermodulation will be degraded in this condition due to the larger signal levels indicated by the extra gain. The ‘Straight in’ condition means that the 50 ohm signal source was connected directly to either IFIP1 or IFIP2 input via a dc blocking capacitor. Input Condition Noise Figure (dB) 50R shunt resistor matched network straight In Gain (dB) 44 61 50 12 5 8 Table 14 Noise Figure and Gain of IF Amp, VGA, I/Q Mixer and Baseband Filters 7.6 Signal Level Indicator (SLI) The SLI output is an analogue output which gives an indication of the signal level in the receiver IF. A typical use of this signal would be to allow a host to control the receiver gain settings in the CMX991/CMX992. In such an application the SLI pin would be connected to an analogue-to-digital converter which would sample the level which the host would then base choice of gain setting on. The host would then set the appropriate gain value via C-BUS (see section 6.4). When SLI is enabled there is a degradation in the noise figure of the IF stages. In many application circuits this degradation does not cause a significant reduction in overall receiver sensitivity as earlier stages dominate the system noise figure. Typical performance is shown in Figure 19 for the IC alone (IF input) and Figure 20 for a typical CMX991/CMX992 receiver system, measured using the EV9910B / EV9920B evaluation PCB. 2.3 2.2 2.1 SLI Output/V 2 1.9 1.8 1.7 1.6 1.5 -100 -80 -60 -40 -20 0 20 IF input level/dBm Figure 19 Typical SLI Performance (with the signal applied to IFIP1 or IFIP2 and terminated with a 50 ohm resistor) © 2009 CML Microsystems Plc 33 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 2.2 2.1 SLI Output/V 2 1.9 1.8 1.7 1.6 1.5 -100 -80 -60 -40 -20 0 20 RF input level/dBm Figure 20 Typical SLI Performance in an Application Circuit (EV9920B) (Input 460MHz, 25kHz IF crystal filter: 45G15B1) 7.7 Receiver Spurious Rejection Performance The immunity of a receiver to signals away from the wanted channel is an important factor in the overall quality of a radio receiver. Receivers may suffer interference due to off-channel signals due to a variety of mechanisms including intermodulation, blocking and receiver spurious resonses. 7.7.1 Blocking The CMX991/CMX992 blocking performance can be evaluated by injecting an unwanted signal at a 1MHz offset and observing the IF output response with the unwanted signal present or not present, as shown in Figure 21. The channel filtering was used at the IF output of the CMX991 1st mixer to ensure the spectrum analyser was capable of measuring the low levels and a LNA was before the spectrum analyser to ensure the measurement was above the analyser noise floor. The results were taken with the LO path in /2 mode, LO at 820MHz. The wanted signal was at 455MHz @-110dBm and the unwanted was –18dBm at 455.9MHz. The plot in Figure 21 shows the output response with (upper trace) and without (lower trace) the unwanted signal present. The noise floor rises by 3.6dB when the blocker is present; note that the scale is 5dB/div on plot. © 2009 CML Microsystems Plc 34 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver R ef L vl - 80 d Bm CMX991/CMX992 Ma r k e r 1 [T1] -118.91 dBm 45 .00149299 MHz RBW VBW SWT 200 Hz 200 Hz 1.5 s RF Att 0 dB Unit dBm -8 0 0 . 3 dB O ff se t 1 [T1] -8 5 2 [T1] 2 1 [T2] -9 0 -1 1 8 . 91 45.001 49 29 9 - 8 8 . 49 45.000 03 00 6 3 . 56 7.450 58 06 0 dBm A M Hz dBm M Hz dB n Hz -9 5 1A V G 2V I EW 1SA 2SA - 10 0 EX T - 10 5 - 11 0 1 - 11 5 1 - 12 0 - 12 5 - 13 0 C e nt e r 4 5 M H z 1 kHz/ Sp an 1 0 k Hz Figure 21 IF Output Response with and without blocking signal present 7.7.2 Half IF Response The half IF response occurs at a frequency half the 1st IF frequency away from the wanted signal is a 2nd order product. For example if receiving at 455MHz with a 1st IF of 45MHz and ‘low side’ LO at 410MHz the half IF response is at 455MHz – (45/2)MHz = 432.5MHz. The half IF response of the CMX991/CMX992 is dependant on the output matching of the 1st mixer. The arrangements described in 7.4 should be applied and matching can be optimised for a particular design. The half IF performance has some variability between devices and care needs to be taken to ensure sufficient margin exits for device variations, a standard deviation of 1.9 may be used for such calculations. 7.8 Modulation Accuracy To check the phase error of the transmitter, a CMX910 Evaluation Kit (EV9100) was used to drive the Tx I/Q modulator differentially with GMSK. This setup tested 9.6kbps GMSK with a BT of 0.4, to fit in a 25kHz channel. The plot in Figure 22 shows the Tx Output ACP performance as ~77dBc and Table 15 shows the RMS phase error as being less than 1 degree (~0.8 degrees). The differential output level from the EV9100 is 2Vp-p, therefore the 0dB I/Q gain setting was used. © 2009 CML Microsystems Plc 35 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver CMX991/CMX992 M ar k e r 1 [T1] -21.46 dBm 4 59.99993387 MHz R e f Lv l - 9 .2 d B m RBW VBW SWT 500 Hz 2 kHz 1.35 s RF Att 20 d B Unit d Bm - 9 .2 0.8 d B O f f s et 1 [T1] -21 .4 6 459.99993 3 8 7 CH PWR -9 . 7 1 ACP Up -77 . 6 0 ACP Low -77 . 7 6 1 - 20 - 30 dB m A MHz dBm dB dB - 40 1 VIEW 1 RM - 50 - 60 - 70 - 80 - 90 C0 C0 cl1 - 1 00 c l 1 cu 1 cu1 - 1 09 C e nter 4 6 0 M H z 6.6 kHz/ Span 6 6 k H z Figure 22 Tx Output with 9.6kbps GMSK from an EV9100 (TxIF = 90MHz, ACP ~ 77dBc) CF SR R e f Lv l -9.2 dBm 460 MHz 9. 6 k Sy z mb o l/ Err or s De m o d MSK S y m b ol T a b le 0.8 dB Offset A 0 40 80 120 160 200 240 01011000 10110001 10111111 00100111 11010100 01100000 010001 1 1 1 0 1 00 0 1 1 1 1 0 01 1 1 0 1 1 1 01 1 1 1 1 1 0 01 0 1 1 1 0 0 10 0 1 0 0 0 0 10 1 0 11 11 1 0 0 0 01 11 1 1 1 1 00 10 1 0 1 0 01 01 1 1 0 0 00 00 0 0 0 1 01 00 0 0 1 0 0 0 0 0 00 1 0 0 1 1 0 11 1 1 1 1 1 0 10 1 1 0 1 0 1 00 0 0 1 1 1 1 00 0 0 1 0 1 0 01 1 1 10 1 0 1 0 1 1 11 1 0 1 1 1 1 01 0 1 0 1 1 1 10 1 1 0 0 1 0 10 1 1 0 0 0 0 10 1 1 0 1 0 E rr o r Su m m a ry Error Vector Mag Ma gn i tu de Er ror Phase Error Fr eq Er ro r Am pl i tu de Dr oop IQ O f fs et 1 .5 2 0 .6 4 0 .7 9 - 4 .6 8 0 .1 3 3 .6 9 % r ms % r ms d eg r m s Hz d B/ sy m % 4 . 18 % Pk at sym 1 1 . 37 % Pk at sym 6 - 2 . 34 d e g P k a t s y m 1 - 4 . 68 Hz Pk R h o F a c t or 0 . 9 98 4 I Q Im b a l an c e 0.06 % Table 15 Symbol/Error Table for the Tx with 9.6kbps GMSK from an EV9100 © 2009 CML Microsystems Plc 36 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8 Performance Specification 8.1 Electrical Performance CMX991/CMX992 For definition of voltage and reference signal, see Table 2. 8.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. ESD Warning: This high performance RF integrated circuit is an ESD sensitive device which has unprotected inputs and outputs. Handling and assembly of this device should only be carried out at an ESD protected workstation. Supply (AVDD – AVSS) or (DVDD – DVSS) Voltage on any pin to AVSS or DVSS Voltage between AVSS and DVSS Voltage between AVDD and DVDD Current into or out of DGND, any AVDD pin or DVDD Current into or out of AGND (exposed metal pad) Current into or out of any other pin Q3 Package Total Allowable Power Dissipation at Tamb = 25°C ... De-rating Storage Temperature Operating Temperature 8.1.2 Min. -0.3 -0.3 -50 -0.3 -75 -200 -20 Max. +4.0 VDD + 0.3 +50 +0.3 +75 +200 +20 Units V V mV V mA mA mA Min. – – -55 -40 Max. 1750 17.5 +125 +85 Units mW mW/°C °C °C Min. 3.0 1.6 -40 Max. 3.6 3.6 +85 Units V V °C Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (AVDD – AVSS) and (DVDD – DVSS) IO Supply (VDDIO – DVSS) Operating Temperature © 2009 CML Microsystems Plc 37 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8.1.3 CMX991/CMX992 Operating Characteristics The following conditions apply unless otherwise specified: VDD = AVDD = DVDD = 3.0V to 3.6V; VSS = AVSS = DVSS, TAMB = -40°C to +85°C, SLI disabled. 8.1.3.1 DC Parameters Notes Min. Typ. Max. Units A, F C – – 10 2.3 – – µA mA D D G G B – – – – – 59 13 85 45 – – – – – 600 mA mA mA mA µA Logic ‘1’ Input Level Logic ‘0’ Input Level 70% – – – – 30% VDDIO VDDIO Output Logic ‘1’ Level (lOH = 0.6 mA) Output Logic ‘0’ Level (lOL = -1.0 mA) Power-up Time Reference Voltage All Blocks Except Reference Voltage Internal Bandgap Voltage (Vbg) External Bias Voltage (VBIAS) – derived from Vbg 80% – – – – +0.4 VDDIO V – – 1.06 1.45 – – 1.13 1.6 0.5 10 1.2 1.75 ms µs V V DC Parameters Total Current Consumption Powersave Mode VBIAS Only Operating Currents Rx Only Synth Only Tx Only (RF Output) Tx Only (IF Output) Current from VDDIO Notes: E E A. Powersave mode includes after general reset with all analogue and digital supplies applied and also in the case with VDD applied but with all analogue supplies disconnected (i.e. in this later scenario, power from VDD will not exceed the specified value whatever the state of the registers). B. Assumes 30pF on each C-BUS interface line and an operating serial clock frequency of 5MHz. C. The stated current drawn here is with the bandgap reference and accompanying bias current generators enabled only (register $11, b7), all other circuitry is disabled. D. Not including any current drawn from the device pins by external circuitry. Rx only – Rx circuitry plus SLI (8mA), synthesiser and bias generator. Synth only – Synthesiser, NR Amplifier, VCO Buffer and bias generator. E. As measured from the rising edge of CSN. F. At Tamb = 25ºC, not including any current drawn from the CMX991/CMX992 pins by external circuitry. G. Tx only – Tx circuitry plus synthesiser and bias generator. IF output basically excludes the Tx Image Reject Mixer, otherwise the two cases are the same. © 2009 CML Microsystems Plc 38 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8.1.3.2 AC Parameters – Receiver Sections Rx 1st Mixer Gain Noise Figure Input Third Order Intercept Point (IIP3) 450MHz 950MHz Input Frequency Range LO Frequency Range Input Impedance IF Output Frequency Range IF Output Impedance LO Leakage at Input 1dB Compression Point (input) Half IF Rejection Blocking LO Input Level Notes: CMX991/CMX992 Notes 1, 7 7 3 2,4 5,6 Min. – – Typ. 16 11.5 Max. – – Units dBV/V dB – +5 100 50 – 10 – – -10 60 – -10 +11 +9.5 – – 300 – 500 – -7 70 90 – – – 1000 1150 – 150 – -27 – – – 0 dBm dBm MHz MHz Ω MHz Ω dBm dBm dB dB dBm 1. Measured from a low loss matched input source to matched output load. 2. Significant variation in half IF rejection can occur as a function of frequency and LO level/matching. Users are recommended to optimise for a particular application. 3. LO as supplied to mixer circuit block. 4. Relative level of signal at mixer IF output relative to RF signal of –30dBm; IF = 45MHz and RF = 450MHz or 800MHz. 5. Relative to –107dBm (level from ETSI EN 300 113), based on IF = 45MHz and RF = 450MHz, to give ~3dB rise in mixer output noise floor. 6. Including operation of selectable dividers, tested in divide by 2 mode. 7. Gain and noise figure can be adjusted using external matching resistors. Note: this will also affect the IIP3 IF Amplifier and I/Q Demodulator Gain Noise Figure Third Order Intercept Point (Input) Input Frequency Range LO Frequency Range Input Impedance Output Impedance LO Leakage at Input 1dB Compression Point VGA Control Range VGA Step Size Image Rejection (I/Q Gain/Phase matching) I/Q Output Bandwidth (-3dB) 1MHz mode 100kHz mode © 2009 CML Microsystems Plc Notes 10, 17 11 17 12 15 13 14 16 39 Min. – – – 10 40 – – – -30 – 4 30 Typ. 45 8 -20 – – 1800 20 – – 48 6 40 Max. – – – 150 600 – – -27 – – 8 – Units dBV/V dB dBm MHz MHz Ω Ω dBm dBm dB dB dB 1 100 1.4 135 – – MHz kHz D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Notes: 10. Measured from an un-matched 50Ω input source to a single-ended I or Q output voltage. Note that practical measurements include combined response of IF Amplifier, I/Q demodulator and I/Q filter stages. 11. At maximum VGA setting (0dB); see section 7.4 for further details. 12. LO Supplied at four times the IF frequency. 13. At maximum gain. 14. Eight VGA steps. 15. Based on single ended input at 45MHz. 16. In 1MHz output mode an IF output in the range 450kHz to 465kHz is supported. 17. Measured with a 45MHz IF; gain reduces at higher IFs. I/Q Filters Gain Noise Figure Third Order Intercept Point (Input) Output Impedance Output Anti-alias Filter Stop-band Stop-band Attenuation Data Filter Bandwidth (-3dB) Differential Output Voltage Swing Notes: Notes 10 20 20 20 21 Min. – – – – 1.92 55 – – Typ. 6 N/A N/A N/A – – 100 – Max. – – – – – – – 4 Units dBV/V dB dBm Ω MHz dB kHz Vp-p 20. Performance included in overall performance of I/Q Demodulator. 21. This is the maximum swing to guarantee meeting the third order distortion characteristics under the specified conditions and is not the maximum limiting value. For clarity, this means that the device has the capability to produce +/-1V on each of the differential outputs. The outputs are capable of driving a load resistance across the differential outputs of 1kΩ. This voltage output capability provides easy interfacing to other CML devices, like the CMX981, which has a maximum input signal amplitude of 2.4Vp-p. Differential Amplifiers Gain Bandwidth Product Input Offset Voltage Input Common Mode Range Input Bias Current Input Resistance Slew Rate Differential Input Voltage Input Referred Noise at 1kHz Input Referred Noise at 450kHz DC Output Range Notes: CMX991/CMX992 Notes 30, 33 32 30 31 Min. 11 – 1.0 – – – – – – AVss+0.1 Typ. 14 1 1.6 0.4 160 6 – 15 10 – Max. – – 2.5 – – – 1.2 – – AVDD-0.1 Units MHz mV V µA kΩ V/µs V nV/√Hz nV/√Hz V 30. With a load of 1kΩ in parallel with 100pF referenced to a virtual earth not ground. 31. The inputs are protected with diodes. These diodes prevent the inadvertent application of voltages that may cause damage to the input transistors. 32. For small signal operation. It is recommended that for this application the input levels be restricted to +/-0.4V about a defined reference voltage of 1.6V (nominal); this will allow for some tolerance in components and for the precision of the setting the reference voltage. 33. Gain Bandwidth Product typically 40MHz with 15pF load. © 2009 CML Microsystems Plc 40 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Auxiliary Rx Functions LNA Control Enable Voltage Level Disable Voltage Level CMX991/CMX992 Notes SLI Output Output Voltage Range Scaling Operating Range Notes: 8.1.3.3 Typ. Max. Units 80% 0 – – – 0.4 VDDIO V Vref. 5 – – 10 50 – 15 – V mV/dB dB 35. See section 7.6. AC Parameters - Transmitter I/Q Modulator Input Signal Level Gain Control Steps Input Common Mode Range Input Voltage Range (on each input) Third Order IMD Products IMD Products (greater than third order) Carrier Leakage Image Suppression I or Q Modulation Bandwidth (-3dB) Notes: 35 Min. Notes 40 41 42 Min. – – VSS+1.0 VSS+0.5 – – – – – Typ. 2.0 +6, 0, -6 VDD/2 – – – -30 -40 – Max. – – VDD-1.0 VDD-0.5 -50 -60 – -30 1 Units Vp-p dB V V dBc dBc dBc dBc MHz 40. The 2.0Vp-p is a differential signal. For clarity, this means +/-0.5V on each input. 41. The common mode range is based on a 2.0Vp-p differential input signal level. 42. This is the maximum modulation frequency that should be applied in the I or Q channel. The bandwidth of the modulator is much higher than this but use of higher modulation frequencies may result in an increase in distortion products. © 2009 CML Microsystems Plc 41 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver Post Modulator Filter CMX991/CMX992 Notes Selectable Filter Bandwidth Gain Stopband (45MHz Mode) >135MHz Stopband (60MHz Mode) >170MHz Stopband (90MHz Mode) >270MHz Stopband (120MHz Mode) >360MHz Tx IF Output Frequency Range Output Signal Level Wideband Noise at 1MHz Output Impedance Notes: Max. Units – MHz – Typ. 45, 60, 90, 120 -2 – dB – 30 – dB – 30 – dB – 30 – dB – 30 – dB 45 – – – – -10 -142 50 120 – – – MHz dBm dBc/Hz Ω Min. 100 – – – – -35 Typ. – 2000 -10 -141 -40 -40 Max. 1000 – – – – – Units MHz Ω dBm dBc/Hz dBc dBc – – 70 70 – – dB dB 40 -10 – – -5 2 or 4 2000 0 – MHz dBm – 45 46 45 At pin TXIFOUT 46. For specified I/Q Modulator Input Signal Level. Image-Reject Up-Converter Output Frequency Range Output Impedance Output Level Wideband Noise at 1MHz Image Suppression LO Suppression APCO P25 Performance ACPR (12.5kHz) with C4FM ACPR (12.5kHz) with H-CPM LO Input Frequency Range Level Division Ratios Notes: Min. Notes 50 46, 51 52 52 50. Differential output TXOUTP and TXOUTN 51. Output via 4:1 balun (See section 4.3.1) and matching to 50Ω 52. TxIF of 45MHz or 90MHz; ACPR measured as TIA-102.CAAB-B section 3.2.8.1 © 2009 CML Microsystems Plc 42 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8.1.3.4 CMX991/CMX992 AC Parameters – IF LO Integer N PLL Phase Locked Loop Supply Current (Enabled) Supply Current (Standby) Reference Input Frequency Level Divide Ratios IF Synthesiser Comparison Frequency Input Frequency Range Input Level Divide Ratios Charge Pump Current Normalised SSB Phase Noise VCO Negative Resistance Amplifier Supply Current (Enabled) Supply Current (Standby) Input Frequency Range Phase Noise at 10kHz Offset Phase Noise at 100kHz Offset VCO Output Buffer Supply Current (Enabled) Supply Current (Standby) Frequency Range IF LO Input Frequency Range Level Division Ratios Notes: Notes Min. Typ. Max. Unit 1 – – 5 1 – – mA µA 5 0.5 2 – – – 30 – 8191 MHz Vp-p – 40 -10 12 – – – – -4 – ±2.5 152 500 600 – 32767 – – kHz MHz dBm mA dBc/Hz – – 40 – – 2 1 – -110 -125 – – 600 – – mA µA MHz dBc/Hz dBc/Hz – – 40 4 1 – – – 600 mA µA MHz 40 -10 – – -5 2 or 4 600 0 – MHz dBm 90 1 91 91 1 92 90. Sinewave or clipped sinewave. 91. With external components forming an 180MHz VCO, as shown in Figure 13/Table 11 and measured after the on-chip divide by 2. 92. Input to VCOP and/or VCON pins, VCO Negative Resistance amplifier disabled, see section 6.2.1) © 2009 CML Microsystems Plc 43 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8.1.3.5 CMX991/CMX992 AC Parameters – C-BUS C-BUS Timings (See Figure 23) tCSE CSN-enable to clock-high time tCSH Last clock-high to CSN-high time tLOZ Clock-low to reply output enable time tHIZ CSN-high to reply output 3-state time tCSOFF CSN-high time between transactions tNXT Inter-byte time tCK Clock-cycle time tCH Serial clock-high time tCL Serial clock-low time tCDS Command data set-up time tCDH Command data hold time tRDS Reply data set-up time tRDH Reply data hold time Notes Min. 100 100 0.0 – 1.0 200 200 100 100 75.0 25.0 50.0 0.0 Typ. – – – – – – – – – – – – – Max. – – – 1.0 – – – – – – – – – Units ns ns ns µs µs ns ns ns ns ns ns ns ns Maximum 30pF load on each C-BUS interface line. Figure 23 C-BUS Timing © 2009 CML Microsystems Plc 44 D/991_992/7 RF Quadrature Transceiver / RF Quadrature Receiver 8.2 CMX991/CMX992 Packaging Notes: 1. 2. In this device, the underside of the Q3 package should be electrically connected to the analogue ground. The circuit board should be designed so that no unwanted short circuits can occur. As package dimensions may change after publication of this datasheet, it is recommended that you check for the latest Packaging Information from the Datasheets page of the CML website: [www.cmlmicro.com]. Figure 24 Q3 Mechanical Outline: Order as part no. CMX991Q3 or CMX992Q3 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.