FEATURES FUNCTIONAL BLOCK DIAGRAM 4 A peak output current Working voltage High-side or low-side relative to input: 537 V peak High-side to low-side differential: 800 V peak High frequency operation: 1 MHz maximum 3.3 V to 5 V CMOS input logic 4.5 V to 18 V output drive UVLO at 2.5 V VDD1 ADuM3223A/ADuM4223A UVLO at 4.1 V VDD2 ADuM3223B/ADuM4223B UVLO at 7.0 V VDD2 ADuM3223C/ADuM4223C UVLO at 11.0 V VDD2 Precise timing characteristics 54 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching CMOS input logic levels High common-mode transient immunity: >25 kV/μs Enhanced system-level ESD performance per IEC 61000-4-x High junction temperature operation: 125°C Thermal shutdown protection Default low output Safety and regulatory approvals ADuM3223 narrow-body, 16-lead SOIC UL recognition per UL 1577 3000 V rms for 1 minute SOIC long package CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak ADuM4223 wide-body, 16-lead SOIC UL recognition per UL 1577 5000 V rms for 1 minute SOIC long package CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak Qualified for automotive applications APPLICATIONS Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Automotive 1 VIA 1 VIB 2 ADuM3223/ ADuM4223 ENCODE 16 VDDA DECODE VDD1 3 15 VOA 14 GNDA GND1 4 13 NC DISABLE 5 12 NC NC 6 NC 7 11 VDDB ENCODE VDD1 8 DECODE 10 VOB 9 NC = NO CONNECT GNDB 10450-001 Data Sheet Isolated Precision Half-Bridge Driver, 4 A Output ADuM3223/ADuM4223 Figure 1. GENERAL DESCRIPTION The ADuM3223/ADuM42231 are 4 A isolated, half-bridge gate drivers that employ the Analog Devices, Inc., iCoupler® technology to provide independent and isolated high-side and low-side outputs. The ADuM3223 provides 3000 V rms isolation in the narrow body, 16-lead SOIC package, and the ADuM4223 provides 5000 V rms isolation in the wide body, 16-lead SOIC package. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers. The ADuM3223/ADuM4223 isolators each provide two independent isolated channels. They operate with an input supply ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM3223/ ADuM4223 offer the benefit of true, galvanic isolation between the input and each output. Each output may be continuously operated up to 537 V peak relative to the input, thereby supporting low-side switching to negative voltages. The differential voltage between the high-side and low-side may be as high as 800 V peak. As a result, the ADuM3223/ADuM4223 provide reliable control over the switching characteristics of IGBT/MOSFET configurations over a wide range of positive or negative switching voltages. Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM3223/ADuM4223 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................9 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions........................... 11 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 1 Applications Information .............................................................. 15 Revision History ............................................................................... 2 PC Board Layout ........................................................................ 15 Specifications..................................................................................... 3 Propagation Delay-Related Parameters ................................... 15 Electrical Characteristics—5 V Operation................................ 3 Thermal Limitations and Switch Load Characteristics ......... 15 Electrical Characteristics—3.3 V Operation ............................. 4 Output Load Characteristics ..................................................... 15 Package Characteristics ............................................................... 5 Boot-Strapped Half-Bridge Operation .................................... 16 Insulation and Safety-Related Specifications ............................ 5 DC Correctness and Magnetic Field Immunity .......................... 16 Regulatory Information ............................................................... 6 Power Consumption .................................................................. 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 7 Insulation Lifetime ..................................................................... 18 Outline Dimensions ....................................................................... 19 Recommended Operating Conditions ...................................... 8 Ordering Guide .......................................................................... 20 Absolute Maximum Ratings............................................................ 9 Automotive Products ................................................................. 20 REVISION HISTORY 7/15—Rev. E to Rev. F Changes to Features Section............................................................ 1 Changes to Table 6 and Table 7...................................................... 6 Changes to Power Consumption Section .................................... 17 11/14—Rev. D to Rev. E Changes to Features Section and General Description Section ................................................................................................ 1 Changes to Table 5 ............................................................................ 5 Changes to Regulatory Information Section, Table 6, and Table 7 ................................................................................................ 6 Changes to Table 8 and Table 9 ....................................................... 7 4/14—Rev. C to Rev. D Changes to Applications Section .................................................... 1 Changes to Insulation Lifetime Section ....................................... 18 Changes to Ordering Guide .......................................................... 20 12/13—Rev. B to Rev. C Change to Features Section ............................................................. 1 Changes to Switching Specifications Parameter, Table 1 ............ 3 Added Thermal Shutdown Temperatures Parameter, Table 1 .... 3 Changes to Switching Specifications Parameter, Table 2 ............ 4 Added Thermal Shutdown Temperatures Parameter, Table 2 .... 4 Changes to Table 10 ..........................................................................8 Change to Figure 13 Caption ........................................................ 13 Changes to Thermal Limitations and Switch Load Characteristics Section .................................................................. 15 Change to Boot-Strapped Half-Bridge Operation Section ....... 16 5/13—Rev. A to Rev. B Added VDDA, VDDB Rise Time of 0.5 V/μs; Table 10 .......................8 Changes to Figure 22...................................................................... 16 1/13—Rev. 0 to Rev. A Added Automotive Information (Throughout) ............................1 Updated Safety and Regulatory Approvals (Throughout) ...........1 Changed High-Side to Low-Side Differential from 700 VDC PEAK to 800 V peak .....................................................................................1 Added ROA, ROB Minimum and Maximum Values, Table 1 .........3 Added ROA, ROB Minimum and Maximum Values, Table 2 .........4 Changes to Table 13 ....................................................................... 10 Changes to Figure 19...................................................................... 15 Added Boot-Strapped Half Bridge Operation Section and Figure 22; Renumbered Sequentially ........................................... 16 Changes to Ordering Guide .......................................................... 20 5/12—Revision 0: Initial Version Rev. F | Page 2 of 20 Data Sheet ADuM3223/ADuM4223 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 12 V. Switching specifications are tested with CMOS signal levels. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Per Channel, Quiescent Supply Current at 1 MHz VDD1 Supply Current VDDA/VDDB Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive Going Threshold Negative Going Threshold Hysteresis Positive Going Threshold Negative Going Threshold Hysteresis Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current1 Output Pulsed Source Resistance Output Pulsed Sink Resistance THERMAL SHUTDOWN TEMPERATURES Junction Temperature Shutdown, Rising Edge Junction Temperature Shutdown, Falling Edge SWITCHING SPECIFICATIONS Pulse Width2 Maximum Data Rate3 Propagation Delay4 ADuM3223A/ADuM4223A Propagation Delay Skew5 Channel-to-Channel Matching6 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current Per Channel Dynamic Output Supply Current Per Channel Refresh Rate Symbol Typ Max Unit IDDI(Q) IDDO(Q) 1.4 2.3 2.4 3.2 mA mA IDD1(Q) IDDA/IDDB(Q) IIA, IIB VIH VIL VOAH, VOBH VOAL, VOBL 1.6 5.6 +0.01 2.5 8.0 +1 mA mA µA V V V V IOx = −20 mA, VIx = VIxH IOx = +20 mA, VIx = VIxL VDD2UV+ VDD2UV− VDD2UVH VDD2UV+ VDD2UV− VDD2UVH VDD2UV+ VDD2UV− VDD2UVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB Min −1 0.7 × VDD1 0.3 × VDD1 VDD2 – 0.1 3.2 5.7 8.9 2.0 0.3 0.3 TJR TJF PW tDHL, tDLH tDHL, tDLH tPSK tPSKCD tPSKCD tR/tF IDDI(D) IDDO(D) fr VDD2 0.0 0.15 6 Up to 1 MHz, no load Up to 1 MHz, no load 0 ≤ VIA, VIB ≤ VDD1 4.1 3.6 0.5 4.4 V V V A-grade A-grade A-grade 6.9 6.2 0.7 10.5 9.6 0.9 4.0 1.1 0.6 7.4 V V V V V V A Ω Ω B-grade B-grade B-grade C-grade C-grade C-grade VDD2 = 12 V VDD2 = 12 V VDD2 = 12 V 11.1 3.0 3.0 150 140 50 1 31 35 Test Conditions 43 47 1 1 12 0.05 1.65 1.2 1 °C °C 54 59 12 5 7 18 ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps CL = 2 nF, VDD2 = 12 V CL = 2 nF, VDD2 = 12 V CL = 2 nF, VDD2 = 12 V; see Figure 20 CL = 2 nF, VDD2 = 4.5 V; see Figure 20 CL = 2 nF, VDD2 = 12 V; see Figure 20 CL = 2 nF, VDD2 = 12 V; see Figure 20 CL = 2 nF, VDD2 = 4.5 V; see Figure 20 CL = 2 nF, VDD2 = 12 V; see Figure 20 VDD2 = 12 V VDD2 = 12 V Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings. The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels. 2 Rev. F | Page 3 of 20 ADuM3223/ADuM4223 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 12 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Per Channel, Quiescent Supply Current at 1 MHz VDD1 Supply Current VDDA/VDDB Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive Going Threshold Negative Going Threshold Hysteresis Positive Going Threshold Negative Going Threshold Hysteresis Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current1 Output Pulsed Source Resistance Output Pulsed Sink Resistance THERMAL SHUTDOWN TEMPERATURE Junction Temperature Shutdown, Rising Edge Junction Temperature Shutdown, Falling Edge SWITCHING SPECIFICATIONS Pulse Width2 Maximum Data Rate3 Propagation Delay4 ADuM3223A/ADuM4223A Propagation Delay Skew5 Channel-to-Channel Matching6 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current Per Channel Dynamic Output Supply Current Per Channel Refresh Rate Symbol Typ Max Unit IDDI(Q) IDDO(Q) 0.87 2.3 1.4 3.2 mA mA IDD1(Q) IDDA/IDDB(Q) IIA, IIB VIH VIL VOAH, VOBH VOAL, VOBL 1.1 5.6 +0.01 1.5 8.0 +10 mA mA µA V V V V Up to 1 MHz, no load Up to 1 MHz, no load 0 ≤ VIA, VIB ≤ VDD1 V V V V V V V V V A Ω Ω A-grade A-grade A-grade B-grade B-grade B-grade C-grade C-grade C-grade VDD2 = 12 V VDD2 = 12 V VDD2 = 12 V VDD2UV+ VDD2UV− VDD2UVH VDD2UV+ VDD2UV− VDD2UVH VDD2UV+ VDD2UV− VDD2UVH IOA(SC), IOB(SC) ROA, ROB ROA, ROB Min −10 0.7 × VDD1 0.3 × VDD1 VDD2 – 0.1 3.2 5.7 8.9 2.0 0.3 0.3 TJR TJF PW tDHL, tDLH tDHL, tDLH tPSK tPSKCD tPSKCD tR/tF IDDI(D) IDDO(D) fr VDD2 0.0 4.1 3.6 0.5 6.9 6.2 0.7 10.5 9.6 0.9 4.0 1.1 0.6 0.15 4.4 7.4 11.1 3.0 3.0 150 140 50 1 35 37 6 47 51 1 1 12 0.05 1.65 1.1 1 Test Conditions IOx = −20 mA, VIx = VIxH IOx = +20 mA, VIx = VIxL °C °C 59 65 12 5 7 22 ns MHz ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps CL = 2 nF, VDD2 = 12 V CL = 2 nF, VDD2 = 12 V CL = 2 nF, VDD2 = 12 V, see Figure 20 CL = 2 nF, VDD2 = 4.5 V, see Figure 20 CL = 2 nF, VDD2 = 12 V, see Figure 20 CL = 2 nF, VDD2 = 12 V, see Figure 20 CL = 2 nF, VDD2 = 4.5 V, see Figure 20 CL = 2 nF, VDD2 = 12 V, see Figure 20 VDD2 = 12 V VDD2 = 12 V Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings. The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay parameters. 5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters. 6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels. 2 Rev. F | Page 4 of 20 Data Sheet ADuM3223/ADuM4223 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) Capacitance (Input-to-Output) Input Capacitance IC Junction-to-Ambient Thermal Resistance ADuM3223 ADuM4223 IC Junction-to-Case Thermal Resistance ADuM3223 ADuM4223 Symbol RI-O CI-O CI Min Typ 1012 2.0 4.0 Max Unit Ω pF pF θJA θJA 76 45 °C/W °C/W θJC θJC 42 29 °C/W °C/W Test Conditions f = 1 MHz INSULATION AND SAFETY-RELATED SPECIFICATIONS ADuM3223 Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 3000 4.0 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.0 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >400 II mm V Unit V rms mm Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM4223 Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 7.6 min Minimum External Tracking (Creepage) L(I02) 7.6 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >400 II mm V Rev. F | Page 5 of 20 Conditions 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM3223/ADuM4223 Data Sheet REGULATORY INFORMATION The ADuM3223 is approved or pending approval by the organizations listed in Table 6. Table 6. UL Recognized under UL 1577 Component Recognition Program1 Single/Protection 3000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice 5A VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122 Basic insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage File 205078 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3223 is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 second (current leakage detection limit = 6 µA). In accordance with DIN V VDE V 0884-10, each ADuM3223 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. The ADuM4223 is approved or pending approval by the organizations listed in Table 7. Table 7. UL Recognized Under UL 1577 Component Recognition Program1 Single/Protection 5000 V rms Isolation Voltage File E214100 CSA Approved under CSA Component Acceptance Notice 5A CQC Approved under CQC11-471543-2012 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage; basic insulation per CSA 60950-1-07 and IEC 60950-1, 760 V rms (1074 V peak) maximum working voltage File 205078 Reinforced insulation per GB4943.1-2011, 380 V rms (537 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m; basic insulation per GB4943.1-2011, 600 V rms (848 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 m File CQC14001108627 1 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122 Reinforced insulation, 849 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4223 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM4223 is proof tested by applying an insulation test voltage ≥ 1592 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. F | Page 6 of 20 Data Sheet ADuM3223/ADuM4223 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 8. ADuM3223 VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety-Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS Conditions Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak Vpd(m) 896 672 V peak V peak VIOTM VIOSM 4242 6000 V peak V peak VIO = 500 V TS PS RS 150 1.64 >109 °C W Ω Conditions Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 849 1592 V peak V peak Vpd(m) 1273 1018 V peak V peak VIOTM VIOSM 7071 6000 V peak V peak TS PS RS 150 2.77 >109 °C W Ω VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) Vpd(m) Table 9. ADuM4223 VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety-Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 3) VIO = 500 V Rev. F | Page 7 of 20 Vpd(m) Data Sheet 1.8 RECOMMENDED OPERATING CONDITIONS 1.6 Table 10. 1.4 Parameter Operating Junction Temperature Supply Voltages1 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 200 AMBIENT TEMPERATURE (°C) 10450-102 SAFE OPERATING PVDD1 , PVDDA OR PVDDB POWER (W) ADuM3223/ADuM4223 Figure 2. ADuM3223 Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10 VDD1 Rise Time VDDA, VDDB Rise Time Maximum Input Signal Rise and Fall Times Common-Mode Transient Immunity, Static2 Common-Mode Transient Immunity, Dynamic3 3.0 2.5 2.0 1.5 1.0 0.5 0 Min −40 Max +125 Unit °C VDD1 VDDA, VDDB TVDD1 TVDDA, TVDDB TVIA, TVIB 3.0 4.5 5.5 18 1 10 1 V V V/µs V/µs ms −50 +50 kV/µs −25 +25 kV/µs All voltages are relative to their respective ground. See the Applications Information section for information on immunity to external magnetic fields. 2 Static common-mode transient immunity is defined as the largest dv/dt between GND1 and GNDA/GNDB, with inputs held either high or low such that the output voltage remains either above 0.8 × VDD2 for VIA/VIB = high or 0.8 V for VIA/VIB = low. Operation with transients above the recommended levels may cause momentary data upsets. 3 Dynamic common-mode transient immunity is defined as the largest dv/dt between GND1 and GNDA/GNDB, with the switching edge coincident with the transient test pulse. Operation with transients above the recommended levels may cause momentary data upsets. 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 10450-103 SAFE OPERATING PVDD1 , PVDDA OR PVDDB POWER (W) 1 Symbol TJ Figure 3. ADuM4223 Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10 Rev. F | Page 8 of 20 Data Sheet ADuM3223/ADuM4223 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 11. Parameter Storage Temperature Operating Junction Temperature Supply Voltages1 Input Voltage1 Output Voltage1 Average Output Current, per Pin2 Common-Mode Transients3 Symbol TST TJ Rating −55 °C to +150 °C −40 °C to +150 °C VDD1 VDDA, VDDB VIA, VIB, DISABLE VOA VOB IO −0.5 V to +7.0 V −0.5 V to +20 V −0.5 V to VDD1 + 0.5 V CMH, CML −100 kV/µs to +100 kV/µs ESD CAUTION −0.5 V to VDDA + 0.5 V −0.5 V to VDDB + 0.5 V −35 mA to +35 mA 1 All voltages are relative to their respective ground. See Figure 2 and Figure 3 for information on maximum allowable current for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating can cause latch-up or permanent damage. 2 Rev. F | Page 9 of 20 ADuM3223/ADuM4223 Data Sheet Table 12. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 Max 565 1131 1131 Unit V peak V peak V peak Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 13. Truth Table ADuM3223/ADuM4223 (Positive Logic)1 DISABLE L VIA Input L VIB Input L VDD1 State Powered VDDA/VDDB State Powered VOA Output L VOB Output L L L H Powered Powered L H L H L Powered Powered H L L H H Powered Powered H H H X X Powered Powered L L L L L Unpowered Powered L L X X X Powered Unpowered L L 1 X = don’t care, L = low, and H = high. Rev. F | Page 10 of 20 Notes Outputs return to the input state within 1 µs of DISABLE = L assertion. Outputs return to the input state within 1 µs of DISABLE = L assertion. Outputs return to the input state within 1 µs of DISABLE = L assertion. Outputs return to the input state within 1 µs of DISABLE = L assertion. Outputs take on default low state within 3 µs of DISABLE = H assertion. Outputs return to the input state within 1 µs of VDD1 power restoration. Outputs return to the input state within 50 µs of VDDA/VDDB power restoration. Data Sheet ADuM3223/ADuM4223 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIB 2 VDD1 3 GND1 4 DISABLE 5 16 VDDA ADuM3223/ ADuM4223 TOP VIEW (Not to Scale) 15 VOA 14 GNDA 13 NC 12 NC NC 6 11 VDDB NC 7 10 VOB VDD1 8 9 GNDB NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 10450-003 VIA 1 Figure 4. Pin Configuration Table 14. ADuM3223/ADuM4223 Pin Function Descriptions Pin No.1 1 6, 7, 12, 13 2 3, 8 4 5 Mnemonic VIA NC VIB VDD1 GND1 DISABLE 9 10 11 14 15 16 GNDB VOB VDDB GNDA VOA VDDA 1 Description Logic Input A. No Connect. Logic Input B. Input Supply Voltage. Ground Reference for Input Logic Signals. Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on default low state within 3 µs of DISABLE = H assertion. Outputs return to the input state within 1 µs of DISABLE = L assertion. Ground Reference for Output B. Output B. Output B Supply Voltage. Ground Reference for Output A. Output A. Output A Supply Voltage. Pin 3 and Pin 8 are internally connected; connecting both pins to supply VDD1 is recommended. For specific layout guidelines, refer to the AN-1109 Application Note, Recommendations for Control of Radiated Emissions with iCoupler Devices. Rev. F | Page 11 of 20 ADuM3223/ADuM4223 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1000 800 CH2 = VO (5V/DIV) GATE CHARGE (nC) VDD2 = 5V 2 600 VDD2 = 8V 400 VDD2 = 10V CH1 = VI (5V/DIV) 200 1 CH1 5.00V Ω M40.0ns 2.50GS/s 100k POINTS A CH1 2.70V 0 10450-105 CH1 5.00V b –820ps b 10.5ns ∆11.3ns a 400 600 800 1000 SWITCHING FREQUENCY (kHz) Figure 8. Typical ADuM4223 Maximum Load vs. Frequency (RG = 1 Ω) Figure 5. Output Waveform for 2 nF Load with 12 V Output Supply a 200 10450-108 VDD2 = 15V 0 3.0 1.40V 11.4V ∆10.0V 2.5 IDD1 CURRENT (mA) CH2 = VOB (5V/DIV) 2 CH1 = VOA (5V/DIV) 2.0 VDD1 = 5V 1.5 VDD1 = 3.3V 1.0 0.5 0 CH2 5.00V Ω M20.0ns 2.50GS/s 100k POINTS A CH1 2.70V 0 10450-106 CH1 5.00V 50 400 40 IDDA , IDDB CURRENT (mA) GATE CHARGE (nC) 0.75 1.00 Figure 9. Typical IDD1 Supply Current vs. Frequency 500 VDD2 = 5V VDD2 = 8V 200 0.50 FREQUENCY (MHz) Figure 6. Output Matching and Rise Time Waveforms for 2 nF Load with 12 V Output Supply 300 0.25 10450-109 1 VDD2 = 10V 100 VDD2 = 15V 30 VDD2 = 10V 20 VDD2 = 5V 10 200 400 600 SWITCHING FREQUENCY (kHz) 800 1000 0 10450-107 0 Figure 7. Typical ADuM3223 Maximum Load vs. Frequency (RG = 1 Ω) 0 0.25 0.50 FREQUENCY (MHz) 0.75 1.00 10450-110 VDD2 = 15V 0 Figure 10. Typical IDDA, IDDB Supply Current vs. Frequency with 2 nF Load Rev. F | Page 12 of 20 Data Sheet ADuM3223/ADuM4223 60 30 25 tDHL 40 RISE/FALL TIME (ns) tDLH 30 20 10 20 40 60 80 100 120 140 Figure 11. Typical Propagation Delay vs. Temperature 10 0 RISE TIME 5 9 7 11 13 15 17 OUTPUT SUPPLY VOLTAGE (V) Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage 5 50 tDHL 40 tDLH 30 20 0 3.0 3.5 4.0 4.5 5.0 5.5 INPUT SUPPLY VOLTAGE (V) Figure 12. Typical Propagation Delay vs. Input Supply Voltage, VDDA, VDDB = 12 V 3 2 PD MATCH tDHL PD MATCH tDLH 1 0 10450-112 10 4 5 7 9 13 11 15 10450-115 PROPAGATION DELAY CH-CH MATCHING (ns) 60 PROPAGATION DELAY (ns) FALL TIME 10450-114 0 10450-111 –20 JUNCTION TEMPERATURE (°C) 17 OUTPUT SUPPLY VOLTAGE (V) Figure 15. Typical Propagation Delay, Channel-to-Channel Matching vs. Output Supply Voltage 60 PROPAGATION DELAY CH-CH MATCHING (ns) 5 50 tDHL 40 tDLH 30 20 10 5 7 9 11 13 15 17 OUTPUT SUPPLY VOLTAGE (V) Figure 13. Typical Propagation Delay vs. Output Supply Voltage, VDD1 = 5 V 4 3 2 PD MATCH tDLH 1 0 –40 10450-113 PROPAGATION DELAY (ns) 15 5 0 –40 0 20 PD MATCH tDHL –20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 10450-116 PROPAGATION DELAY (ns) 50 Figure 16. Typical Propagation Delay, Channel-to-Channel Matching vs. Temperature, VDDA, VDDB = 12 V Rev. F | Page 13 of 20 ADuM3223/ADuM4223 Data Sheet 8 1.4 7 1.2 SOURCE/SINK CURRENT (A) 1.6 VOUT SOURCE RESISTANCE 0.8 VOUT SINK RESISTANCE 0.6 0.4 0 5 4 SOURCE IOUT 3 2 1 4 6 8 10 12 14 16 18 OUTPUT SUPPLY VOLTAGE (V) Figure 17. Typical Output Resistance vs. Output Supply Voltage 0 4 6 8 10 12 14 16 18 OUTPUT SUPPLY VOLTAGE (V) Figure 18. Typical Output Current vs. Output Supply Voltage Rev. F | Page 14 of 20 10450-118 0.2 10450-117 ROUT (Ω) 1.0 SINK IOUT 6 Data Sheet ADuM3223/ADuM4223 APPLICATIONS INFORMATION The ADuM3223/ADuM4223 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins, as shown in Figure 19. Use a small ceramic capacitor with a value between 0.01 μF and 0.1 μF to provide a good high frequency bypass. On the output power supply pin, VDDA or VDDB, it is also recommended to add a 10 μF capacitor to provide the charge required to drive the gate capacitance at the ADuM3223/ADuM4223 outputs. On the output supply pin, the bypass capacitor use of vias should be avoided or multiple vias should be employed to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin should not exceed 5 mm. VIA VDDA VIB VOA VDD1 GNDA GND1 NC DISABLE NC VDDB NC VOB VDD1 GNDB 10450-119 NC Figure 19. Recommended PCB Layout PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. The ADuM3223/ADuM4223 specify tDLH (see Figure 20) as the time between the rising input high logic threshold, VIH, to the output rising 10% threshold. Likewise, the falling propagation delay, tDHL, is defined as the time between the input falling logic low threshold, VIL, and the output falling 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM3223/ADuM4223 component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM3223/ ADuM4223 components operating under the same conditions. THERMAL LIMITATIONS AND SWITCH LOAD CHARACTERISTICS For isolated gate drivers, the necessary separation between the input and output circuits prevents the use of a single thermal pad beneath the part, and heat is, therefore, dissipated mainly through the package pins. Package thermal dissipation limits the performance of switching frequency vs. output load, as illustrated in Figure 7 and Figure 8 for the maximum load capacitance that can be driven with a 1 Ω series gate resistance for different values of output voltage. For example, this curve shows that a typical ADuM3223 can drive a large MOSFET with 140 nC gate charge at 8 V output (which is equivalent to a 17 nF load) up to a frequency of about 300 kHz. Each of the ADuM3223/ADuM4223 isolator outputs has a thermal shutdown protection function, which sets an output to a logic low when the rising junction temperature typically reaches 150°C, and turns back on after the junction temperature falls from the shutdown by approximately 10°C. OUTPUT LOAD CHARACTERISTICS The ADuM3223/ADuM4223 output signals depend on the characteristics of the output load, which is typically an N-channel MOSFET. The driver output response to an N-channel MOSFET load can be modeled with a switch output resistance (RSW), an inductance due to the printed circuit board trace (LTRACE), a series gate resistor (RGATE), and a gate-to-source capacitance (CGS), as shown in Figure 21. VIA 90% ADuM3223/ ADuM4223 VOA RSW RGATE LTRACE VO CGS 10450-006 PC BOARD LAYOUT Figure 21. RLC Model of the Gate of an N-Channel MOSFET OUTPUT 10% VIH INPUT VIL tR tF 10450-005 tDHL tDLH RSW is the switch resistance of the internal ADuM3223/ADuM4223 driver output, which is about 1.1 Ω. RGATE is the intrinsic gate resistance of the MOSFET and any external series resistance. A MOSFET that requires a 4 A gate driver has a typical intrinsic gate resistance of about 1 Ω and a gate-to-source capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the inductance of the printed circuit board trace, typically a value of 5 nH or less for a well-designed layout with a very short and wide connection from the ADuM3223/ADuM4223 output to the gate of the MOSFET. Figure 20. Propagation Delay Parameters Rev. F | Page 15 of 20 ADuM3223/ADuM4223 Data Sheet The following equation defines the Q factor of the RLC circuit, which indicates how the ADuM3223/ADuM4223 output responds to a step change. For a well-damped output, Q is less than 1. Adding a series gate resistance dampens the output response. 1 × (R SW + R GATE ) LTRACE C GS In Figure 5, the ADuM3223/ADuM4223 output waveforms for a 12 V output are shown for a CGS of 2 nF. Note the small amount of ringing of the output in Figure 5 with CGS of 2 nF, RSW of 1.1 Ω, RGATE of 0 Ω, and a calculated Q factor of 0.75, where less than 1 is desired for good damping. Output ringing can be reduced by adding a series gate resistance to dampen the response. For applications of less than 1 nF load, it is recommended to add a series gate resistor of about 2 Ω to 5 Ω. BOOT-STRAPPED HALF-BRIDGE OPERATION The ADuM3223/ADuM4223 are well suited to the operation of two output gate signals that are referenced to separate grounds, as in the case of a half-bridge configuration. Because isolated auxiliary supplies are often expensive, it is beneficial to reduce the amount of supplies. One method to perform this is to use a boot-strap configuration for the high-side supply of the ADuM3223/ADuM4223. In this topology, the decoupling capacitor, CA, acts as the energy storage for the high-side supply, and is filled whenever the low-side switch is closed, bringing GNDA to GNDB. During the charging time of CA, the dv/dt of the VDDA voltage must be controlled to reduce the possibility of glitches on the output. Keeping the dv/dt below 10 V/µs is recommended for the ADuM3223/ADuM4223. This can be controlled by introducing a series resistance, RBOOT, into the charging path of CA. As an example, if VAUX is 12 V, CA has a total capacitance of 10 µF, and the forward voltage drop of the bootstrap diode is 1 V: RBOOT = Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 1 µs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 3 µs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. In addition, the outputs are in a low default state while the power is coming up before the UVLO threshold is crossed. The ADuM3223/ADuM4223 is immune to external magnetic fields. The limitation on the ADuM3223/ADuM4223 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM3223/ADuM4223 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt) ∑π rn2, n = 1, 2, ... , N where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). 12 V − 1 V VAUX − VD BOOT = = 0.11 Ω dv 10 μF × 10 V/μ s C A × dt max VIA VIB VPRIM VPRIM VDD1 CDD1 1 GND1 DISABLE NC VPRIM NC VDD1 1 2 ADuM3223/ ADuM4223 ENCODE 16 DECODE 15 3 14 4 13 5 12 6 11 7 ENCODE DECODE 10 9 8 VDDA RBOOT VOA REXT_A VDBOOT VBUS DBOOT CA GNDA NC NC VDDB VOB VAUX REXT_B CB GNDB 2 NC = NO CONNECT Figure 22. Circuit of Bootstrapped Half-Bridge Operation Rev. F | Page 16 of 20 10450-222 Q= DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Data Sheet ADuM3223/ADuM4223 Given the geometry of the receiving coil in the ADuM3223/ ADuM4223 and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 23. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 10 1 0.1 0.01 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 23. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.08 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and had the worst-case polarity), the received pulse is reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3223/ADuM4223 transformers. Figure 24 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM3223/ADuM4223 are immune and only can be affected by extremely large currents operated at a high frequency and very close to the component. For the 1 MHz example, a 0.2 kA current must be placed 5 mm away from the ADuM3223/ADuM4223 to affect the component’s operation. DISTANCE = 1m 100 where: CEST = CISS × 5. fS is the switching frequency. Alternately, use the gate charge to obtain a more precise value for PDISS. PDISS = QGATE × VDDx × fS where: QGATE is the gate charge for the MOSFET. fS is the switching frequency. This power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, RGON and RGOFF. The ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the ADuM3223/ADuM4223 chips. PDISS_IC = PDISS × (RDSON_P/(REXT_X + RDSON_P) + RDSON_N/(REXT_X + RDSON_N)) Taking the power dissipation found inside the chip and multiplying it by θJA gives the rise above ambient temperature that the ADuM3223/ADuM4223 experience per channel. TJ = θJA × 2 × PDISS_IC + TAMB For the device to remain within specification, TJ must not exceed 125°C. If TJ exceeds 150°C (typical), the device enters TSD. To calculate the total supply current, the supply currents for each input and output channel corresponding to IDD1, IDDA, and IDDB are calculated and totaled. 10 Figure 9 provides total input IDD1 supply current as a function of data rate for both input channels. Figure 10 provides total IDDA or IDDB supply current as a function of data rate for both outputs loaded with 2 nF capacitance. DISTANCE = 100mm DISTANCE = 5mm 0.1 0.01 1k During the driving of a MOSFET gate, the driver must dissipate power. This power is not insignificant and can lead to thermal shutdown (TSD) if considerations are not made. The gate of a MOSFET can be simulated approximately as a capacitive load. Due to Miller capacitance and other nonlinearities, it is common practice to take the stated input capacitance, CISS, of a given MOSFET and multiply it by a factor of 5 to arrive at a conservative estimate to approximate the load being driven. With this value, the estimated total power dissipation per channel due to switching action is given by 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 10450-123 MAXIMUM ALLOWABLE CURRENT (kA) 1k 1 The supply current at a given channel of the ADuM3223/ ADuM4223 isolator is a function of the supply voltage, channel data rate, and channel output load. PDISS = CEST × (VDDx)2 × fS 10450-122 0.001 1k POWER CONSUMPTION Figure 24. Maximum Allowable Current for Various Current-to-ADuM3223/ADuM4223 Spacings Rev. F | Page 17 of 20 ADuM3223/ADuM4223 Data Sheet The values shown in Table 12 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM3223/ADuM4223 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 25, Figure 26, and Figure 27 illustrate these different isolation voltage waveforms. A bipolar ac voltage environment is the worst case for the iCoupler products and is the 50-year operating lifetime that Analog Devices recommends for maximum working voltage. In the case of Rev. F | Page 18 of 20 RATED PEAK VOLTAGE 10450-009 Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. Note that the voltage presented in Figure 26 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 0V Figure 25. Bipolar AC Waveform RATED PEAK VOLTAGE 10450-010 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3223/ ADuM4223. unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. Any crossinsulation voltage waveform that does not conform to Figure 26 or Figure 27 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 12. 0V Figure 26. Unipolar AC Waveform RATED PEAK VOLTAGE 10450-011 INSULATION LIFETIME 0V Figure 27. DC Waveform Data Sheet ADuM3223/ADuM4223 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 9 16 4.00 (0.1575) 3.80 (0.1496) 1 8 1.27 (0.0500) BSC 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 6.20 (0.2441) 5.80 (0.2283) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AC 060606-A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 28. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 29. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. F | Page 19 of 20 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 ADuM3223/ADuM4223 Data Sheet ORDERING GUIDE 1, 2 Model ADuM3223ARZ ADuM3223ARZ-RL7 ADuM3223BRZ ADuM3223BRZ-RL7 ADuM3223CRZ ADuM3223CRZ-RL7 ADuM3223WARZ ADuM3223WARZ-RL7 ADuM3223WBRZ ADuM3223WBRZ-RL7 ADuM3223WCRZ ADuM3223WCRZ-RL7 ADuM4223ARWZ ADuM4223ARWZ-RL ADuM4223BRWZ ADuM4223BRWZ-RL ADuM4223CRWZ ADuM4223CRWZ-RL ADuM4223WARWZ ADuM4223WARWZ-RL ADuM4223WBRWZ ADuM4223WBRWZ-RL ADuM4223WCRWZ ADuM4223WCRWZ-RL EVAL-ADuM3223AEBZ EVAL-ADuM4223AEBZ 1 2 No. of Channels 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Output Peak Current (A) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Minimum Output Voltage (V) 4.5 4.5 7.5 7.5 11.5 11.5 4.5 4.5 7.5 7.5 11.5 11.5 4.5 4.5 7.5 7.5 11.5 11.5 4.5 4.5 7.5 7.5 11.5 11.5 4.5 4.5 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 7” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13” Tape and Reel ADuM3223 evaluation board ADuM4223 evaluation board Package Option R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16 R-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 Ordering Quantity 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADuM3223W and ADuM4223W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10450-0-7/15(F) Rev. F | Page 20 of 20