AD ADRF6801

750 MHz to 1150 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
ADRF6801
FEATURES
GENERAL DESCRIPTION
IQ demodulator with integrated fractional-N PLL
LO frequency range: 750 MHz to 1150 MHz
Input P1dB: 12.5 dBm
Input IP3: 25 dBm
Noise figure (DSB): 14.3 dB
Voltage conversion gain: 5.1 dB
Quadrature demodulation accuracy
Phase accuracy: 0.3°
Amplitude accuracy: 0.05 dB
Baseband demodulation: 275 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
The ADRF6801 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 3.0 GHz to 4.6 GHz. A
divide-by-4 quadrature divider divides the output frequency of
the VCO down to the required local oscillator (LO) frequency
to drive the mixers in quadrature. Additionally, an output buffer
can be enabled that generates an fVCO/2 signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
The ADRF6801 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
GND
VCCLO VCCLO
35
34
17
LOSEL
IBBP
36
33
BUFFER
CTRL
IBBN GND
32
31
ADRF6801
30 GND
LON 37
29 VCCBB
BUFFER
28 GND
LOP 38
27 VCCRF
FRACTION MODULUS
REG
GND 11
BUFFER
INTEGER
REG
MUX
DATA 12
SPI
INTERFACE
QUAD
÷2
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
LE 14
GND 15
PRESCALER
÷2
N COUNTER
26 RFIN
VCO
CORE
25 GNDRF
×2
REFIN 6
GND
÷2
24 GND
MUX
7
–
PHASE
+ FREQUENCY
DETECTOR
TEMP
SENSOR
÷4
3.3V LDO
MUXOUT 8
1
2
10
16
VCC1
DECL3
VCC2
GND
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
3
4
5
CPOUT GND RSET
23 GND
22 VCCBB
2.5V LDO
VCO LDO
9
39
40
DECL2
VTUNE
DECL1
21 GND
18
19
20
QBBP QBBN GND
09576-001
CLK 13
DIVIDER
÷1
OR
÷2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADRF6801
TABLE OF CONTENTS
Features .............................................................................................. 1 Bias Circuitry .............................................................................. 14 Applications....................................................................................... 1 Register Structure....................................................................... 14 General Description ......................................................................... 1 Applications Information .............................................................. 21 Functional Block Diagram .............................................................. 1 Basic Connections...................................................................... 21 Revision History ............................................................................... 2 Supply Connections ................................................................... 21 Specifications..................................................................................... 3 Synthesizer Connections ........................................................... 21 Timing Characteristics ................................................................ 5 I/Q Output Connections ........................................................... 22 Absolute Maximum Ratings............................................................ 6 RF Input Connections ............................................................... 22 ESD Caution.................................................................................. 6 Charge Pump/VTUNE Connections ...................................... 22 Pin Configuration and Function Descriptions............................. 7 LO Select Interface ..................................................................... 22 Typical Performance Characteristics ............................................. 9 External LO Interface ................................................................ 22 Synthesizer/PLL .......................................................................... 12 Setting the Frequency of the PLL ............................................. 22 Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13 Register Programming............................................................... 22 Circuit Description......................................................................... 14 Evaluation Board Layout and Thermal Grounding................... 24 LO Quadrature Drive................................................................. 14 ADRF6801 Software .................................................................. 28 V-to-I Converter......................................................................... 14 Characterization Setups................................................................. 30 Mixers .......................................................................................... 14 Outline Dimensions ....................................................................... 34 Emitter Follower Buffers ........................................................... 14 Ordering Guide .......................................................................... 34 EVM Measurements .................................................................. 23 REVISION HISTORY
1/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADRF6801
SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 900 MHz, fBB = 4.5 MHz, RLOAD = 450 Ω differential, all register and PLL
settings use the recommended values shown in the Register Structure section, unless otherwise noted.
Table 1.
Parameter
RF INPUT AT 900 MHz
Internal LO Frequency Range
Input Return Loss
Input P1dB
Second-Order Input Intercept (IIP2)
Third-Order Input Intercept (IIP3)
Noise Figure
LO-to-RF Leakage
I/Q BASEBAND OUTPUTS
Voltage Conversion Gain
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset (Differential)
Output Common-Mode Voltage
Gain Flatness
Maximum Output Swing
Maximum Output Current
LO INPUT/OUTPUT
Output Level
Input Level
Input Impedance
VCO Operating Frequency
SYNTHESIZER SPECIFICATIONS
Channel Spacing
PLL Bandwidth
SPURS
Reference Spurs
Test Conditions/Comments
RFIN pins
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
Measured at 900 MHz
Min
Rev. 0 | Page 3 of 36
Max
Unit
1125
1150
<−20
12.5
>65
25
14.3
18.9
−75
MHz
MHz
dB
dBm
dBm
dBm
dB
dB
dBm
5.1
275
0.3
0.05
±5
VPOS − 2.4
0.2
4
2.4
12
dB
MHz
Degrees
dB
mV
V
dB p-p
V p-p
V p-p
mA p-p
−2.5
dBm
0
50
dBm
Ω
MHz
MHz
750
750
−5 dBm each tone
−5 dBm each tone
Double sideband from RF to either I or Q output
With a −10 dBm interferer 5 MHz away
At 1×LO frequency, 50 Ω termination at the RF port
IBBP, IBBN, QBBP, QBBN pins
450 Ω differential load across IBBP, IBBN (or QBBP, QBBN)
1 V p-p signal 3 dB bandwidth
Any 5 MHz (<100 MHz)
Differential 450 Ω load
Differential 200 Ω load
Each pin
LOP, LON
Into a differential 50 Ω load, LO buffer enabled (LO
frequency = 900 MHz, output frequency = 1800 MHz)
Externally applied 2×LO, PLL disabled
Externally applied 2×LO, PLL disabled
With VCO amplitude = 63 (R6 [DB15 to DB10])
With VCO amplitude = 24 (R6 [DB15 to DB10])
All synthesizer specifications measured with
recommended settings provided in Figure 33 through
Figure 39
fPFD = 26 MHz; modulus = 2047
Can be adjusted with off-chip loop filter component
values and RSET
fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
fREF = 26 MHz, fPFD = 26 MHz
fPFD/2
fPFD × 2
fPFD × 3
Typ
3000
3000
4500
4600
25
130
kHz
kHz
−91.6
−107.8
−89.1
−94.2
dBc
dBc
dBc
dBc
ADRF6801
Parameter
PHASE NOISE (USING 130 kHz LOOP FILTER)
Integrated Phase Noise
PHASE NOISE (USING 2.5 kHz LOOP FILTER)
PLL FIGURE OF MERIT (FOM)
Phase Detector Frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
MUXOUT Output Level
REFOUT Duty Cycle
CHARGE PUMP
Pump Current
Output Compliance Range
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
Voltage Range (5 V)
Supply Current (5 V)
Supply Current (5 V)
Test Conditions/Comments
fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset
10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured
at BB outputs with fBB = 50 MHz
1 kHz offset
10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
Measured with fREF = 26 MHz, fPFD = 26 MHz
Measured with fREF = 104 MHz, fPFD = 26 MHz
Min
20
REFIN, MUXOUT pins
Usable range
Typ
Max
−99.5
−107.8
−106.6
−126.7
−131.7
−143.5
−150.5
0.16
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
−71.3
−88.3
−114.1
−129.5
−138.6
−150.2
−150.3
−215.4
−220.9
26
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz/Hz
dBc/Hz/Hz
MHz
10
40
160
4
VOL (lock detect output selected)
VOH (lock detect output selected)
Unit
0.25
2.7
50
500
MHz
pF
V
V
%
μA
V
1
2.8
1.4
0
3.3
0.7
V
V
μA
pF
5.25
V
mA
mA
mA
CLK, DATA, LE pins
0.1
5
VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
4.75
Normal Rx mode, internal LO
Rx mode, internal LO with LO buffer enabled
Rx mode, using external LO input (internal VCO, PLL shut
down)
Power-down mode
Rev. 0 | Page 4 of 36
5
262
288
157
20
mA
ADRF6801
TIMING CHARACTERISTICS
VS = 5 V, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
t4
t5
CLOCK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
09576-002
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 36
ADRF6801
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VCC1, VCC2, VCCLO,
VCCBB, and VCCRF (VS1)
Digital I/O, CLK, DATA, and LE
RFIN
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
−0.5 V to +5.5 V
−0.3 V to +3.6 V
16 dBm
30°C/W
150°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 36
ADRF6801
VCO
LDO
31 GND
32 IBBN
33 IBBP
34 VCCLO
35 GND
36 LOSEL
37 LON
38 LOP
39 VTUNE
40 DECL1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BUFFER
CTRL
30 GND
VCC1 1
29 VCCBB
DECL3 2
SCALE
PHASE DETECTOR
AND
CHARGE PUMP
CPOUT 3
28 GND
BLEED
GND 4
27 VCCRF
DIV
CTRL
26 RFIN
RSET 5
VCO
BAND
×2
REFIN 6
÷2
MUX
GND 7
ENABLE
6
CURRENT
CAL/SET 6
VCO
3000MHz
TO
4600MHz
PROGRAMABLE
DIVIDER
÷4
MUX
DIV
÷1
OR
÷2
QUADRATURE
÷2
25 GNDRF
24 GND
PRESCALER
÷2
23 GND
MUXOUT 8
22 VCCBB
DECL2 9
2.5V
LDO
THIRD-ORDER
SDM
21 GND
VCC2 10
FRACTION
MODULUS
INTEGER
08817-003
GND 20
QBBN 19
QBBP 18
VCCLO 17
GND 16
GND 15
LE 14
CLK 13
DATA 12
GND 11
SERIAL PORT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4, 7, 11, 15, 16, 20, 21,
23, 24, 28, 30, 31, 35
Mnemonic
VCC1
DECL3
CPOUT
GND
Description
The 5 V Power Supply Pin for VCO and PLL (VCC1).
Decoupling Node for the 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
Connect these pins to a low impedance ground plane.
Rev. 0 | Page 7 of 36
ADRF6801
Pin No.
5
Mnemonic
RSET
6
8
REFIN
MUXOUT
9
10
12
13
DECL2
VCC2
DATA
CLK
14
LE
17, 34
18, 19
22, 29
25
26
27
32, 33
36
VCCLO
QBBP, QBBN
VCCBB
GNDRF
RFIN
VCCRF
IBBN, IBBP
LOSEL
37, 38
LON, LOP
39
VTUNE
40
DECL1
EP
Description
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this
mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents
(INOMINAL) can be externally tweaked according to the following equation where the resulting value is in
units of ohms.
⎡ 217 .4 × I CP ⎤
RSET = ⎢
⎥ − 37 .8
⎣ I NOMINAL ⎦
Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz.
Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register.
Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
The 5 V power supply pin for the 2.5 V LDO.
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit
word.
The 5 V Power Supply for the LO Path Blocks.
Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks.
Ground Return for RF Input Balun.
Single-Ended, Ground Referenced 50 Ω, RF Input.
The 5 V Power Supply for the RF Input Section of the Demodulator Blocks.
Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is
set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The
externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set
low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set
high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and
the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds
to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
Connect a 10 μF capacitor between this pin and ground as close to the device as possible
because this pin serves as the VCO supply and loop filter reference.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. 0 | Page 8 of 36
ADRF6801
TYPICAL PERFORMANCE CHARACTERISTICS
80
16
14
IP1dB
75
12
INPUT IP2 (dBm)
TA = +85°C
TA = +25°C
TA = –40°C
10
8
6
GAIN
70
TA = +85°C
TA = +25°C
TA = –40°C
65
I CHANNEL
Q CHANNEL
60
4
55
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
50
750
800
1150
23
1100
1150
1100
1150
16
15
14
13
19
12
17
11
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
10
750
09576-005
800
TA = +85°C
TA = +25°C
TA = –40°C
17
800
850
900
950
1000
1050
LO FREQUENCY (MHz)
Figure 5. Input IP3 vs. LO Frequency
09576-008
NOISE FIGURE (dB)
INPUT IP3 (dBm)
25
21
Figure 8. Noise Figure vs. LO Frequency
5
IQ QUADRATURE PHASE ERROR (Degrees)
1.0
0.8
TA = +85°C
TA = +25°C
TA = –40°C
0.2
0
–0.2
–0.4
–0.6
–0.8
800
850
900
950
1000
1050
1100
LO FREQUENCY (MHz)
1150
09576-006
IQ GAIN MISMATCH (dB)
1100
18
27
–1.0
750
1050
19
TA = +85°C
TA = +25°C
TA = –40°C
29
0.4
1000
20
33
0.6
950
Figure 7. Input IP2 vs. LO Frequency
35
15
750
900
LO FREQUENCY (MHz)
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
31
850
Figure 6. IQ Gain Mismatch vs. LO Frequency
4
TA = +85°C
TA = +25°C
TA = –40°C
3
2
1
0
–1
–2
–3
–4
–5
750
800
850
900
950
1000
1050
LO FREQUENCY (MHz)
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
Rev. 0 | Page 9 of 36
09576-009
0
750
09576-007
2
09576-004
CONVERSION GAIN (dB) AND INPUT P1dB (dBm)
VS = 5 V, TA = 25°C, unless otherwise noted. LO = 750 MHz to 1150 MHz.
–50
1
–55
0
NORMALIZED BASEBAND
FREQUENCY RESPONSE (dB)
–60
–65
–70
–75
–80
–2
–3
–4
–5
–6
–85
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
–7
09576-010
–90
750
–1
1
10
09576-013
LO-TO-RF FEEDTHROUGH (dBm)
ADRF6801
100
BASEBAND FREQUENCY (MHz)
Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
Figure 13. Normalized Baseband Frequency Response vs. Baseband
Frequency
–35
80
–40
70
–50
–55
–60
–65
–70
–75
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
TA = +85°C
TA = +25°C
TA = –40°C
50
I CHANNEL
Q CHANNEL
40
30
IIP3
20
IP1dB
10
0
5
10
15
20
25
30
35
40
45
50
BASEBAND FREQUENCY (MHz)
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. Baseband Frequency
–30
34
32
–35
30
–40
NOISE FIGURE (dB)
28
–45
–50
–55
–60
26
24
22
20
18
16
14
–65
800
850
900
950
1000
1050
1100
RF FREQUENCY (MHz)
1150
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
10
–35
–30
–25
–20
–15
–10
–5
0
INPUT BLOCKER POWER (dBm)
Figure 15. Noise Figure vs. Input Blocker Level,
fLO = 900 MHz (RF Blocker 5 MHz Offset)
Rev. 0 | Page 10 of 36
5
09576-015
12
–70
750
09576-012
RF-TO-BB FEEDTHROUGH (dBc)
60
09576-014
INPUT P1dB (dBm), INPUT IP2 (dBm),
AND INPUT IP3 (dBm)
–45
09576-011
LO-TO-BB FEEDTHROUGH (dBV rms)
IIP2
2.0
–5
1.9
–10
1.8
–15
–20
–25
1.7
1.6
1.5
–30
1.4
–35
1.3
–40
750
800
850
900
950
1000
1050
1100
1150
RF FREQUENCY (MHz)
1.2
–40
–15
Figure 16. RF Input Return Loss vs. RF Frequency
60
85
3.5
–2
3.0
–4
VTUNE VOLTAGE (V)
–6
–8
–10
TA = +85°C
TA = +25°C
TA = –40°C
2.5
2.0
1.5
12
1.0
–16
1500
1600
1700
1800
1900
2000
2100
2200
2300
LOP, LON OUTPUT FREQUENCY (MHz)
09576-017
–14
Figure 17. LO Output Return Loss vs. LO Output Frequency, LO Output
Enabled (1500 MHz to 2300 MHz), Measured through TC1-1-13 Balun
400
380
360
TA = +85°C
TA = +25°C
TA = –40°C
340
320
300
280
260
240
200
750
800
850
900
950
1000
1050
1100
LO FREQUENCY (MHz)
1150
09576-018
220
Figure 18. 5 V Supply Currents vs. LO Frequency,
LO Output Enabled
Rev. 0 | Page 11 of 36
0.5
750
800
850
900
950
1000
1050
LO FREQUENCY (MHz)
Figure 20. VTUNE vs. LO Frequency
1100
1150
09576-020
LOP, LON DIFFERENTIAL
OUTPUT RETURN LOSS (dB)
35
Figure 19. VPTAT vs. Temperature
0
CURRENT (mA)
10
TEMPERATURE (°C)
09576-019
VPTAT VOLTAGE (V)
0
09576-016
RF INPUT RETURN LOSS (dB)
ADRF6801
ADRF6801
SYNTHESIZER/PLL
VS = 5 V. See the Register Structure section for recommended settings used. External loop filter bandwidths of ~130 kHz and 2.5 kHz
used (see plots within this section for annotations), fREF = fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
–40
1.0
INTEGRATED PHASE NOISE (°rms)
PHASE NOISE (dBc/Hz)
–80
130kHz LOOP FILTER
BANDWIDTH
–100
TA = +85°C
TA = +25°C
TA = –40°C
0.9
TA = +85°C
TA = +25°C
TA = –40°C
–60
–120
2.5kHz LOOP FILTER
BANDWIDTH
–140
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
0
750
09576-021
–160
Figure 21. Phase Noise vs. Offset Frequency, fLO = 900 MHz, Shown for Loop
Filter Bandwidths of 2.5 kHz and 130 kHz
950
1 × PFD FREQUENCY
3 × PFD FREQUENCY
0.5 × PFD FREQUENCY
–70
–85
–90
–95
–100
1100
1150
10kHz
OFFSET
–90
1kHz OFFSET
–110
130kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
10kHz
OFFSET
–130
TA = +85°C
TA = +25°C
TA = –40°C
5MHz
OFFSET
–150
900
950
1000
1050
1100
1150
Figure 22. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
5MHz
OFFSET
800
850
900
950
1000
1050
LO FREQUENCY (MHz)
1100
1150
09576-025
850
–170
750
09576-022
800
LO FREQUENCY (MHz)
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets),
Shown for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
–90
TA = +85°C
TA = +25°C
TA = –40°C
2 × PFD FREQUENCY
4 × PFD FREQUENCY
–100
PHASE NOISE (dBc/Hz)
–80
–85
–90
–95
–100
100kHz OFFSET
–110
100kHz OFFSET
–120
1MHz OFFSET
–130
–140
1MHz OFFSET
–105
–150
–110
750
–160
750
800
850
900
950
1000
1050
1100
1150
LO FREQUENCY (MHz)
Figure 23. PLL Reference Spurs vs. LO Frequency, Using Loop Filter
Bandwidth of 130 kHz
09576-023
130kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
800
850
900
950
1000
LO FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40°C
1050
1100
1150
09576-026
–70
–75
1050
1kHz
OFFSET
–80
–110
750
1000
–50
TA = +85°C
TA = +25°C
TA = –40°C
PHASE NOISE (dBc/Hz)
PLL REFERENCE SPURS (dBc)
900
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted), Using
Loop Filter Bandwidth of 130 kHz
–105
PLL REFERENCE SPURS (dBc)
850
LO FREQUENCY (MHz)
–70
–75
800
09576-024
0.1
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets), Shown
for Loop Filter Bandwidths of 2.5 kHz and 130 kHz
Rev. 0 | Page 12 of 36
ADRF6801
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
TA = +85°C
TA = +25°C
TA = –40°C
70
60
IP1dB
50
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
GAIN (dB) AND INPUT P1dB (dBm)
90
TA = +85°C
TA = +25°C
TA = –40°C
80
70
I CHANNEL
Q CHANNEL
60
50
40
30
20
10
0
60
62
64
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
TA = +85°C
TA = +25°C
TA = –40°C
I CHANNEL
Q CHANNEL
50
40
30
20
10
0
15
17
19
21
23
25
27
29
31
33
35
INPUT IP3 (dBm)
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
60
50
40
30
20
10
–0.3
–0.2
–0.1
0
0.1
80
18
20
22
24
2
3
4
5
80
70
TA = +85°C
TA = +25°C
TA = –40°C
60
50
40
30
20
10
6
8
10
12
14
16
NOISE FIGURE (dB)
0.2
IQ GAIN MISMATCH (dB)
0.3
0.4
0.5
09576-029
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
TA = +85°C
TA = +25°C
TA = –40°C
–0.4
78
Figure 31. Noise Figure
90
0
–0.5
76
90
4
100
70
74
100
Figure 28. Input IP3
80
72
0
09576-028
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
90
60
70
Figure 30. Input IP2
100
70
68
INPUT IP2 (dBm)
Figure 27. Gain and Input P1dB
80
66
09576-030
GAIN
80
09576-131
90
100
09576-132
100
09576-027
CUMULATIVE DISTRIBUTION PERCENTAGE (%)
VS = 5 V, fLO = 900 MHz, fBB = 4.5 MHz.
Figure 29. IQ Gain Mismatch
100
90
80
70
60
TA = +85°C
TA = +25°C
TA = –40°C
50
40
30
20
10
0
–5
–4
–3
–2
–1
0
1
IQ QUADRATURE PHASE ERROR (Degrees)
Figure 32. IQ Quadrature Phase Error
Rev. 0 | Page 13 of 36
ADRF6801
CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
The ADRF6801 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low output
noise floor for excellent dynamic range.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The RF input signal is applied to an on-chip balun which then
provides both a ground referenced, 50 Ω single-ended input
impedance and a differential voltage output to a V-to-I converter
that converts the differential voltages to differential output currents.
These currents are then applied to the emitters of the Gilbert
cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals
off chip. The output impedance is set by on-chip 12 Ω series
resistors that yield a 24 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than
with a high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter followers are set
from VCCBB via the voltage drop across the mixer load resistors,
the VBE of the output emitter follower, and the voltage drop
across the 12 Ω series resistor.
BIAS CIRCUITRY
There are several band gap reference circuits and three low
dropout regulators (LDOs) in the ADRF6801 that generate the
reference currents and voltages used by different sections. The
first of the LDOs is the 2.5 V LDO, which is always active and
provides the 2.5 V supply rail used by the internal digital logic
blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)
for the user to provide external decoupling.
The second LDO is the VCO LDO, which acts as the positive
supply rail for the internal VCO. The VCO LDO output is
connected to DECL2 (Pin 40) for the user to provide external
decoupling. The VCO LDO can be powered down by setting
Register 6, DB18 = 0, which allows the user to save power when
not using the VCO.
The third LDO is the 3.3 V LDO, which acts as the 3.3 V
positive supply rail for the reference input, phase frequency
detector, and charge pump circuitry. The 3.3 V LDO output is
connected to DECL3 (Pin 2) for the user to provide external
decoupling. The 3.3 V LDO can be powered down by setting
Register 6, DB19 = 0, which allows the user to save power when
not using the VCO. The demodulator also has a bias circuit that
supplies bias current for the mixer V-to-I stage, which then sets
the bias for the mixer core. The demodulator bias cell can also
be shut down by setting Register 5, DB7 = 0.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable
features through a 3-wire SPI control interface that is used to
program the seven internal registers. The minimum delay and
hold times are shown in the timing diagram (see Figure 2). The
SPI provides digital control of the internal PLL/VCO as well as
several other features related to the demodulator core, on-chip
referencing, and available system monitoring functions. The
MUXOUT pin provides a convenient, single-pin monitor output
signal that can be used to deliver a PLL lock-detect signal or an
internal voltage proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the
ADRF6801 is initialized at a given frequency. This calibration is run
automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 7 and then programming the registers in descending
order, ending with Register 0, is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
Rev. 0 | Page 14 of 36
ADRF6801
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
0
0
0
0
0
0
0
0
0
0
0
0
0
DM
INTEGER DIVIDE RATIO
CONTROL BITS
DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ID6
ID4
ID3
ID2
ID1
ID0
C3(0)
C2(0)
C1(0)
ID5
DM
DIVIDE MODE
0
1
FRACTIONAL (DEFAULT)
INTEGER
DIVIDE RATIO
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
1
0
1
0
1
21 (INTEGER MODE ONLY)
0
0
1
0
1
1
0
22 (INTEGER MODE ONLY)
0
0
1
0
1
1
1
23 (INTEGER MODE ONLY)
0
0
1
1
0
0
0
24
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
1
0
0
0
56 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
0
1
1
1
119
1
1
1
1
0
0
0
120 (INTEGER MODE ONLY)
1
1
1
1
0
0
1
121 (INTEGER MODE ONLY)
1
1
1
1
0
1
0
122 (INTEGER MODE ONLY)
1
1
1
1
0
1
1
123 (INTEGER MODE ONLY)
09576-031
DIVIDE
MODE
Figure 33. Integer Divide Control Register (R0)
Register 0—Integer Divide Control
With R0[2:0] set to 000, the on-chip integer divide control register
is programmed as shown in Figure 33. The internal VCO
frequency (fVCO) equation is
(1)
fVCO = fPFD × (INT + (FRAC/MOD)) × 2
where:
fVCO is the output frequency of the internal VCO.
INT is the preset integer divide ratio value (21 to 123 for integer
mode, 24 to 119 for fractional mode).
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).
The integer divide ratio sets the INT value in Equation 1. The
INT, FRAC, and MOD values make it possible to generate output
frequencies that are spaced by fractions of the PFD frequency.
Note that the demodulator LO frequency is given by fLO = fVCO/4.
Divide Mode
Divide mode determines whether fractional mode or integer mode
is used. In integer mode, the VCO output frequency, fVCO, is
calculated by
Rev. 0 | Page 15 of 36
fVCO = fPFD × (INT) × 2
(2)
ADRF6801
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO
0
0
CONTROL BITS
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
C3(0)
C2(0)
C1(1)
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MODULUS VALUE
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
2
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
0
0
0
0
0
0
0
0
0
1536 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
1
1
1
1
1
1
1
1
1
1
1
2047
09576-032
DB23 DB22
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
CONTROL BITS
FRACTIONAL DIVIDE RATIO
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
C3(0)
C2(1)
C1(0)
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
FRACTIONAL VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
0
1
1
0
0
0
0
0
0
0
0
768 (DEFAULT)
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
09576-033
FD10
<MOD
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
Figure 35. Fractional Divide Control Register (R2)
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ-Δ modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER
DITHER RESTART VALUE
ENABLE
DB20
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DEN
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5
DEN
0
1
CONTROL BITS
DB7 DB6 DB5
DV4 DV3 DV2
DB4 DB3 DB2 DB1 DB0
DV1 DV0 C3(0) C2(1) C1(1)
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DITH1
0
0
DITH0
0
1
DITHER MAGNITUDE
15 (DEFAULT)
7
1
0
3
1
1
1 (RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9
DV8
DV7
DV6
DV5
DV4
DV3
DV2
DV1
DV0
DITHER RESTART
VALUE
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
1
...
...
1
0x00001 (DEFAULT)
...
...
0x1FFFF
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
0
...
...
1
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Rev. 0 | Page 16 of 36
09576-034
DB23
0
DITHER
MAGNITUDE
DB22
DB21
DITH1
DITH0
ADRF6801
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by
Register 4—Charge Pump, PFD, and Reference Path
Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
Figure 37.
ΔΦ [deg] = 22 . 5
The charge pump current is controlled by the base charge
pump current (ICP, BASE) and the value of the charge pump
current multiplier (ICP, MULT).
θ PFD , OFS
I CP , MULT
Finally, the phase offset can be either positive or negative
depending on the value of the DB17 bit in Register 4.
The base charge pump current can be set using an internal or
external resistor (according to Bit DB18 of Register 4). When
using an external resistor, the value of ICP, BASE can be varied
according to
⎡ 217 . 4 × I CP , BASE ⎤
R SET [Ω ] = ⎢
⎥ − 37 . 8
250
⎣
⎦
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, or 4) of the charge pump base current. The
multiplying value (ICP, MULT) is equal to 1 plus the value of the
DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6801 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals. The
default mode provides a lock-detect output that allows users to
verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
described in Figure 37.
Rev. 0 | Page 17 of 36
ADRF6801
CHARGE
PUMP
REF
INPUT REF
PATH
SOURCE
OUPUT MUX
SOURCE
PDF
PHASE
OFFSET
POLARITY
CHARGE
PUMP
CURRENT
MULTIPLIER
PFD PHASE OFFSET
MULTIPLIER VALUE
CP
CNTL
SRC
CHARGE
PUMP
CONTROL
PFD ANTIBACKLASH
DELAY
PFD EDGE
SENSITIVITY
CONTROL BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RMS2
RMS1
RMS0
RS1
RS0
CPM
CPBD
CPB4
CPB3 CPB2 CPB1
CPB0
CPP1
CPP0
CPS
CPC1
CPC0
PE1
PE0
PAB1
PAB0
C3(1)
C2(0)
C1(0)
PAB1 PAB0 PFD ANTIBACKLASH
DELAY
0
0
0
1
1
1
0
1
0ns (DEFAULT,
RECOMMENDED)
0.5ns
0.75ns
0.9ns
PE0
REFERENCE PATH EDGE
SENSITIVITY
0
1
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
PE1
0
1
DIVIDER PATH EDGE
SENSITIVITY
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
CHARGE PUMP
CPC1 CPC0 CONTROL
BOTH ON
0
0
PUMP DOWN
0
1
PUMP UP
1
0
TRISTATE (DEFAULT)
1
1
CPS
CHARGE PUMP CONTROL SOURCE
0
1
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)
CONTROL FROM PFD (DEFAULT)
CHARGE PUMP
CPP1 CPP0 CURRENT MULTIPLIER
0
0
1
1
CPM
0
1
0
1
0
1
1
2 (DEFAULT, RECOMMENDED)
3
4
CPB4 CPB3 CPB2 CPB1 CPB0
PFD PHASE OFFSET MULTIPLIER
0
0
...
0
...
0
...
1
0 × 22.5°/ICP, MULT
1 × 22.5°/ICP, MULT
...
6 × 22.5°/ICP, MULT (RECOMMENDED)
...
10 × 22.5°/ICP, MULT (DEFAULT)
...
31 × 22.5°/ICP, MULT
0
0
...
0
...
1
...
1
0
0
...
1
...
0
...
1
0
0
...
1
...
1
...
1
0
1
...
0
...
0
...
1
CPBD
PFD PHASE OFFSET POLARITY
0
1
NEGATIVE
POSITIVE (DEFAULT, RECOMMENDED)
CHARGE PUMP CURRENT
REFERENCE SOURCE
INTERNAL (DEFAULT)
EXTERNAL
RS1
RS0
INPUT REFERENCE
PATH SOURCE
0
0
1
1
0
1
0
1
2 × REFERENCE INPUT
REFERENCE INPUT (DEFAULT)
0.5 × REFERENCE INPUT
0.25 × REFERENCE INPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LOCK DETECT (DEFAULT)
VPTAT
BUFFERED VERSION OF REFERENCE INPUT
BUFFERED VERSION OF 0.5 × REFERENCE INPUT
BUFFERED VERSION OF 2 × REFERENCE INPUT
TRISTATE
BUFFERED VERSION OF 0.25 × FREF
RESERVED (DO NOT USE)
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
Rev. 0 | Page 18 of 36
09576-035
RMS2 RMS1 RMS0 OUTPUT MUX SOURCE
ADRF6801
Register 5—LO Path and Demodulator Control
Register 5 controls whether the LOIP and LOIN pins act as an input or output, whether the divider before the polyphase divider is in
divide-by-1 or divide-by-2, and whether the demodulator bias circuitry is enabled as detailed in Figure 38.
DEMOD
BIAS
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB7
DB6
DB5
DMBE
0
LDIV
LO
LO OUTPUT
IN/OUT DRIVER CONTROL BITS
CTRL ENABLE
DB4
DB3 DB2 DB1 DB0
LXL
LDRV C3(1) C2(0) C1(1)
LO OUTPUT DRIVER
LDRV ENABLE
0
1
DRIVER OFF (DEFAULT)
DRIVER ON
LXL LO IN/OUT CONTROL
0
1
LDIV
DIVIDE RATIO
0
1
÷1
÷ 2 (DEFAULT,
NECESSARY FOR VCO USE)
DMBE
DEMOD BIAS ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
Figure 38. LO Path and Demodulator Control Register (R5)
Rev. 0 | Page 19 of 36
LO OUTPUT (DEFAULT)
LO INPUT
09576-036
0
LO
FIRST
DIVIDER
ADRF6801
Register 6—VCO Control and Enables
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 31
decimal, with a default value of 24.
With R6[2:0] set to 110, the VCO control and enables register is
programmed as shown in Figure 39.
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 3.0 V supply is
available.
VCO band selection is normally selected based on BANDCAL
calibration; however, the VCO band can be selected directly using
Register 6. The VCO BS SRC determines whether the BANDCAL
calibration determines the optimum VCO tuning band or if the
external SPI interface is used to select the VCO tuning band
based on the value of the VCO band select.
CHARGE
3.3V
VCO
PUMP
LDO VCO LDO VCO
ENABLE ENABLE ENABLE ENABLE SWITCH
DB20
CPEN
DB19
L3EN
DB18
LVEN
VCO
BS
CSR
VCO AMPLITUDE
CONTROL BITS
VCO BAND SELECT
DB17
DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 VCO BAND SELECT
FROM SPI
0
...
1
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
...
1
1
1
1
1
1
0
...
32 (DEFAULT)
...
63
VBSRC VCO BAND CAL AND SW SOURCE CONTROL
BAND CAL (DEFAULT)
SPI
0
1
VC5
VC4
VC3
VC2
VC1
VC0
VCO AMPLITUDE
0
...
0
...
1
...
1
0
...
0
...
0
...
1
0
...
1
...
1
...
1
0
...
0
...
1
...
1
0
...
0
...
1
...
1
0
...
0
...
1
...
1
0
...
8 (DEFAULT)
...
47
...
63 (RECOMMENDED)
VCO SW
VCO SWITCH CONTROL FROM SPI
0
1
REGULAR (DEFAULT)
BAND CAL
VCO EN
VCO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
LVEN
VCO LDO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
L3EN 3.3V LDO ENABLE
0
1
DISABLE
ENABLE (DEFAULT)
CPEN CHARGE PUMP ENABLE
0
1
09576-037
DB23 DB22 DB21
0
0
0
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.
DISABLE
ENABLE (DEFAULT)
Figure 39. VCO Control and Enables (R6)
Rev. 0 | Page 20 of 36
ADRF6801
APPLICATIONS INFORMATION
BASIC CONNECTIONS
SYNTHESIZER CONNECTIONS
The basic circuit connections for a typical ADRF6801 application
are shown in Figure 40.
The ADRF6801 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. A 1 V p-p nominal external reference must be applied
to Pin 6 through an ac coupling capacitor. The reference is
compared to an internally divided version of the VCO output
frequency to create a charge pump error current to control and
lock the VCO. The charge pump output current is filtered and
converted to a control voltage through the external loop filter
that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected to
Pin 5 and ground, along with the internal digital settings applied to
the PLL (see the Register 4—Charge Pump, PFD, and Reference
Path Control section for more details).
SUPPLY CONNECTIONS
The ADRF6801 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6801. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 27, Pin 29, Pin 34,
and Pin 40 should be bypassed to ground using individual bypass
capacitors. Pin 40 is the decoupling pin for the on-board VCO
LDO, and for best phase noise performance, several bypass
capacitors ranging from 100 pF to 10 μF may help to improve
phase noise performance. For additional details on bypassing the
supply nodes, see the evaluation board schematic in Figure 42.
+5V
CHARGE PUMP
LOOP FILTER
39
38
37
36
35
34
33
32
31
VTUNE
LOP
LON
LOSEL
GND
VCCLO
IBBP
IBBN
GND
1 VCC1
VCCBB 29
3 CPOUT
GND 28
5
VCCRF 27
GND
RSET
MONITOR
OUTPUT
6
REFIN
7
GND
GND 24
8 MUXOUT
GND 23
9
RF INPUT
GNDRF 25
DECL2
VCCBB 22
10 VCC2
+5V
GND
CLK
LE
GND
GND
VCCLO
QBBP
QBBN
GND
GND 21
DATA
+5V
+5V
RFIN 26
ADRF6801
R2
EXTERNAL
REFERENCE
+5V
GND 30
2 DECL3
4
OPEN
IF I-OUTPUT
11
12
13
14
15
16
17
18
19
20
SPI CONTROL
IF Q-OUTPUT
BALUN
+5V
Figure 40. Basic Connections
Rev. 0 | Page 21 of 36
IF Q-OUTPUT
09576-041
+5V
40
DECL1
IF I-OUTPUT
BALUN
ADRF6801
I/Q OUTPUT CONNECTIONS
SETTING THE FREQUENCY OF THE PLL
The ADRF6801 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 24 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to transform a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
RF INPUT CONNECTIONS
The ADRF6801 is to be driven single-ended and can be either dc
coupled or ac coupled. There is an on-chip ground referenced
balun that converts the applied single-ended signal to a differential
signal that is then input to the RF V-to-I converter.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6801 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage to control the VCO
via the VTUNE voltage. The stock filter on the evaluation
board has a bandwidth of 130 kHz. The loop filter contains
seven components, four capacitors, and three resistors. Changing
the values of these components changes the bandwidth of the loop
filter. Note that to obtain the approximately 2.5 kHz loop bandwidth, the user can change the values of the following components
on the evaluation board to as follows: C14 = 0.1 μF, R10 = 68 Ω,
C15 = 4.7 μF, R9 = 270 Ω, C13 = 47 nF, R60 = 0 Ω, C4 = open.
LO SELECT INTERFACE
The ADRF6801 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
in Register 5 set high). See the Pin Configuration and Function
Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6801 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down
by either 2 or 4 depending on the LO path divider bit, LDIV, in
Register 5, prior to the actual IQ demodulating mixer core. The
divider is determined by the register settings in the LO path
and mixer control register (see the Register 5—LO Path and
Demodulator Control section). The LO input pins (Pin 37 and
Pin 38) present a broadband differential 50 Ω input impedance.
The LOP and LON input pins must be ac-coupled. This is achieved
on the evaluation board via a Mini-Circuits TC1-1-13+ balun with
a 1:1 impedance ratio. When not in use, the LOP and LON pins
can be left unconnected.
fPLL = fPFD × 2 × (INT + FRAC/MOD)
where:
fPLL is the frequency at the VCO when the loop is locked.
fPFD is the frequency at the input of the phase frequency detector.
INT is the integer divide ratio programmed into Register 0.
MOD is the modulus divide ratio programmed into Register 1.
FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is
determined by the combination of the desired fPLL and the maximum
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum fPLL of 4600 MHz,
fREF > ~fPLL/(119 × 2 × 2), or 9.7 MHz.
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
When the internal VCO is used, the actual LO frequency is
fLO = fPLL/4
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest
register (Register 7) first and then sequentially down to Register 0
last. When Register 0, Register 1, or Register 2 is programmed,
an internal VCO calibration is initiated that must execute when
the other registers are set. Therefore, the order must be Register 7,
Register 6, Register 5, Register 4, Register 3, Register 2, Register 1,
and then Register 0. Whenever Register 0, Register 1, or Register 2
is written to, it initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
If none of the register values is changing from their defaults,
there is no need to program them.
Rev. 0 | Page 22 of 36
ADRF6801
EVM MEASUREMENTS
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–65
–55
–45
–35
–25
–15
INPUT POWER (dBm)
–5
5
15
09576-042
In general, a demodulator exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase. At large enough signal levels,
where the distortion components due to the harmonic nonlinearities in the device are falling in-band, EVM degrades
as signal levels increase. At medium signal levels, where the
demodulator behaves in a linear manner and the signal is well
above any notable noise contributions, the EVM has a tendency to
reach an optimal level determined dominantly by either quadrature
accuracy and I/Q gain match of the demodulator or the precision
of the test equipment. As signal levels decrease, such that the
noise is the major contribution, the EVM performance vs. the
signal level exhibits a decibel-for-decibel degradation with
decreasing signal level. At lower signal levels, where noise proves
to be the dominant limitation, the decibel EVM proves to be
directly proportional to the SNR.
The ADRF6801 shows excellent EVM performance for 16 QAM.
Figure 41 shows the EVM of the ADRF6801 being better than
−40 dB over a RF input range of about +35 dB for the 16 QAM
modulated signal at a 10 MHz symbol rate. The pulse shaping
filter’s roll-off (alpha) was set to 0.35.
EVM (dB)
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude imbalance,
noise floor, and phase imbalance) cause the actual constellation
points to deviate from their ideal locations.
Figure 41. EVM vs. Input Power, EVM Measurements at fRF = 900 MHz;
fIF = 0 MHz (that is, Direct Down Conversion); 16 QAM; Symbol Rate = 10 MHz
The basic test setup to test EVM for the ADRF6801 consisted
of an Agilent E4438C, which was used as a signal source. The
900 MHz modulated signal was driven single ended into the
RFIN SMA connector of the ADRF6801 evaluation board. The
IQ baseband outputs were taken differentially into two AD8130
difference amplifiers to convert the differential signals into singleended signals. A Hewlett Packard 89410A VSA was used to sample
and calculate the EVM of the signal. The ADRF6801 IQ baseband output pins were presented with a 450 Ω differential load
impedance.
Rev. 0 | Page 23 of 36
ADRF6801
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6801. The
evaluation board schematic is shown in Figure 42. Table 5 provides
VCC
VCC_SENSE
1
2
3
4
the component values and suggestions for modifying the
component values for the various modes of operation.
VCC_RF
R55
S1
VCC
5
OSC_3P3V
OUTPUT_EN
LO_EXTERN
6
J1
10kΩ
3P3V_SENSE
7
8
9
10
R33
2P5V_LDO
0Ω
VTUNE
R60
10kΩ
10kΩ
3
R12
0Ω
R39
R27
0Ω
1 VCC1
37
LOP
R7
38
36
35
34
33
32
VCC_BB
31
C26
100pF
GND
DECL1
39
IBBP
40
VCO_LDO
0Ω
0Ω
C11
0.1µF
C12
100pF
VCC_RF
2 DECL3
VCCBB 29
3 CPOUT
GND 28
4
GND
5
RSET
0Ω
C24
100pF
R28
RFIN
RFIN 26
0Ω
6 REFIN
GNDRF 25
1nF
7 GND
GND 24
8 MUXOUT
GND 23
VCC_BB1
R16
REFOUT
R25
9 DECL2
VCCBB 22
0Ω
C17
0.1µF
0Ω
C16
100pF
CLK
LE
GND
GND
VCCLO
QBBP
QBBN
GND
R18
GND
2P5V_LDO
2P5V
VCC_BB
11
12
13
14
15
16
17
18
19
20
0Ω C23
0.1µF
C22
100pF
GND 21
DATA
10 VCC2
C3
10µF
C25
0.1µF
VCCRF 27
ADRF6801
R2
REFIN
R14
49.9Ω
VCC_RF
R26
OPEN
C31
C27
0.1µF
GND 30
R8
C10
100pF
OPEN
C30
0.1µF
C1
100pF
VCC4
OPEN
DATA
R47
3
0Ω
VCC
R17
C33
OPEN
VCC2
0Ω
C19
0.1µF
C18
100pF
C34
OPEN
R51
OPEN
R52
OPEN
R48
R44
OPEN
1
0Ω
R22
0Ω
R43
QOUT_SE
0Ω
5
OPEN
R57
0Ω
QBBN
C29
0.1µF
R50
OPEN
C32
OPEN
T3
4
2
P3
CLK
R30
0Ω
QBBP
R23
R21
0Ω
LE
R58
OPEN
IOUT_SE
5
IBBN
VTUNE
VCC4
R40
0Ω
1
R5
0Ω
C5
LON
C2
10µF
T2
4
1nF
1nF
R49
OPEN
C9
0.1µF
0Ω
1
C6
R15
0Ω
P2
T1
3P3V1
3P3V_SENSE
R41
OPEN
IBBN
VCO_LDO
3
2
0Ω
C4
22pF
R1
0Ω
R4
0Ω
R46
GND
C15
2.7nF
IBBP
R3
5 2
4
C13
6.8pF
OPEN
C7
0.1µF
R45
VCCLO
R11
OPEN
R10
3kΩ
R9
VCC
VCC
VCC_LO
C8
100pF
LOSEL
R38
R37
0Ω
R13
0Ω
C28
10µF
R6
0Ω
LO
C14
22pF
R31
0Ω
VCC_SENSE
VCC_LO
10kΩ
LO_EXTERN
VCO_LDO
0Ω
VCC4
VCC_LO
R32
0Ω
R56
R59
OPEN
CP
VCC_BB
R29
0Ω
S2
R20
R35
0Ω
0Ω
R19
OPEN
R42
R54
VCC
R53
0Ω
10kΩ
OPEN
R34
NET NAME
TEST POINT
OUTPUT_EN
GND
OPEN
1
GND1
P1
2
6
3
7
4
8
C21
100pF
9
GND2
0Ω
SMA INPUT/OUTPUT
DIG_GND
VTUNE
VCC_LO
R24
5
R36
0Ω
Figure 42. Evaluation Board Schematic
Rev. 0 | Page 24 of 36
C20
0.1µF
VCC_LO1
09576-044
LEGEND
ADRF6801
The package for the ADRF6801 features an exposed paddle on
the underside that should be well soldered to an exposed
opening in the solder mask on the evaluation board. Figure 43
illustrates the dimensions used in the layout of the ADRF6801
footprint on the ADRF6801 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on
the evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6801 was measured to be approximately 30°C/W in still air.
0.012
09576-046
0.035
0.050
0.168
Figure 44. ADRF6801 Evaluation Board Top Layer
0.025
09576-043
0.020
0.177
0.232
09576-047
Figure 43. Evaluation Board Layout Dimensions for the ADRF6801 Package
Figure 45. ADRF6801 Evaluation Board Bottom Layer
Table 5. Evaluation Board Configuration Options
Component
VCC, VCC2, VCC4, VCO_LDO, VCC_LO,
VCC_LO1, VCC_RF, VCC_BB1, 3P3V1,
2P5V, CLK, DATA, LE, CP, DIG_GND,
GND, GND1, GND2
Function
Power supply, ground and other test points.
Connect a 5 V supply to VCC.
R1, R6, R7, R8, R13, R15, R17, R18,
R24, R25, R26, R27, R29, R31, R32,
R36, R49
Power supply decoupling. Shorts or power supply
decoupling resistors.
Rev. 0 | Page 25 of 36
Default Condition
VCC, VCC2, VCC4, VCC_LO, VCC_RF, VCC_BB1,
VCC_LO1, VCO_LDO, 3P3V1, 2P5V =
Components Corporation TP-104-01-02,
CP, LE, CLK, DATA =
Components Corporation TP-104-01-06,
GND, GND1, GND2, DIG_GND =
Components Corporation TP-104-01-00
R1, R6, R7, R8 = 0 Ω (0402),
R13, R15, R17 = 0 Ω (0402),
R18, R24, R25, R26, R27 = 0 Ω (0402),
R29, R31, R32 = 0 Ω (0402),
R36 = 0 Ω (0402),
R49 = open (0402)
ADRF6801
Component
C1, C2, C3, C7, C8, C9, C10, C11, C12,
C16, C17, C18, C19, C20, C21, C22,
C23, C24, C25, C26, C27, C28
Function
The capacitors provide the required decoupling of
the supply-related pins.
T1, C5, C6
External LO path. The T1 transformer provides
single-ended-to-differential conversion. C5 and C6
provide the necessary ac coupling.
REFIN input path. R14 provides a broadband 50 Ω
termination followed by C31, which provides the
ac coupling into REFIN. R16 provides an external
connectivity to the MUXOUT feature described in
Register 4. R58 provides option for connectivity to
the P1-6 line of a 9-pin D-sub connector for dc
measurements.
Loop filter component options. A variety of loop filter
topologies is supported using component
placements C4, C13, C14, C15, R9, R10, and R60. R38
and R59 provide connectivity options to numerous
test points for engineering evaluation purposes. R2
provides resistor programmability of the charge
pump current (see Register 4 description). R37
connects the charge pump output to the loop filter.
R12 references the loop filter to the VCO_LDO. Default
values on board provide a loop filter bandwidth of
roughly 130 kHz using a 26 MHz PFD frequency.
IF I/Q output paths. The T2 and T3 baluns provide a
9:1 impedance transformation; therefore, with a 50 Ω
load on the single-ended IOUT/QOUT side, the center
tap side of the balun presents a differential 450 Ω
to the ADRF6806. The center taps of the baluns are
ac grounded through C29 and C30. The baluns create
a differential-to-single-ended conversion for ease
of testing and use, but an option to have straight
differential outputs is achieved via populating R3,
R39, R23, and R42 with 0 Ω resistors and removing
R4, R5, R21, and R22. P2 and P3 are differential
measurement test points (not to be used as jumpers).
RF input interface. R28 provides the single-ended
RF input path to the on-chip RF input balun.
Serial port interface. A 9-pin D-sub connector (P1)
is provided for connecting to a host PC or control
hardware. Optional RC filters can be installed on
the CLK, DATA, and LE lines to filter the PC signals
through R50 to R52 and C32 to C34. CLK, DATA, and
LE signals can be observed via test points for debug
purposes. R58 provides a connection to the MUXOUT
for sensing lock detect through the P1 connector.
LO select interface. The LOSEL pin, in combination
with the LDRV and LXL bits in Register 5, controls
whether the LOP and LON pins operate as inputs or
outputs. A detailed description of how the LOSEL pin,
LDRV bit, and the LXL bit work together to control
the LOP and LON pins is found in Table 4 under the
LOSEL pin description. Using the S1 switch, the
user can pull LOSEL to a logic high (VCC/2) or a logic
low (ground). Resistors R55 and R56 form a resistor
divider to provide a logic high of VCC/2. LO select
can also be controlled through Pin 9 of J1. The 0 Ω
jumper, R33, must be installed to control LOSEL via J1.
R16, R14, R58, C31
R2, R9, R10, R11, R12, R37, R38, R59,
R60, C4, C14, C15, C13
R3, R4, R5, R21, R22, R23, R39, R40,
R41, R42, R43, R44, R45, R46, R47,
R48, C29, C30, T2, T3, P2, P3
R28
R30, R35, R50, R51, R52, R57, C32,
C33, C34, P1
R33, R55, R56, S1
Rev. 0 | Page 26 of 36
Default Condition
C1, C8, C10, C12 = 100 pF (0402),
C16, C18, C21, C22 = 100 pF (0402),
C24, C26 = 100 pF (0402),
C7, C9, C11 = 0.1 μF (0402),
C17, C19, C20, C23 = 0.1 μF (0402),
C25, C27 = 0.1 μF (0402),
C3, C2 = 10 μF (0603), C28 = 10 μF (3216)
C5, C6 = 1 nF (0603),
T1 = TC1-1-13+ Mini-Circuits
R14 = 49.9 Ω (0402),
R16 = 0 Ω (0402),
R58 = open (0402),
C31 = 1 nF (0603)
R12, R37, R38 = 0 Ω (0402),
R59 = open (0402),
R9, R60 = 10 kΩ (0402),
R10 = 3 kΩ (0402),
R2, R11 = open (0402),
C13 = 6.8 pF (0402),
C4, C14 = 22 pF (0402),
C15 = 2.7 nF (1206)
R4, R5, R21, R22, = 0 Ω (0402),
R40, R43, R45, R46 = 0 Ω (0402),
R47, R48 = 0 Ω (0402),
R3, R23, R39, R41, R42, R44 = open (0402),
C29, C30, = 0.1 μF (0402),
T2, T3 = TCM9-1+ Mini-Circuits,
P2, P3 = Samtec SSW-102-01-G-S
R28 = 0 Ω (0402)
R30, R35, R57 = 0 Ω (0402),
R50, R51, R52 = open (0402),
C32, C33, C34 = open (0402),
P1 = Tyco Electronics 5747840-3
R33 = 0 Ω (0402),
R55, R56 = 10 kΩ (0402),
S1 = Samtec TSW-103-08-G-S
ADRF6801
Component
J1
R19, R20, R34, R53, R54, S2
Function
Engineering test points and external control. J1 is a
10-pin connector connected to various important
points on the evaluation board that the user can
measure or force voltages upon.
Provides ground connection for Pin 16.
Rev. 0 | Page 27 of 36
Default Condition
J1 = Molex Connector Corp. 10-89-7102
R20, R53 = 0 Ω (0402),
R34, R54 = open (0402),
R19 = open, S2 = open
ADRF6801
ADRF6801 SOFTWARE
The ADRF6801 evaluation board can be controlled from PCs
using a USB adapter board, which is also available from Analog
Devices, Inc. The USB adapter evaluation documentation and
ordering information can be found on the EVAL-ADF4XXXZ-USB
product page. The basic user interfaces are shown in Figure 46 and
Figure 47.
09576-048
The software allows the user to configure the ADRF6801 for
various modes of operation. The internal synthesizer is controlled
by clicking on any of the numeric values listed in RF Section.
Attempting to program Ref Input Frequency, PFD Frequency,
VCO Frequency (2×LO), LO Frequency, or other values in RF
Section launches the Synth Form window shown in Figure 47.
Using Synth Form, the user can specify values for Local Oscillator
Frequency (MHz) and External Reference Frequency (MHz).
The user can also enable the LO output buffer and divider options
from this menu. After setting the desired values, it is important
to click Upload all registers for the new setting to take effect.
Figure 46. Evaluation Board Software Main Window
Rev. 0 | Page 28 of 36
09576-049
ADRF6801
Figure 47. Evaluation Board Software Synth Form Window
Rev. 0 | Page 29 of 36
ADRF6801
CHARACTERIZATION SETUPS
Figure 48 to Figure 50 show the general characterization bench
setups used extensively for the ADRF6801. The setup shown in
Figure 48 was used to do the bulk of the testing. An automated
Agilent VEE program was used to control the equipment over the
IEEE bus. This setup was used to measure gain, input P1dB, output
P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature
accuracy, and supply current. The evaluation board was used to
perform the characterization with a Mini-Circuits TCM9-1+ balun
on each of the I and Q outputs. When using the TCM9-1+ balun
below 5 MHz (the specified 1 dB low frequency corner of the
balun), distortion performance degrades; however, this is not
the ADRF6801 degrading, merely the low frequency corner of
the balun introducing distortion effects. Through this balun,
the 9-to-1 impedance transformation effectively presented a 450 Ω
differential load at each of the I and Q channels. The losses of the
output baluns were de-embedded from all measurements.
To do phase noise and reference spur measurements, the setup
shown in Figure 50 was used. Phase noise was measured at the
baseband output (I or Q) at a baseband carrier frequency of
50 MHz. The baseband carrier of 50 MHz was chosen to allow
phase noise measurements to be taken at frequencies of up to
20 MHz offset from the carrier. The noise figure was measured
using the setup shown in Figure 49 at a baseband frequency
of 10 MHz.
Rev. 0 | Page 30 of 36
ADRF6801
IEEE
R&S SMA100
SIGNAL GENERATOR
IEEE
3dB
RF1
R&S SMT03 SIGNAL GENERATOR
AGILENT 11636A
POWER DIVIDER
(USED AS COMBINER)
REF
3dB
RF2
IEEE
MINI-CIRCUITS
ZHL-42W AMPLIFIER
(SUPPLIED WITH +15V dc
FOR OPERATION)
3dB
3dB
RF
R&S SMT03 SIGNAL GENERATOR
IEEE
CH A
RF SWITCH MATRIX
CH B
HP 8508A
VECTOR
VOLTMETER
IEEE
I CH
RF
Q CH
6dB
3dB
6dB
AGILENT MXA
SPECTRUM ANALYZER
IEEE IEEE
AGILENT DMM
(FOR ISUPPLY MEAS.)
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
ADRF6801
EVALUATION BOARD
10-PIN
CONNECTION
(+5V VPOS,
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
IEEE
IEEE
6dB
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
REF
IEEE
09576-050
IEEE
Figure 48. General Characterization Setup
Rev. 0 | Page 31 of 36
ADRF6801
IEEE
AGILENT 8665B
LOW NOISE SYN
SIGNAL GENERATOR
REF
RF1
AGILENT 346B
NOISE SOURCE
3dB
RF
RF SWITCH MATRIX
10MHz
LOW-PASS FILTER
IEEE
AGILENT N8974A
NOISE FIGURE ANALYZER
I CH
RF
Q CH
6dB
3dB
6dB
AGILENT DMM
(FOR ISUPPLY MEAS.)
E IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
IEEE
ADRF6801
EVALUATION BOARD
10-PIN
CONNECTION
(+5V VPOS1,
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
IEEE
6dB
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
REF
IEEE
09576-051
IEEE
Figure 49. Noise Figure Characterization Setup
Rev. 0 | Page 32 of 36
ADRF6801
IEEE
R&S SMA100
SIGNAL GENERATOR
IEEE
REF
RF1
R&S SMA100
SIGNAL GENERATOR
IEEE
100MHz
LOW-PASS FILTER
3dB
AGILENT E5052 SIGNAL SOURCE
ANALYZER
RF
RF SWITCH MATRIX
IEEE
AGILENT MXA
SPECTRUM ANALYZER
I CH
RF
Q CH
6dB
3dB
6dB
AGILENT DMM
(FOR ISUPPLY MEAS.)
E IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
IEEE
ADRF6801
EVALUATION BOARD
10-PIN
CONNECTION
(+5V VPOS1,
DC MEASURE)
AGILENT E3631A
POWER SUPPLY
IEEE
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
REF
IEEE
I E IEEE
6dB
IEEE
09576-052
IEEE
Figure 50. Phase Noise Characterization Setup
Rev. 0 | Page 33 of 36
ADRF6801
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
SEATING
PLANE
40
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADRF6801ACPZ-R7
ADRF6801-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 34 of 36
Package Option
CP-40-1
Ordering
Quantity
750
ADRF6801
NOTES
Rev. 0 | Page 35 of 36
ADRF6801
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09576-0-1/11(0)
Rev. 0 | Page 36 of 36