SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14583B is a dual Schmitt trigger constructed with complementary P–channel and N–channel MOS devices on a monolithic silicon substrate. Each Schmitt trigger is functionally independent except for a common 3–state input and an internally–connected Exclusive OR output for use in line receiver applications. Trigger levels are adjustable through the positive, negative, and common terminals with the use of external resistors. Applications include the speed–up of a slow waveform edge in interface receivers, level detectors, etc. P SUFFIX PLASTIC CASE 648 • • • • Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Single Supply Operation Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Resistor Adjustable Trigger Levels D SUFFIX SOIC CASE 751B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL DC Supply Voltage Value Lead Temperature (8–Second Soldering) TA = – 55° to 125°C for all packages. BLOCK DIAGRAM 6 * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Plastic Ceramic SOIC 5 7 VDD = PIN 16 VSS = PIN 8 APos ANeg ACom Aout Ain Aout Dis 9 13 4 11 14 10 Bout Bin Bout BPos BNeg BCom 15 LOGIC DIAGRAM 12 POSITIVE A NEGATIVE A 6 5 7 COMMON A Ain 9 2 4 3 1 Aout TRUTH TABLE Inputs 11 Aout 3–STATE OUTPUT DISABLE 13 14 EXCLUSIVE OR Bin 15 10 Bout 12 Bout 1 COMMON B 2 3 POSITIVE B2 NEGATIVE B A B 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 Outputs Dis Aout Aout Bout Bout 0 0 Z 0 Z 1 0 1 0 1 0 0 Z 1 Z 1 0 1 1 0 0 1 0 1 1 1 1 1 Z 0 Z 0 0 0 1 1 Z 1 Z 0 ę 0 0 1 1 1 1 0 0 Z = High impedance at output VDD = PIN 16 VSS = PIN 8 REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14583B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 1.2 – 0.25 – 1.62 – 1.8 — — — — – 1.0 – 0.2 – 0.5 – 1.5 – 1.7 – 0.36 – 0.9 – 3.5 — — — — – 0.7 – 0.14 – 0.35 – 1.1 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 0.25 0.5 1.0 — — — 0.0005 0.0010 0.0015 0.25 0.5 1.0 — — — 7.5 15 30 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three–State Leakage Current ITL 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (1.33 µA/kHz) f + IDD IT = (2.65 µA/kHz) f + IDD IT = (3.98 µA/kHz) f + IDD — ± 0.1 — ± 0.0001 µAdc ± 0.1 — ± 3.0 µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. MC14583B 2 PIN ASSIGNMENT BCom 1 16 VDD BPos 2 15 Bin BNeg 3 14 Aout 4 13 DIS ANeg 5 12 Bout APos 6 11 Aout ACom 7 10 Bout VSS 8 9 Ain MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL Propagation Delay Time Ain, Bin to Aout, Bout tPLH, tPHL = (1.7 ns/pF) CL + 565 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns tPLH, tPHL Ain, Bin to Aout, Bout tPLH, tPHL = (1.7 ns/pF) CL + 1015 ns tPLH, tPHL = (0.66 ns/pF) CL + 347 ns tPLH, tPHL = (0.5 ns/pF) CL + 235 ns tPLH, tPHL Ain, Bin to Exclusive OR tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 257 ns tPLH, tPHL = (0.5 ns/pF) CL + 145 ns tPLH, tPHL 3–State Enable, Disable Delay Time (see figure 5) ton, toff = (1.7 ns/pF) CL + 140 ns ton, toff = (0.66 ns/pF) CL + 57 ns ton, toff = (0.5 ns/pF) CL + 30 ns ton, toff Positive Threshold Voltage (R1, R2 = 5.0 kΩ) VDD Min Typ # Max 5.0 10 15 — — — 180 90 65 360 180 130 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns ns 5.0 10 15 — — — 650 230 150 1300 460 300 5.0 10 15 — — — 1100 380 260 2200 760 520 5.0 10 15 — — — 750 280 170 1500 560 340 5.0 10 15 — — — 225 90 55 450 180 110 VT+ 5.0 10 15 — — — 3.30 5.70 8.20 — — — Vdc Negative Threshold Voltage (R1, R2 = 5.0 kΩ) VT– 5.0 10 15 — — — 1.70 4.30 6.80 — — — Vdc Hysteresis Voltage (R1, R2 = 5.0 kΩ) VH 5.0 10 15 0.85 0.70 0.70 1.70 1.40 1.40 3.40 2.80 2.80 Vdc Threshold Voltage Variation, A to B (R1, R2 = 5.0 kΩ) ∆VT 5.0 10 15 — — — 0.1 0.15 0.20 — — — Vdc ns ns ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MOTOROLA CMOS LOGIC DATA MC14583B 3 VDD Vout VDD 1 VSS SW1 Aout Aout Ain DIS Bin Bout Bout 2 2 SW2 1 Output Under Test IO Output Source Characteristics Output Sink Characteristics Test NJ VGS = – VDD Value VDS = Vout – VDD Switch Position SW1 SW2 Test NJ VGS = VDD Value VDS = Vout Switch Position SW1 SW2 Aout, Bout 1 1 2 2 Aout, Bout Exclusive OR 2 2 1 1 1 2 1 1 EXTERNAL POWER SUPPLY VSS Figure 1. Typical Output Source and Sink Characteristics Test Circuit VDD 500 µF 0.01 µF CERAMIC ID PULSE GENERATOR 1 Ain PULSE GENERATOR 2 Aout Aout DIS Bin Bout Bout VSS fout, Ain fout, Bin CL CL CL CL CL Figure 2. Power Dissipation Test Circuit and Waveforms 80 R1 70 POSITIVE COMMON NEGATIVE R2 B — Feedback scheme for hysteresis adjustment: POSITIVE COMMON NEGATIVE R1 TYPICAL THRESHOLD POINT (%VDD) A — Feedback scheme for independent threshold adjustment: 60 50 40 30 VSS = 0 VDD = 5.0 V VDD = 10 V VDD = 15 V 20 10 6 8 10 20 40 100 1.0 k 10 k R1, R2, RESISTANCE (OHMS) 100 k 1.0 M Figure 3. Typical Threshold Points MC14583B 4 MOTOROLA CMOS LOGIC DATA VDD PULSE GENERATOR 1 Ain PULSE GENERATOR 2 DIS Bin Bout Bout PULSE GENERATOR 3 Aout Aout CL VSS CL CL CL CL INPUT = tr = tf = 20 ns VDD Ain 50% VSS VDD 50% Bin VSS VDD 3–STATE DISABLE 50% tPLH tPHL Aout tr tf 90% 50% 10% tPHL tr tf tPLH 90% 50% Bout 10% tPHL tPLH 50% Aout ton tf toff 90% tPHL tr 90% EXCLUSIVE OR VOH VOL VOH Bout tr VOL VOL ton toff tf VOH VOH 10% tPLH VSS tPHL tPLH tPHL tPLH 50% 10% tf tr VOL VOH VOL NOTE: Dashed lines indicate high output resistance Figure 4. Switching Time Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA MC14583B 5 VDD VDD 1 k* PULSE GENERATOR 1 Ain PULSE GENERATOR 2 DIS Bin Aout Aout 1 SW 2 Bout Bout Test Switch Position ton HL ton LH 1 toff HL toff LH 2 2 1 1 k* CL * Metal film, ± 1%, 1/4 W or greater VSS CL = 15 pF, which includes test circuit capacitance. VDD Ain VSS VDD Bin VSS VDD 3–STATE DISABLE 50% ton LH Aout 10% VOL ton LH Bout 10% 90% VOH′ SWITCH POSITION 2 toff LH ton HL VOH′ 90% toff HL VOH′ VSS toff LH 90% VOH toff LH 90% VOH VOH 10% (VOH – VOL′) VOL′ VOL VOH 10% (VOH – VOL′) VOL′ VOL SWITCH POSITION 1 VOL′ and VOH′ refer to the levels present as a result of the 1 k ohm load resistors. Figure 5. 3–State Switching Time Test Circuit and Waveforms MC14583B 6 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14583B 7 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14583B 8 ◊ *MC14583B/D* MOTOROLA CMOS LOGIC DATA MC14583B/D