For:char Printed on:Mon, Feb 6, 1995 09:32:08 From book:DL121CH4 (5) VIEW Document:MC74F283 (5) VIEW Last saved on:Fri, Feb 3, 1995 16:03:54 MC54/74F283 4-BIT BINARY FULL ADDER (With Fast Carry) The MC54/74F283 high-speed 4-bit binary full adder with internal carry lookahead, accepts two 4-bit binary words (A0–A3, B0–B3) and a Carry input (C0). It generates the binary Sum outputs (S0–S3) and the Carry output (C4) from the most significant bit. The F283 will operate with either active-HIGH or active-LOW operands (positive or negative logic). 4-BIT BINARY FULL ADDER (With Fast Carry) FAST SCHOTTKY TTL FUNCTIONAL DESCRIPTION The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C0. The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. J SUFFIX CERAMIC CASE 620-09 16 1 20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation.Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7. Due to the symmetry of the binary add function, the F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure A. Note that if C0 is not used it must be tied LOW for active-HIGH logic or tied HIGH for active-LOW logic. Due to pin limitations, the intermediate carries of the F283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure B shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure C shows a way of dividing the F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure D shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1–I5 that are true. Figure E shows one method of implementing a 5-input majority gate. When three or more of the inputs I1–I5 are true, the output M5 is true. CONNECTION DIAGRAM VCC B2 A2 S2 A3 B3 S3 C4 16 15 14 13 12 11 10 9 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 1 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 7 C0 4 S0 1 S1 13 S2 10 S3 C4 1 S1 2 B1 3 A1 4 S0 5 A0 6 B0 7 C0 9 8 GND FAST AND LS TTL DATA 4-146 A0 B0 A1 B1 A2 B2 A3 B3 5 6 3 2 14 15 12 11 VCC = PIN 16 GND = PIN 8 MC54/74F283 LOGIC DIAGRAM C0 A0 B0 A1 S0 B1 A2 S1 B2 A3 S2 B3 S3 C4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 – 55 25 125 74 0 25 70 VCC Supply Voltage TA Operating Ambient Temperature Range IOH Output Current — High 54, 74 — — –1.0 mA IOL Output Current — Low 54, 74 — — 20 mA Figure A. Active-HIGH versus Active-LOW Interpretation C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L L H L H H L L H H H L L H Active HIGH Active LOW 0 1 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 1 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FAST AND LS TTL DATA 4-147 °C MC54/74F283 C10 L A0 B0 A1 B1 A2 B2 A3 B3 C0 C0 C4 S0 S1 S2 A0 B0 A1 B1 A10 B10 A0 B0 A1 B1 A2 B2 A3 B3 C4 C0 S3 C3 Figure B. 3-Bit Adder S0 S1 S2 S3 S0 S1 C2 S10 C11 Figure C. 2-Bit and 1-Bit Adders I3 I4 I5 I1 I2 I3 I4 I5 I1 I2 L A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 C0 C0 C4 S0 S1 S2 20 21 22 C4 S0 S1 S2 S3 S3 M5 Figure D. 5-Input Encoder Figure E. 5-Input Majority Gate DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V IIN = –18 mA VCC = MIN 54, 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.5 V 74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VIN = 2.7 V 100 µA VIN = 7.0 V Input LOW Current C0 Input – 0.6 mA VIN = 0.5 V VCC = MAX A and B Inputs –1.2 mA –150 mA VOUT = 0 V VCC = MAX 55 mA Inputs = 4.5 V VCC = MAX IOS Output Short Circuit Current (Note 2) ICC Power Supply Current 0.35 – 60 36 NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-148 VCC = MAX MC54/74F283 AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C VCC = +5.0 V CL = 50 pF TA = –55 to +125°C VCC = 5.0 V ±10% CL = 50 pF TA = 0 to +70°C VCC = 5.0 V ±10% CL = 50 pF Min Typ Max Min Max Min Max Unit tPLH tPHL Propagation Delay C0 to Sn 3.5 4.0 7.0 7.0 9.5 9.5 3.5 4.0 14 14 3.5 4.0 10.5 10.5 ns tPLH tPHL Propagation Delay An or Bn to Sn 3.0 3.5 7.0 7.0 9.5 9.5 3.0 3.5 14 14 3.0 3.5 10.5 10.5 ns tPLH tPHL Propagation Delay C0 to C4 3.5 3.0 5.7 5.4 7.5 7.0 3.5 3.0 10.5 10 3.5 3.0 8.5 8.0 ns tPLH tPHL Propagation An or Bn to C4 3.0 3.0 5.7 5.3 7.5 7.0 3.0 3.0 10.5 10 3.0 3.0 8.5 8.0 ns FAST AND LS TTL DATA 4-149