54ACT283 4-Bit Binary Full Adder with Fast Carry General Description Features The ’ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0–A3, B0–B3) and a Carry input (C0). It generates the binary Sum outputs (S0–S3) and the Carry output (C4) from the most significant bit. The ’ACT283 will operate with either active HIGH or active LOW operands (positive or negative logic). n n n n Logic Symbols Guaranteed 4000V minimum ESD protection Outputs source/sink 24 mA TTL-compatible inputs Available to Mil-Std-883 Pin Assignment for LCC DS100977-1 IEEE/IEC DS100977-3 Functional Description The ’ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 + B0 + C0) + 21 (A1 + B1) DS100977-4 Connection Diagrams Pin Assignment for DIP and Flatpak DS100977-2 © 1998 National Semiconductor Corporation DS100977 + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the ’ACT283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the ’ACT283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the ’ACT283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. www.national.com 54ACT283 4-Bit Binary Full Adder with Fast Carry September 1998 Functional Description equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1–I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1–I5 are true, the output M5 is true. (Continued) Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L L H L H H L L H H H L L H Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FIGURE 1. Active HIGH versus Active LOW Interpretation DS100977-5 FIGURE 2. 3-Bit Adder DS100977-7 FIGURE 4. 5-Input Encoder DS100977-6 FIGURE 3. 2-Bit and 1-Bit Adders DS100977-8 FIGURE 5. 5-Input Majority Gate www.national.com 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DS100977-9 Logic Diagram 3 www.national.com Absolute Maximum Ratings (Note 1) 3-STATE Output Current Applied to Output in LOW State (Max) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to +5.5V twice the rated IOL (mA) Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to VCC DC Electrical Characteristics for ’ACT Family Devices Symbol VIH VIL VOH Parameter VCC TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.7 5.5 4.7 Units Conditions V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA VIN = V VOL Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 4.5 0.5 Maximum Input or VIH IOH = −24 mA V IOH = −24 mA (Note 3) IOUT = 50 µA VIN = V IIN IL V IL or VIH V IOL = 24 mA 5.5 0.5 5.5 ± 1.0 µA IOL = 24 mA (Note 3) VI = V CC, GND 5.5 1.6 mA VI = V 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min 5.5 160.0 µA VIN = V Leakage Current ICCT Maximum CC − 2.1V ICC/Input IOLD IOHD Minimum Dynamic Output Current (Note 4) ICC Maximum Quiescent Supply Current or GND Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. www.national.com 4 CC AC Electrical Characteristics for ’ACT Family Devices Symbol 54ACT TA, VCC = Mil CL = 50 pF Parameter Min Units Max tPLH Propagation Delay 2.5 14.0 tPHL C0 to Sn 2.5 14.0 tPLH Propagation Delay 2.0 17.0 tPHL An or Bn to Sn 2.0 17.0 tPLH Propagation Delay 2.5 10.0 tPHL C0 to C4 2.5 11.0 tPLH Propagation Delay 2.5 10.5 tPHL An or Bn to C4 2.5 11.5 5 ns ns ns ns www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier (L) Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) Package Number J16A 7 www.national.com 54ACT283 4-Bit Binary Full Adder with Fast Carry Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.