SEMICONDUCTOR TECHNICAL DATA ! The MC100SX1451FI100 AutoBahn chip is a high–speed serial– to–parallel, parallel–to–serial transceiver. The AutoBahn can be used to implement a high–speed, half–duplex, bi–directional serial data link with an effective data transfer rate of 100MByte/sec. A higher performance AutoBahn chip, with user selectable serial data transfer rates of 100 or 200MByte/s, is planned (see the MC100SX1451FI200 datasheet).This serial link can be used to establish multi–point or point–to–point connections. A unique differential cutoff driver switches from a standard PECL VOH level to cutoff. In the cutoff state the outputs present a high impedance which is required to implement a true shared bus. The part features a 32–bit wide parallel TTL compatible I/O interface that can connect directly with standard memory or bus transceiver devices. The control pins are all TTL compatible to simplify interfacing requirements. The serial interface is PECL (Positive Emitter Coupled Logic) which provides excellent transmission line drive capability. Because the serial bus is implemented using differential ECL technology, the receiver circuitry exhibits excellent common mode noise rejection. AUTOBAHN SPANCEIVER • 100MByte/s Serial Data Transfer Capability • TTL Compatible Parallel Interface FI SUFFIX CERAMIC QFP PACKAGE CASE 963–02 • Supports 16– or 32–Bit Data Bus Interfaces • Bus Driving Differential ECL Serial Outputs • On–Board Clock Recovery and Data Synchronization • 64–Pin Surface Mount CQFP Packaging • Parallel Data Bus Handshake Control An innovative data synchronizing architecture allows data to be transmitted in bursts without preamble bits. This allows instantaneous data acquisition without the inherent overhead of traditional PLL clock recovery. Thus, the data transfer is nearly overhead free with only one synchronization bit for every byte of data transmitted. Insertion and removal of synchronization bits are totally transparent to the user. The AutoBahn supports variable data transfer rates. This is accomplished by combining the fixed burst transfer rates of 50 or 100MByte/s with a flexible method of allowing data to be written into the AutoBahn for transfer. If new data has not been written into the parallel data register prior to the completion of a serial data burst, the AutoBahn will insert a gap in the serial data stream. Therefore, the effective throughput of the serial bus is throttled by the speed of the parallel host interface which writes data to the chip. With its very high block data transfer capability and instantaneous start up ability, the AutoBahn is ideally suited for multimedia graphics applications and parallel processing architectures requiring multi–processor communication links. Motorola’s state–of–the–art MOSAIC V process allows for the realization of 1.8GHz internal clock rates at power levels which are compatible with today’s low profile surface mount packages. Furthermore, the design is implemented with a flow–through pinout architecture to simplify PCB layout and routing. The board space efficiency of the CQFP ensures that the AutoBahn device will prove valuable in the most demanding space conscious applications. The AutoBahn chip works from a single +5.0V supply. Separate internal VCC busses isolate the TTL outputs from the high speed PECL circuitry. AutoBahn and Spanceiver are trademarks of PEP Modular Computers. ‘Spanceiver’ has been formed as a contraction of Serial/Parallel Transceiver. MOSAIC V is a trademark of Motorola, Inc. 7/97 Motorola, Inc. 1997 1 REV 0 MC100SX1451FI100 RESET RESET LOGIC PISO CONTROL LOGIC STRB R/W REGSEL REGISTER READ/ WRITE LOGIC TRANSMIT REGISTER D31– D00 PISO SHIFT REGISTER FULL SYNC BIT GENERATOR SERIAL BUS TRANSCEIVER RECEIVE REGISTER CONTROL REGISTER SIPO SHIFT REGISTER SER SER SYNC BIT EXTRACT SIPO CONTROL LOGIC DIFFERENTIAL DETECTOR ERROR REGISTER BUSY PLL CLOCK FOSC GENERATOR C1 ERROR Figure 1. Simplified Block Diagram MOTOROLA 2 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 PIN DESCRIPTIONS Name I/O Description RESET I Asynchronous reset signal which places the AutoBahn into default state. In most applications, RESET should only have to be asserted on system startup. R/W I Read/Write control signal. Used to select between writing to or reading from the AutoBahn. REGSEL I Control signal used to select between the Parallel Data Register and the Control and Error Register(s). A logic ‘H’ selects the data register while a logic ‘L’ selects the Control and Error Register(s). I/O Bi–directional data inputs/outputs. These pins comprise the data bus to be used to interface to the user host interface. D00 is the least significant bit. STRB I Data strobe signal. During a write, it indicates that data is valid on the parallel bus. While in a read, it indicates that the AutoBahn can now place data on the parallel interface. FULL O Signal which indicates that the transmitter or receiver presently contains data. In conjunction with the STRB signal, it is used to implement a two signal handshake for parallel data transfers. BUSY O Serial bus BUSY signal, used to indicate to the parallel interface that the AutoBahn bus is presently in use. ERROR O Control output which is used to indicate that the AutoBahn has identified a fault condition. The error condition can then be read out from the Error Register. FOSC I 25.00MHz clock source from a crystal oscillator reference. TTL COMPATIBLE I/O D00 – D31 PECL COMPATIBLE I/O SER/SER I/O Differential serial data inputs/outputs which operate at modified PECL levels. POWER, GROUND AND FILTER PINS Name Number Description C1 1 PLL Filter Capacitor Pin VCCE 1 Positive Supply for Internal PECL Logic Circuitry VCCO 1 Positive Supply for PECL Outputs VEE 1 Ground for PECL VCCT 7 Positive Supply for TTL Compatible Signals VEET 8 Ground for TTL Compatible Signals VCCX 1 Positive Supply for VCO VEEX 1 Ground for VCO BLOCK DIAGRAM FUNCTIONAL DESCRIPTION Reset Logic The Reset Logic generates the internal reset signal used to set the device into a known state. The reset signal clears the Control and Error Registers and resets the SIPO and PISO Control Logic. The external reset signal is validated with the FOSC input clock to assure that a valid reset pulse has been applied to the chip. The external reset input pin (RESET) must be low for a minimum of 125 nsec after the FOSC input is stable. STRB assertion may occur no earlier than 500 nsec after RESET deassertion (reset recovery time). ECLinPS and ECLinPS Lite DL140 — Rev 3 Control Register The Control Register is used to configure the operation of the AutoBahn. The register fields are described in detail in the section containing the Control and Error Register Bit Definition. Register Read/Write Control Logic This logic is utilized to access the Transmit Register, the Receive Register, and the Control and Error Registers from the parallel bus. The interface protocol utilizes two direction control signals (R/W and REGSEL). The actual handshake to 3 MOTOROLA MC100SX1451FI100 read or write data from the chip is accomplished with the input STRB signal , combined with the output FULL signal. Differential Detector The differential detector is used to recognize when the serial bus goes out of the cutoff state and into a differential steady state condition. The differential detector is only utilized at the very start of a transmission. The detector informs the SIPO Control Logic that the serial bus is no longer in cutoff so that the bus BUSY signal can be asserted by the device. Transmit Register The transmit register is a 32–bit wide parallel–loadable register. This register interfaces to the bi–directional TTL compatible data bus. Access to this register is controlled via the Register Read/Write Logic. PLL Clock Generator The Clock Generator circuitry synthesizes a master timing clock from the frequency reference signal (FOSC) input. The clock generator provides timing signals used to support the transfer rate of 900 MBit/s. The clock is generated by a Phase Locked Loop (PLL) which requires a simple external capacitor to set the loop filter bandwidth. The value for C1 is 2700 pF. This circuitry is used to provide the master timing for the PISO and SIPO Control Logic blocks. PISO Shift Register The PISO (Parallel In/Serial Out) Register accepts data from the Transmit Register and converts it into a serial bit stream. This register is under control of the PISO Control Logic. The shift register can be adjusted to handle 16–bit or 32–bit data traffic based on the state of the appropriate field in the Control Register. SYNC Bit Extractor The SYNC Bit Extractor removes each SYNC bit from the incoming data stream. It is controlled by the SIPO Control Logic. If a SYNC bit is not detected at the proper bit time in the extraction process, a field will be set in the Error Register to indicate that a transmission error has occurred. PISO Control Logic The PISO (Parallel In/Serial Out) Control Logic is responsible for controlling the transfer of data out from the AutoBahn to the serial bus. This logic interfaces to the PISO Shift Register and the SYNC Bit Generator. It is driven by the PLL Clock Generator. SIPO Shift Register The SIPO (Serial In/Parallel Out) Register accepts data from the SYNC Bit Extractor and converts it into a parallel word that is then transferred to the Receive Register. The operation of this shift register is controlled by the SIPO Control Logic. SYNC Bit Generator This circuitry inserts one bit of timing information into the data stream before every byte of data is sent to the Serial Bus Transceiver and transmitted. This timing information is used by the receiver to properly re–clock the incoming data stream. To support the maximum data rate of 100 MByte/sec, the actual serial shift rate is 900 MBit/s NRZ, rather than 800 MBit/s NRZ. The insertion and removal of SYNC bits is transparent to the end user. SIPO Control Logic The SIPO (Serial In/Parallel Out) Control Logic is responsible for controlling the transfer of data into the AutoBahn. This circuitry performs all the critical control functions to allow the AutoBahn to accept and process the incoming serial data stream. The SIPO Control Logic has the ability to detect certain transmission related errors and set the appropriate field(s) in the Error Register. Serial Bus Transceiver The transceiver implements a two signal bi–directional differential bus. The transceiver circuitry consists of a highly sensitive differential receiver and a cutoff driver. The receiver accepts a differential signal from the serial bus. This differential signal is amplified and limited by the receiver before being routed to the clock generation circuitry for clock extraction and data re–timing. Receive Register The receive register is a 32–bit wide parallel load register. It accepts data from the SIPO (Serial In/Parallel Out) Shift Register. This register interfaces to the bi–directional TTL compatible data bus. Access to this register is controlled via the Register Read/Write Logic. Error Register The AutoBahn has the capability to detect certain transmission related error conditions. These errors are detected by the SIPO Control Logic which sets the appropriate error field in the Error Register. The register fields are described in detail in the section containing the Control and Error Register Bit Definition. The Error Register has additional logic that is used to generate the ERROR signal. The cutoff driver is used to transmit serial data on to the bus. The outputs switch between a normal HIGH level (VOH) and a cutoff LOW signal – when low the output emitter follower is turned ’off’, thus presenting a high impedance to the bus. If the cutoff driver is disabled, both outputs of the differential pair go to the cutoff state so the bus resource is available for use by other AutoBahn chips sharing the same bus. MOTOROLA 4 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 AUTOBAHN TRANSMIT State Diagram Reset SER (Serial Data) in CUTOFF AUTOBAHN RECEIVE State Diagram Reset New data written into Transmit Register SER differential, Waiting for 15nS Differential SER detected 15nS Timer Expired New data written into Transmit Register [Assert BUSY signal] Waiting for Start bit Transmitting serial data words Start bit observed NO new data written into Transmit Register 4 longword timer expired Waiting for differential SER New data written into Transmit Register New start bit observed Receiving serial data words NO new start bit observed Waiting four longword periods since latest start bit New start bit observed Waiting four longword periods since latest start bit 10nS timer expired 4 longword timer expired [Negate BUSY signal] Waiting for 10nS Figure 2. Transmit and Receive State Diagram THEORY OF OPERATION AND TRANSMIT TIMING PRINCIPLE The AutoBahn is a high speed data mover resource for use in parallel bus systems, such as the VMEbus. It is also suitable for proprietary bus architectures and point–to–point links. All necessary logic, such as multiplexing/ de–multiplexing, control, and timing generation is incorporated on chip. External control signals and a frequency reference must be provided to the device. Arbitration is off loaded to the parallel bus system; thus, no collision detection or protocol overhead is required for the chip. The AutoBahn has three primary operating modes: – Idle and assert a BUSY signal. In a VME type application, this signal is used by the local controller to determine when to arbitrate for the serial bus resource. Transmit Mode To begin a transfer, data is written into the parallel data register. This event starts an internal timeout timer. The AutoBahn transfers the data to the serial transmit register, inserts timing information, and shifts the data out the serial bus. The timing information adds one additional bit into the data stream for every byte of data. Because the data is NRZ, a 900MBit/s data rate translates into a maximum frequency of 450MHz. If a new word has been loaded into the parallel data register, the next transfer will begin. Otherwise, the differential output driver will hold the serial bus at the state of the last data bit transmitted. The bus will be held in this state until new data is loaded into the parallel data register or the timeout time expires. The timeout timer runs for a period of four 32–bit transfer times. The transfer rate is selected through control register select bits. As an example, in 32–bit mode with a transfer rate – Transmit – Receive Figure 2 has been included to aid in understanding the operation of the device. Idle Mode After the device has been reset, the default operating mode is Idle. In the default condition the serial bus is cut off and the receiver is ’listening’ to detect activity on the serial bus. The function of this mode is to detect serial bus activity ECLinPS and ECLinPS Lite DL140 — Rev 3 5 MOTOROLA MC100SX1451FI100 of 100MByte/s, a new data word is transferred approximately every 40ns (32 data bits + 4 synchronization bits = 36 bits * 1.1ns/bit). For this case, the timeout timer runs for approximately 160ns. The timeout timer is re–started every time a new serial word transmission begins. Since the AutoBahn only has one level of elastic storage, the receiver memory interface must be able to support the same transfer rate as the transmitter. Receive Mode When the AutoBahn is operating in receive mode it strips off the timing information and clocks the data into the serial register. When the register is full, it transfers the data into the parallel data register and asserts the FULL signal pin to indicate the presence of data. The interface hardware detects the presence of new data and reads out the content of the data register. In receive mode, a timeout timer is also employed to handle the end of data transfer termination. The receive timeout timer operates in the same manner as the transmit timeout timer. Every time new data is received, the timeout timer is re–started. If no data is received, the timeout timer will expire and the part will return to the idle state. Typical data transmission waveforms are shown in Figure 3 and Figure 4. The transmit timeout timer serves two functions. It allows the termination of block data transfers without the need for explicit external control. After the last word in a data block is written into the device, the timeout timer will expire and the device will return to the idle state. More importantly, it allows the AutoBahn to support a broad range of data transfer rates. If a hardware design application only needs capacity to transfer data at 60MByte/s, the AutoBahn will automatically burst the data out at 100MByte/sec and insert pauses in the serial data stream to accommodate the slower parallel data transfer rate. This means the user can tailor the design of the parallel memory interface to meet the needs of the application, while still taking advantage of the performance of the AutoBahn. TRANSMITTING AUTOBAHN D00:D31 WRITE DATA REGSEL R/W STRB FULL SER CUTOFF SYNC D0 D1 D2 D3 D31 CUTOFF TIMEOUT DELAY BUSY D00:D31 READ DATA RECEIVING AUTOBAHN REGSEL R/W STRB FULL SER CUTOFF SYNC D0 D1 D2 D3 D31 CUTOFF TIMEOUT DELAY BUSY Figure 3. Transmit and Receive Timing for a Single 32–Bit Longword Transmissions MOTOROLA 6 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 TRANSMITTING AUTOBAHN D00:D31 WRITE DATA WRITE DATA WRITE DATA WRITE DATA 36–BIT SERIAL 36–BIT SERIAL WRITE DATA REGSEL R/W STRB FULL CUTOFF SER 36–BIT SERIAL 36–BIT SERIAL BUSY D00:D31 READ DATA READ DATA READ DATA RECEIVING AUTOBAHN REGSEL R/W STRB FULL CUTOFF SER 36–BIT SERIAL 36–BIT SERIAL 36–BIT SERIAL 36–BIT SERIAL BUSY Figure 4. Transmit and Receive Timing for Burst Transmission APPLICATION CIRCUIT AND POWER SUPPLY VCCT (+5V) ADDRESS BUS VCCT Note 1 0.22µF DATA BUS VEET (3,11,18,30 36,43,51,59) GND (56) VCCE (41) Note 2 VCCO 40pF 0.22µF (26) AUTOBAHN MC100SX1451 VEE GND LOGIC (PAL) VCCE (+5V) (8) VCCX 0.22µF 40pF (22) VEEX (20) GND SER SER Note 1: Capaitor located close to every pin. Note 2: If separate supply planes for ECL and TTL are available, the inductor is not necessary. Note 3: A common ground plane for TTL and ECL must be used. SERIAL BUS OSCILLATOR Figure 5. Simplified Application Circuit ECLinPS and ECLinPS Lite DL140 — Rev 3 Note 3 GND AUTOBAHN FOSC Note 3 VCC GND VCCE (+5V) C1 2700pF 47,55,63) 1µH CONTROL SIGNALS 32–BIT DATA BUS VCCx STRB FULL R/W C1 REGSEL (7,14,33,39, Figure 6. Power Supply Filtering 7 MOTOROLA MC100SX1451FI100 PECL DESIGN CONSIDERATIONS The differential serial bus is realized using PECL (Positive Emitter Coupled Logic). PECL is normal ECL with the VCC and VEE power supplies levels shifted from ground and –5.2V to +5.0V and ground respectively. This change simplifies the requirements of interfacing high speed ECL circuitry and TTL circuitry on the same chip and improves the user system architecture because only a single power supply is required. The output driver circuitry is an open emitter, emitter follower which generates PECL levels when terminated by a pull down resistor to an appropriate reference voltage. The output emitter follower circuitry is optimized to drive transmission lines. To minimize line reflections, the transmission line should be terminated with the line characteristic impedance, in most cases 50Ω. The simplest and most robust method of realizing this termination in PECL is with a resistor divider network referenced to VCC. This means the PECL output levels and the termination voltage will then be referenced to the same VCC supply. CARD 1 PARALLEL BUS INTERFACE Figure 8 is the equivalent circuit for the serial bus. Resistors R1 and R2 are used to implement a simple voltage divider with the characteristic impedance of the transmission line. The following equations are used to solve for these values. R1 = R2 ({VCC – VTT}/{VTT – VEE}) R2 = ZO ({VCC – VEE}/{VCC – VTT}) VTT = VCC (R2/{R1 + R2}) For the typical setup: VCC = 5.0V; VEE = GND; VTT = 3.0V; and ZO = 50Ω R2 = 50 ({5 – 0}/{5–3}) = 125Ω R1 = 125 ({5–3}/{3–0}) = 83.3Ω More detailed information about PECL and thevenin equivalent termination schemes can be found in Motorola Application Note AN1406/D – “Designing with PECL”. CARD 2 AUTO BAHN PARALLEL BUS INTERFACE CARD N AUTO BAHN PARALLEL BUS INTERFACE AUTO BAHN RESISTOR DIVIDER TERMINATION NETWORK BACKPLANE TRADITIONAL PARALLEL BUS DIFFERENTIAL BI–DIRECTIONAL SERIAL BUS Figure 7. Typical Bus Application AUTOBAHN 1 AUTOBAHN N VCC VCC R1 R2 R1 VCC R1 CONTROLLED IMPEDANCE TRANSMISSION LINES R2 R2 VCC R1 R2 Figure 8. Equivalent Circuit for Serial Bus MOTOROLA 8 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 CONTROL AND ERROR REGISTER BIT DEFINITIONS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRITE: RESERVED FACTORY TEST CLEAR FACTORY TEST FACTORY TEST 16–/32–BIT MODE FACTORY TEST IGNORE TIMEOUT ERROR 15 14 13 12 11 CONTROL 10 9 8 7 6 5 4 3 2 1 0 READ: RESERVED SYNC BIT ERROR FACTORY TEST CLEAR FACTORY TEST WORD MISSING ERROR FACTORY TEST OVERWRITE ERROR 16–/32–BIT MODE FACTORY TEST IGNORE TIMEOUT Figure 9. Control and Error Register Definitions Clear Asserting this bit clears the internal control logic and terminates any transmit or receive activity. To remove the Clear condition, this bit must be set to a logic ‘H’ which sets the chip into the Idle mode. H Normal Operation L Clear Register must be accessed, and the field must be de–asserted. H L Overwrite Error Flag This bit will be set if the data in the parallel register is overwritten. This can occur in Receive mode if data is not read from the parallel register in a timely manner. The overwrite error does not occur in idle mode. 16/32 Bit Mode This bit defines the data width on the host interface. This feature allows the AutoBahn chip to be used in systems with either 16–bit or 32–bit data width without the need for additional interface hardware. In 16–bit mode, the data bus used is D00 – D15. H 32–bit data width L 16–bit data width H L Overwrite No Overwrite Word Missing Error This bit will be asserted if the second half of a 32–bit transfer is not completed before the time out timer expires. This can occur if the transmitter fails to complete the transfer. This field will be asserted only after the timeout timer expires. Factory Test These bits are used by the manufacturer for testing the product. It must be set to a logic ‘H’ state for proper operation. H Normal Operation H L Word Missing Error No Error SYNC Bit Missing Error This bit will be asserted if the AutoBahn detects that a SYNC bit has not been received at the proper time by the PISO Control Logic. If this bit has been asserted then the data has been corrupted. Ignore Timeout This bit is used to disable the timeout timer for the transmitter. The purpose of this bit is to allow for the establishment of permanent or temporary dedicated links. When this bit is asserted, the timeout timer will be ignored by the PISO Control Logic. This bit only needs to be set in the transmitting AutoBahn chip. To exit this mode, the Control ECLinPS and ECLinPS Lite DL140 — Rev 3 Normal Operation Disable Timeout H L 9 SYNC Bit Missing Error No Error MOTOROLA MC100SX1451FI100 Reserved Bits All reserved bits are allocated for future enhancements. The user must write logic ‘H’ values into these bits. Reserved bits are read back as ‘do not care’. cooling techniques are obvious user–controlled variables; however, PCB substrate material, layout density, size of the air gap between the board and the package, amount of exposed copper interconnect, use of thermally conductive epoxies, and the number of boards in a chassis can all have significant impacts on the thermal performance of the system. PCB substrates have different thermal characteristics which should be explored when considering alternatives. The user should also account for the different power dissipations of various components in the system and space them on the PCB accordingly. In this way the heat load is spread across a larger area and “hot spots” do not appear in the layout. Copper interconnect traces act as heat radiators; therefore, improved thermal dissipation can be achieved through the addition of interconnect traces on the top layer. Finally, thermally conductive epoxies can accelerate the transfer of heat from the device to the PCB where it can be more easily transferred to the ambient. The following equation can be used to estimate the junction temperature of a device in a given environment: TJ = TA + PD ∗ ΘJA CRYSTAL OSCILLATOR REQUIREMENTS The AutoBahn requires a high quality frequency source (FOSC) which is used as the reference for the PLL Clock Generator. The performance requirements were targeted to provide the AutoBahn chip appropriate design margin for the serial data transfer operation as well as to allow the user flexibility is selecting a commercially available low cost crystal oscillator. Below is a list of the key performance attributes of the crystal oscillator. Parameter Frequency Stability Output Levels Duty Cycle Rise/Fall Time Operating Range Startup Time Rating 25.000MHz ±100ppm TTL 45% / 55% at 1.5V ≤7nsec 0°C to 70°C 10msec TJ TA PD ΘJA There are many suppliers of high quality crystal oscillator frequency sources which meet or exceed the above requirements. One such supplier is JVC. Their part numbers for 25MHz oscillators are as follows: VX4321–2500 (Metal Can) or SMC2500 (SMD). The power dissipation is comprised of two elements: the internal gate power and the power associated with the output signals. Essentially, the two contributors can be calculated separately, then added to give the total power dissipation for the device. The source of the output power distribution depends on whether the device is transmitting or receiving. In transmit mode, the PECL outputs are dissipating power, while in receive mode, the parallel outputs are dissipating dynamic power. The worst case condition, when the AutoBahn is in receive mode, is described below. THERMAL CONSIDERATIONS As in any system, proper thermal management is essential to establish the appropriate trade–off between performance, density, reliability, and cost. In particular, the designer should be aware of the reliability implications of continuously operating semiconductor devices at high junction temperatures. The increasing use of surface mount devices (SMD) is putting a greater emphasis on the need for better thermal system management. SMD devices require less board space than their through–hole equivalents; so, designs incorporating SMD technologies have a higher thermal density. To optimize the thermal management of the system, it is imperative that the user understand all the variables which contribute to the device junction temperature. By proper package selection, the vendor can select the proper package and die attach method to decrease the thermal resistance and thus the junction temperature of the device. The user has the greatest control of additional variables which commonly impact the thermal performance of the device. Ambient temperatures, air flow, and related MOTOROLA Junction Temperature Ambient Temperature Power Dissipation Average Package Thermal Resistance (Junction – Ambient) PD = Pstatic + Po (TTL) where Pstatic = ICC * VCC VCC ICC and Po (TTL) = No* CL * FD * VS ^2 CL FD VS No 10 Operating voltage Static DC Current Capacitive load (in pF) Parallel Data Rate (0.5 * # MBits/sec) Output Swing Number of outputs (16 or 32) ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 For a typical application: CL FD VS No VCC ICC The ceramic quad flat package selected is manufactured from an Aluminum nitride (AlN) ceramic material for optimum thermal performance. A table of the average ΘJA values for this package under various air flow conditions is listed below: 20 pF 0.5* 100 MBits/s 3.8 V 32 outputs 5V 700 mA PD = 470 * 5 + 32 * 20pF * 25 MHz*3.82 Air Flow (m/sec) ΘJA (°C/W) 0 40 1 32 2 23 With this information, the user can estimate the junction temperature of the device in their application. PD = 3.5 + 0.231W = 3.73W MAXIMUM RATINGS* Value Unit VCC Symbol Power Supply (VEE = 0V) Parameter –0.5 to 6.5 V VIN Input Voltage (VEE = 0V) –0.5 to 6.5 V IOUT PECL Output Current 50 100 mA IOUT–TTL TTL Output Current TA Operating Temperature Range TSTG Storage Temperature Range Continuous Surge TBD 0 to 70 °C –50 to +175 °C TJ Maximum Junction Temperature 175 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. TTL DC CHARACTERISTICS (VCCT = VCC = VCCO = 5.0V ±5%) Symbol Parameter IIH Input HIGH Current IIL Input LOW Current VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IOZ Tri–State Current ICC Device Current Drain Min Typ Max Unit 0.7 µA VIN = VCC –0.6 mA VIN = GND V IOH = –2mA V IOL = 5.0mA 2.5 0.5 2.0 Condition V 0.8 700 V ±15 µA 760 mA 100E PECL DC CHARACTERISTICS (VCCT = VCC = VCCO = 5.0V ±5%) Symbol Parameter Min Max Unit 200 µA IIH Input HIGH Current IIL Input LOW Current 0.500 VOH Output HIGH Voltage 3.975 4.25 V VCUT Output CUTOFF Voltage 3.000 3.07 V VIH Input HIGH Voltage 3.835 4.12 V VIL Input LOW Voltage 3.000 3.07 V Condition µA Note 1. VPP (DC) Input Sensitivity 150 mV Note 2. NOTE: PECL levels are referenced to VCC and will vary 1:1 with power supply. The outputs are loaded with an equivalent 25Ω termination to +3.0V. The values shown are for VCC = VCCO = VCCT = 5.0V. 1. Valid when the equivalent termination voltage is 3.0V to assure proper operation. 2. VPP is the minimum differential input voltage required to assure proper operation. ECLinPS and ECLinPS Lite DL140 — Rev 3 11 MOTOROLA MC100SX1451FI100 AC CHARACTERISTICS (VCC = VCCO = VCCT = 5.0V ±5%; VEE = VEEX = VEET = GND) Symbol ts 25°C 70°C Min T2 2 1.0 1.0 1.0 ns T3 2 3.0 3.0 3.0 ns T4 2 4.0 T5 2 3.0 Characteristic Setup Time R/W→STRB REGSEL→STRB Data→STRB 0°C Wave– form Name Typ* Max Min Typ* Max Min Typ* Max Unit Condition th Hold Time tpd Propagation Delay STRB→FULL th Hold Time tpd Propagation Delay SER→BUSY T6 3 6.0 ts Setup Time R/W→STRB REGSEL→STRB T7 4 2.0 2.0 2.0 ns th Hold Time T8 4 1.0 1.0 1.0 ns tpd Propagation Delay STRB→Data Valid T9 4 7.0 8.5 18.0 7.0 8.5 18.0 7.0 8.5 18.0 ns Note 1 on page 13 tpd Propagation Delay STRB→FULL T10 4 5.5 8.0 10.0 5.5 8.0 10.0 5.5 8.0 10.0 ns Note 1 on page 13 tpd Propagation Delay STRB→Data Invalid T11 4 12.0 14.0 17.0 12.0 14.0 17.0 12.0 14.0 17.0 ns Note 1 on page 13 ts Setup Time R/W→STRB REGSEL→STRB Data→STRB T12 5 1.0 1.0 1.0 ns T13 5 3.0 3.0 3.0 ns T14 5 3.0 3.0 3.0 ns STRB→R/W STRB→REGSEL STRB→Data STRB→R/W STRB→REGSEL 6.0 9.0 4.0 6.0 9.0 3.0 8.0 10.0 6.0 4.0 6.0 9.0 3.0 8.0 10.0 6.0 ns ns 8.0 10.0 ns th Hold Time th Hold Time tpw Pulse Width STRB T15 5 7.0 ts Setup Time R/W→STRB REGSEL→STRB T16 6 2.0 2.0 2.0 ns th Hold Time T17 6 2.0 2.0 2.0 ns tpd Propagation Delay STRB→Data Valid T18 6 7.0 tpw Pulse Width STRB T19 6 7.0 tpd Propagation Delay STRB→Data Invalid T20 6 14.0 tr, tf TTL Rise/Fall Time — — 3.0 6.1 12.6 3.0 ns 10 – 90% 15pF Load tr, tf PECL Rise/Fall Time — — 200 770 930 200 ps 20 – 80% STRB→R/W STRB→REGSEL STRB→Data STRB→R/W STRB→REGSEL 12.0 8.5 7.0 18.0 7.0 12.0 7.0 17.0 12.0 8.5 14.0 7.0 18.0 7.0 12.0 7.0 17.0 12.0 8.5 14.0 ns 18.0 ns 12.0 ns 17.0 ns * Values for 0°C and 70°C are target values. Typicals for 25°C are taken from a small measurement database. Min and Max values are derived from using 3 sigmas point of the data distribution and will be added when the data becomes available. MOTOROLA 12 ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 Note 1: Propagation Delay T9 Becasue the typical use of the AutoBahn is in a shared bus system, the propagartion delay T9 (STRB –> data valid) is the time between the falling edge of STRB and OUTPUT ACTIVE of the receiver. The crosspoint of 1.5V is dependent on the bus environment. See Figure 10. T9 Propagation Delay T10 This value is taken with the high impedance active probe. With a higher load at the pin, this value will be higher up to 5%. T11 STRB Load C=15pF DATA 1.5V R=1kΩ 0V Propagation Delay T11 The definition of the propagation delay T11 corresponds to T9. In this case, T11 is the time between the rising edge of STRB and the HIGH IMPEDANCE of the receiver. That means, other talker of the common bus have to wait for T11 to send datas to the bus. See Figure 10. HIGH Z OUTPUT ACTIVE HIGH Z Figure 10. Definition of the Waveforms STRB → Data Valid TIMING WAVEFORMS 1.5V STRB (I) SER (O) SER (O) 50% T1 NOTE 2: T1 (STRB to SER differential) is indeterminate, varying from 3 to 9 bit clock cycles due to synchronization circuitry to avoid metastability. Waveform 1. Start of Transmit Timing R/W (I) 1.5V 1.5V REGSEL (I) 1.5V 1.5V D00:D31 (I) HIGH Z DATA VALID1 STRB (I) 1.5V HIGH Z1 1.5V T3 FULL (O) 1.5V T2 T4 NOTE 3 T5 NOTE 3: STRB deassertion to next FULL a minimum of 18 nsec. Waveform 2. Transmit Mode – Data Transfer Handshake ECLinPS and ECLinPS Lite DL140 — Rev 3 13 MOTOROLA MC100SX1451FI100 SER (I) SER (I) 50% 1.5V BUSY (O) T6 Waveform 3. Timing for Detection of a Steady–State Differential Condition on the Serial Bus R/W (I) 1.5V 1.5V REGSEL (I) 1.5V 1.5V HIGH Z1 D00:D31 (I) STRB (I) DATA VALID1 1.5V T8 FULL (O) 1.5V T7 T9 T10 T11 Waveform 4. Receive Mode – Data Transfer Handshake R/W (I) 1.5V 1.5V REGSEL (I) 1.5V 1.5V D00:D31 (I) HIGH Z DATA VALID1 STRB (I) HIGH Z1 1.5V 1.5V 1.5V T13 T12 T14 T15 Waveform 5. Write to Control Register R/W (I) 1.5V 1.5V REGSEL (I) 1.5V 1.5V HIGH Z1 D00:D31 (I) STRB (I) DATA VALID1 1.5V T17 T16 T18 T19 T20 Waveform 6. Read from the Control and Error Registers MOTOROLA 14 ECLinPS and ECLinPS Lite DL140 — Rev 3 D09 VCCT D08 D07 D06 VEET D05 VCCE D04 VCCT D03 D02 VEET D01 D00 VCCT MC100SX1451FI100 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D10 49 32 BUSY D11 50 31 FULL VEET 51 30 VEET D12 52 29 REGSEL D13 53 28 R/W D14 54 27 STRB VCCT 55 26 VCCO VCC 56 25 SER MC100SX1451 D18 61 20 VEEX D19 62 19 C1 VCCT 63 18 VEET D20 64 17 ERROR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D31 FOSC D30 21 VCCT 60 D29 D17 D28 VCCX VEET 22 D27 59 D26 VEET VEE RESET VCCT 23 D25 58 D24 D16 D23 SER VEET 24 D22 57 D21 D15 Figure 11. Pinout: 64–Lead CQFP (Top View) ECLinPS and ECLinPS Lite DL140 — Rev 3 15 MOTOROLA MC100SX1451FI100 OUTLINE DIMENSIONS FI SUFFIX CERAMIC QFP PACKAGE CASE 963–02 ISSUE A L B 33 DETAIL A S D S H A–B S D DETAIL A F N J 17 64 V M B 0.20 (0.008) L –A–, –B–, –D– 0.20 (0.008) –B– –A– S C A–B 32 M 49 P B 0.05 (0.002) A–B 48 16 1 D BASE METAL –D– 0.02 (0.008) A 0.20 (0.008) C A–B M S D M C A–B S D S VIEW ROTATED 90 _ CLOCKWISE S 0.05 (0.002) A–B SECTION B–B S 0.20 (0.008) C M H A–B S D S E –H– –C– SEATING PLANE 0.01 (0.004) G H DATUM PLANE DETAIL C DIM A B C D E F G H J K L N P Q R S T U V W X U T R –H– Q DATUM PLANE K W X DETAIL C MOTOROLA NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DEFINE MAXIMUM CERAMIC BODY DIMENSION INCLUDING GLASS PROTRUSION AND MISMATCH BETWEEN CERAMIC BODY AND COVER. 16 MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 3.00 4.11 0.30 0.45 2.54 3.22 0.30 0.40 0.80 BSC 0.45 0.89 0.13 0.23 0.65 0.95 12.00 REF 0.13 0.17 0.40 BSC 0_ 7_ 0.13 0.30 16.95 17.45 0.13 ––– 0_ ––– 16.95 17.45 0.35 0.45 1.60 REF INCHES MIN MAX 0.547 0.555 0.547 0.555 0.118 0.162 0.012 0.018 0.100 0.127 0.012 0.016 0.031 BSC 0.018 0.035 0.005 0.009 0.026 0.037 0.472 REF 0.005 0.007 0.016 BSC 0_ 7_ 0.005 0.012 0.667 0.687 0.005 ––– 0_ ––– 0.667 0.687 0.014 0.018 0.063 REF ECLinPS and ECLinPS Lite DL140 — Rev 3 MC100SX1451FI100 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 Mfax: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://motorola.com/sps ◊ ECLinPS and ECLinPS Lite DL140 — Rev 3 17 MC100SX1451FI100/D MOTOROLA