Revised January 1999 MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HCT74 utilizes advanced silicon-gate CMOS technology to achieve operation speeds similar to the equivalent LS-TTL part. It possesses the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positivegoing transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. The 74HCT logic family is functionally and pin-out compatible with the standard 74LS logic family. All inputs are pro- tected from damage due to static discharge by internal diode clamps to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features ■ Typical propagation delay: 20 ns ■ Low quiescent current: 40 µA maximum (74HCT Series) ■ Low input current: 1 µA maximum ■ Fanout of 10 LS-TTL loads ■ Meta-stable hardened Ordering Code: Order Number MM74HCT74M Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74HCT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide M74HCT74MTC MTC14 MM74HCT74N N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs PR CLR CLK D Q Q L H X X H L H L X X L H L L X X H H ↑ H H H ↑ L L H H H L X Q0 Q0 H H (Note 1) (Note 1) H L Q0 = the level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level. © 1999 Fairchild Semiconductor Corporation DS005360.prf www.fairchildsemi.com MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear February 1984 MM74HCT74 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN ) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA 600 mW 500 mW V 0 VCC V −40 +85 °C 500 ns (tr, tf) Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) (Soldering 10 seconds) Units 5.5 Input Rise or Fall Times Power Dissipation (PD) S.O. Package only Max 4.5 (VIN, VOUT) Operating Temperature Range (TA) −65°C to +150°C (Note 4) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) 260°C DC Electrical Characteristics VCC = 5V ±10% (unless otherwise specified) Symbol VIH Parameter TA = 25°C Conditions Typ Minimum HIGH Level TA = −40° to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VOL IIN ICC VIN = VIH or VIL |IOUT| = 20 µA VCC VCC− 0.1 VCC− 0.1 VCC− 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V |IOUT| = 4.8 mA, VCC = 5.5V 5.2 4.98 4.84 4.7 V Maximum LOW Level VIN = VIH or VIL Voltage |IOUT| = 20 µA Maximum Input 0 0.1 0.1 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V |IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 V ±0.0.5 ±0.5 ±1.0 µA VIN = VCC or GND, Current VIH or VIL Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA 2.0 20 80 µA VIN = 2.4V or 0.5V (Note 5) 0.3 0.4 0.5 mA Note 5: This is measured per pin. All other inputs are held at VCC Ground. 3 www.fairchildsemi.com MM74HCT74 Absolute Maximum Ratings(Note 2) (Note 3) MM74HCT74 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Limit Units 50 30 MHz 18 30 ns 18 30 ns 20 ns 20 ns −3 0 ns 8 16 ns Frequency from Clock to Q or Q tPHL, tPLH Maximum Propagation Delay Clock to Q or Q tPHL, tPLH Maximum Propagation Delay from Preset or Clear to Q or Q tREM Minimum Removal Time, Preset or Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock, Preset or Clear AC Electrical Characteristics VCC = 5.0V ± 10%, CL = 50 pF, tr = tf = 6 ns unless otherwise specified Symbol Parameter Conditions TA = 25°C Typ fMAX Maximum Operating TA = −40° to +85°C Units Guaranteed Limits 27 21 MHz 21 35 44 ns 21 35 44 ns 20 25 ns 20 25 ns −3 0 0 ns 9 16 20 ns 500 500 ns 15 19 ns Frequency tPHL, tPLH Maximum Propagation Delay from Clock to Q or Q tPHL, tPLH Maximum Propagation Delay from Preset or Clear to Q or Q tREM Minimum Removal Time Preset or Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock, Preset or Clear tr, tf Maximum Clock Input Rise and Fall Time tTHL, tTLH Maximum Output Rise and Fall Time CPD Power Dissipation (per flip-flop) 10 pF Capacitance (Note 6) CIN Maximum Input 5 10 10 Capacitance Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF MM74HCT74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCT74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HCT74 Dual D-Type Flip-Flop with Preset and Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)