MAXIM MAX3750

19-4792; Rev 1; 1/99
KIT
ATION
EVALU
E
L
B
AVAILA
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
Features
The MAX3750/MAX3751 are +3.3V, Fibre Channel port
bypass ICs that include a high-speed multiplexer and
output buffer stage for hot swapping a storage device.
These devices are optimized for use in a Fibre Channel
arbitrated loop topology.
The MAX3750 has a 2.125Gbps data rate, while the
MAX3751’s data rate is 1.0625Gbps. Total power consumption (including output currents) is low: just 190mW
for the MAX3750 and 180mW for the MAX3751. Low
10ps jitter makes these devices ideal for cascaded
topologies. The output driver circuitry is tolerant of load
mismatches commonly caused by board vias and
inductive connectors. On-chip termination reduces
external part count and simplifies board layout.
♦ Single +3.3V Supply
♦ Low Jitter: 10ps
♦ Low Power Consumption
190mW (MAX3750)
180mW (MAX3751)
♦ Large Output Signal Swing: >1000mVp-p
♦ Mismatch Tolerant Output Driver Stage
♦ 150Ω Differential On-Chip Termination on All Inputs
♦ 150Ω On-Chip Back Termination on All Output
Ports
Ordering Information
Applications
PART
2.125Gbps Fibre Channel Arbitrated Loop
1.0625Gbps Fibre Channel Arbitrated Loop
Mass Storage Systems
RAID/JBOD Applications
TEMP. RANGE
PIN-PACKAGE
MAX3750CEE
0°C to +70°C
16 QSOP
MAX3751CEE
0°C to +70°C
16 QSOP
OUT-
GND
IN+
MAX3750
MAX3751
SEL
FC-AL
DISK DRIVE
OUTC4
VCC
LOUT-
LOUT+
C5
OUT+
IN-
LIN-
LIN+
C3
OUT+
RX
C1
TX
LOUT-
LOUT+
LIN-
LIN+
LOUT-
LOUT+
LIN-
LIN+
RX
C2
TX
C8
RX
C7
TX
FC-AL
DISK DRIVE
FC-AL
DISK DRIVE
Typical Application Circuit
GND
OUT+
IN+
SEL
OUT-
IN-
MAX3750
MAX3751
C6
VCC
3.3V
IN+
MAX3750
MAX3751
GND
3.3V
SEL
IN-
VCC
3.3V
MICROPROCESSOR
C1–C8 = 100nF
THREE MAX3750/MAX3751s CASCADED IN AN FC-AL APPLICATION
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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MAX3750/MAX3751
General Description
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V
Voltage at LOUT+, LOUT-,
OUT+, OUT- ..............................(VCC - 1.65V) to (VCC + 0.5V)
Current Out of LOUT+, LOUT-, OUT+, OUT- ...................±22mA
Voltage at SEL, LIN+, LIN-, IN+, IN- ..........-0.5V to (VCC + 0.5V)
Differential Voltage at (LIN+ - LIN-), (IN+ - IN-).....................±2V
Continuous Power Dissipation (TA = +70°C)
16 QSOP (derate 8.3mW/°C above +70°C) .................667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ...............................-55°C to 150°C
Lead Soldering Temperature (soldering, 10sec).............+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.)
PARAMETER
Supply Current
Data Input Voltage Swing
Differential Input Impedance
Output Voltage at LOUT± and OUT±
TYP
MAX
MAX3750 (Note 1)
CONDITIONS
57
84
MAX3751 (Note 1)
54
78
150
2200
172
mV
Ω
1600
mV
Total differential signal, peak-to-peak
150Ω load, total differential signal,
peak-to-peak
TTL Input Current
TTL Input Low
TTL Input High
MIN
200
132
1000
-10
-0.3
2
10
0.8
VCC + 0.3
UNITS
mA
µA
V
V
Note 1: Output currents included.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.)
PARAMETER
Data Rate
CONDITIONS
MIN
TYP
MAX3750
2.125
MAX3751
1.0625
200
MAX
Gbps
Data Input Voltage Swing
Total differential signal, peak-to-peak
2200
Output Edge Speed
IN± →OUT±, IN± →LOUT±
MAX3750
160
MAX3751
325
Deterministic Jitter
IN± →OUT±, IN± →LOUT±, LIN± →OUT±
MAX3750, peak-to-peak (Notes 2, 4)
10
MAX3751, peak-to-peak (Notes 3, 4)
10
Random Jitter
IN± →OUT±, IN± →LOUT±, LIN± →OUT±
MAX3750, RMS (Note 2)
1.6
MAX3751, RMS (Note 3)
1.6
Prop Delay
IN± →OUT±, IN± →LOUT±, LIN± →OUT±
MAX3750
300
MAX3751
442
Note 2: Input tR and tF < 150ps, 20% to 80%.
Note 3: Input tR and tF < 300ps, 20% to 80%.
Note 4: Deterministic jitter is measured with 20 bits of the k28.5 pattern (00111110101100000101).
2
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UNITS
mV
ps
ps
ps
ps
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
SUPPLY CURRENT vs. TEMPERATURE
MAX3750/51 toc01
59
SUPPLY CURRENT (mA)
58
57
MAX3750
56
55
54
MAX3751
53
52
51
50
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 8, 16
GND
2
LOUT+
Electrical Ground
Noninverted Port Data Output
3
LOUT-
Inverted Port Data Output
6
OUT+
Noninverted Data Output
7
OUT-
Inverted Data Output
9
SEL
Select Input:
SEL = Low: IN± → OUT±
SEL = High: LIN± → OUT±
10
LIN-
Inverted Port Data Input
11
LIN+
Noninverted Port Data Input
12, 13
VCC
Positive Supply Voltage
14
IN-
Inverted Data Input
15
IN+
Noninverted Data Input
_______________________________________________________________________________________
3
MAX3750/MAX3751
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
_________________Circuit Description
Layout Techniques
The MAX3750/MAX3751 are high-frequency products.
The performance of the circuit is largely dependent
upon layout of the circuit board. Use a multilayer circuit
board with dedicated ground and VCC planes. Power
supplies should be capacitively bypassed to the
ground plane with surface-mount capacitors placed
near the power-supply pins.
A simplified block diagram of the single port bypass is
shown in Figure 1. IN+ and IN- drive an input buffer
(INBUFF) with 150Ω of internal differential input termination. INBUFF drives an output buffer (LOBUFF) and
an input to a multiplexer (MUX).
A low TTL input at SEL selects the signal path of
INBUFF through MUX to the output buffer (OUTBUFF).
When SEL has a high TTL logic level present the signal
path is into LIBUFF, through MUX, to OUTBUFF.
Low-Frequency Cutoff
The low-frequency cutoff is determined by the input
resistance and the coupling capacitor as illustrated by
the following equation:
fC = 1 / (2πRC)
LOBUFF
LIN-
LIN+
LOUT-
In a typical system where R = 150Ω and C = 100nF,
resulting in fC = 10kHz.
LOUT+
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
LIBUFF
OUTBUFF
IN+
MUX
INBUFF
D0
OUT+
Q
IN-
OUT-
D1
SEL
MAX3750
MAX3751
VCC
TTLIN
GND
SEL
NOTE: SEE INTERNAL INPUT/OUTPUT SCHEMATICS FOR DETAILED TERMINATIONS (FIGURES 2–5).
Figure 1. MAX3750/MAX3751 Block Diagram
4
_______________________________________________________________________________________
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
MAX3750/MAX3751
VCC
75Ω
ESD
STRUCTURES
75Ω
VCC
(L)OUT+
(L)OUT-
SEL
ESD
STRUCTURE
GND
GND
Figure 2. LOUT/OUT Pins Internal Input/Output Schematic
Figure 3. SEL Pin Internal Input/Output Schematic
VCC
ESD
STRUCTURE
IN+
MAX3750
MAX3751
300Ω
(L)IN+
OUT+
300Ω
IN-
OUT-
IN+
OUT+
(L)IN75Ω
75Ω
43Ω
43Ω
MAX3750
MAX3751
176Ω
43Ω
IN-
176Ω
43Ω
OUT-
GND
Figure 4. LIN/IN Pins Internal Input/Output Schematic
Figure 5. 50Ω Termination Applications
_______________________________________________________________________________________
5
Pin Configuration
TOP VIEW
GND 1
16 GND
LOUT+ 2
15 IN+
LOUT- 3
14 IN-
GND 4
GND 5
MAX3750
MAX3751
13 VCC
12 VCC
OUT+ 6
11 LIN+
OUT- 7
10 LIN-
GND 8
9
SEL
QSOP
Package Information
QSOP.EPS
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.