19-3062; Rev 0; 12/03 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs For 10-bit compatible devices, refer to the MAX5522– MAX5525 data sheet. For 8-bit compatible devices, refer to the MAX5512–MAX5515 data sheet. Applications Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory or Field Programmable Voltage and Current Sources Industrial Process Control and Remote Industrial Devices Remote Data Conversion and Monitoring Chemical Sensor Cell Bias for Gas Monitors Programmable LCD Bias Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Features ♦ Ultra-Low 5µA Supply Current ♦ Shutdown Mode Reduces Supply Current to 0.18µA (max) ♦ Single +1.8V to +5.5V Supply ♦ Small 4mm x 4mm x 0.8mm Thin QFN Package ♦ Internal Reference Sources 8mA of Current (MAX5533/MAX5535) ♦ Flexible Force-Sense-Configured Rail-to-Rail Output Buffers ♦ Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRECompatible Serial Interface ♦ TTL- and CMOS-Compatible Digital Inputs with Hysteresis ♦ Glitch-Free Outputs During Power-Up Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5532EUA -40°C to +85°C 8 µMAX MAX5533EUA -40°C to +85°C 8 µMAX MAX5534ETC -40°C to +85°C 12 Thin QFN-EP* MAX5535ETC -40°C to +85°C 12 Thin QFN-EP* *EP = Exposed paddle (internally connected to GND). Selector Guide PART OUTPUTS REFERENCE MAX5532EUA Unity gain External TOP MARK — MAX5533EUA Unity gain Internal — MAX5534ETC Force sense External AACM MAX5535ETC Force sense Internal AACN Pin Configurations TOP VIEW CS 1 SCLK 2 DIN 3 8 OUTA MAX5532 MAX5533 REFIN(MAX5532) 4 REFOUT(MAX5533) 7 GND 6 VDD 5 OUTB µMAX Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5532–MAX5535 General Description The MAX5532–MAX5535 are dual, 12-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering Rail-to-Rail® buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 5µA, making the devices suitable for low-power and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18µA. The MAX5532–MAX5535 use a 3-wire serial interface that is compatible with SPI™, QSPI™, and MICROWIRE™. Upon power-up, the MAX5532–MAX5535 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that need to be off during power-up. The zero-scale outputs enable glitch-free power-up. The MAX5532 accepts an external reference input and provides unity-gain outputs. The MAX5533 contains a precision internal reference and provides a buffered external reference output with unity-gain DAC outputs. The MAX5534 accepts an external reference input and provides force-sense outputs. The MAX5535 contains a precision internal reference and provides a buffered external reference output with force-sense DAC outputs. The MAX5534/MAX5535 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin QFN package. The MAX5532/ MAX5533 are available in an 8-pin µMAX package. All devices are guaranteed over the extended -40°C to +85°C temperature range. MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUTA, OUTB to GND .................................-0.3V to (VDD + 0.3V) FBA, FBB to GND .......................................-0.3V to (VDD + 0.3V) SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V) REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 12-Pin Thin QFN (derate 16.9mW/°C above +70°C).....1349mW 8-Pin µMAX (derate 5.9mW/°C above +70°C) .............471mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX VDD = 5V, VREF = 4.096V ±4 ±8 VDD = 1.8V, VREF = 1.024V ±4 ±8 Guaranteed monotonic, VDD = 5V, VREF = 4.096V ±0.2 ±1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.024V ±0.2 ±1 VDD = 5V, VREF = 4.096V ±1 ±20 VDD = 1.8V, VREF = 1.024V ±1 ±20 VDD = 5V, VREF = 4.096V ±2 ±4 VDD = 1.8V, VREF = 1.024V ±2 ±4 UNITS STATIC ACCURACY (MAX5532/MAX5534 EXTERNAL REFERENCE) Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) N INL DNL VOS 12 Gain-Error Temperature Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V mV µV/°C ±2 GE LSB LSB Offset-Error Temperature Drift Gain Error (Note 3) Bits LSB ±4 ppm/°C 85 dB STATIC ACCURACY (MAX5533/MAX5535 INTERNAL REFERENCE) Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) N INL DNL VOS 12 ±4 ±8 VDD = 1.8V, VREF = 1.2V ±4 ±8 Guaranteed monotonic, VDD = 5V, VREF = 3.9V ±0.2 ±1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.2V ±0.2 ±1 VDD = 5V, VREF = 3.9V ±1 ±20 VDD = 1.8V, VREF = 1.2V ±1 ±20 VDD = 5V, VREF = 3.9V ±2 ±4 VDD = 1.8V, VREF = 1.2V ±2 ±4 Offset-Error Temperature Drift Gain Error (Note 3) 2 Bits VDD = 5V, VREF = 3.9V LSB _______________________________________________________________________________________ mV µV/°C ±2 GE LSB LSB Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Gain-Error Temperature Coefficient Power-Supply Rejection Ratio PSRR 1.8V ≤ VDD ≤ 5.5V TYP MAX UNITS ±4 ppm/°C 85 dB REFERENCE INPUT (MAX5532/MAX5534) Reference-Input Voltage Range Reference-Input Impedance VREFIN RREFIN 0 Normal operation VDD 4.1 In shutdown V MΩ 2.5 GΩ REFERENCE OUTPUT (MAX5533/MAX5535) Initial Accuracy VREFOUT Output-Voltage Temperature Coefficient Line Regulation Load Regulation Output Noise Voltage Short-Circuit Current (Note 6) VTEMPCO No external load, VDD = 1.8V 1.197 1.214 1.231 No external load, VDD = 2.5V 1.913 1.940 1.967 No external load, VDD = 3V 2.391 2.425 2.459 No external load, VDD = 5V 3.828 3.885 3.941 TA = -40°C to +85°C (Note 4) 12 30 ppm/°C VREFOUT < VDD - 200mV (Note 5) 2 200 µV/V 0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V, VREF = 1.2V 0.3 2 0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V, VREF = 3.9V 0.3 2 -150µA ≤ IREFOUT ≤ 0, sinking 0.2 0.1Hz to 10Hz, VREF = 3.9V 150 10Hz to 10kHz, VREF = 3.9V 600 0.1Hz to 10Hz, VREF = 1.2V 50 10Hz to 10kHz, VREF = 1.2V 450 VDD = 5V 30 VDD = 1.8V 14 V µV/µA µVP-P mA Capacitive Load Stability Range (Note 7) 0 to 10 nF Thermal Hysteresis (Note 8) 200 ppm Reference Power-Up Time (from Shutdown) REFOUT unloaded, VDD = 5V 5.4 REFOUT unloaded, VDD = 1.8V 4.4 Long-Term Stability 200 ms ppm/ 1khrs _______________________________________________________________________________________ 3 MAX5532–MAX5535 ELECTRICAL CHARACTERISTICS (continued) MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC OUTPUTS (OUTA, OUTB) Capacitive Driving Capability CL Short-Circuit Current (Note 6) 1000 VDD = 5V, VOUT set to full scale, OUT shorted to GND, source current 65 VDD = 5V VOUT set to 0V, OUT shorted to VDD, sink current 65 VDD = 1.8V, VOUT set to full scale OUT shorted to GND, source current 14 VDD = 1.8V, VOUT set to 0V, OUT shorted to VDD, sink current 14 mA VDD = 5V 3 Coming out of shutdown (MAX5532/MAX5534) VDD = 1.8V 3.8 Coming out of standby (MAX5533/MAX5535) VDD = 1.8V to 5.5V 0.4 DAC Power-Up Time Output Power-Up Glitch pF CL = 100pF FB_ Input Current µs 10 mV 10 pA DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage VIH 4.5V ≤ VDD ≤ 5.5V 2.4 2.7V < VDD ≤ 3.6V 2.0 1.8V ≤ VDD ≤ 2.7V Input Low Voltage VIL Input Leakage Current IIN Input Capacitance CIN V 0.7 x VDD 4.5V ≤ VDD ≤ 5.5V 0.8 2.7V < VDD ≤ 3.6V 0.6 1.8V ≤ VDD ≤ 2.7V V 0.3 x VDD (Note 9) ±0.05 ±0.5 µA 10 pF Positive and negative (Note 10) 10 V/ms 0.1 to 0.9 of full scale to within 0.5 LSB (Note 10) 660 µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time SR 0.1Hz to 10Hz Output Noise Voltage 10Hz to 10kHz 4 VDD = 5V 80 VDD = 1.8V 55 VDD = 5V 620 VDD = 1.8V 476 _______________________________________________________________________________________ µVP-P Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V POWER REQUIREMENTS Supply Voltage Range VDD 1.8 MAX5533/MAX5535 Supply Current (Note 9) IDD MAX5532/MAX5534 Standby Supply Current Shutdown Supply Current IDDSD IDDPD MAX5533/MAX5535 (Note 9) VDD = 5V 7.0 8.0 VDD = 3V 6.4 8.0 VDD = 1.8V 7.0 8.0 VDD = 5V 3.8 5.0 VDD = 3V 3.8 5.0 VDD = 1.8V 4.7 6.0 VDD = 5V 3.3 4.5 VDD = 3V 2.8 4.0 VDD = 1.8V 2.4 3.5 0.05 0.25 (Note 9) µA µA µA TIMING CHARACTERISTICS (VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 16.7 MHz TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V ) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 15 ns DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 24 ns SCLK Pulse-Width Low tCL 24 ns CS Pulse-Width High tCSW 100 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 20 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 20 ns _______________________________________________________________________________________ 5 MAX5532–MAX5535 ELECTRICAL CHARACTERISTICS (continued) MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs TIMING CHARACTERISTICS (VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 MHz TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V ) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 24 ns DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 40 ns ns SCLK Pulse-Width Low tCL 40 CS Pulse-Width High tCSW 150 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 30 ns Note 1: Linearity is tested within codes 96 to 4080. Note 2: Offset is tested at code 96. Note 3: Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_. Note 4: Guaranteed by design. Not production tested. Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5532/MAX5534) or VREF = 3.9V (MAX5533/MAX5535). 6 _______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs SUPPLY CURRENT vs. TEMPERATURE (MAX5532/MAX5534) 4.5 3.5 3.0 2.5 2.0 1.5 3.5 3.0 2.5 2.0 8 1.5 7 6 5 4 3 1.0 1.0 2 0.5 0.5 1 0 0 0 -40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -15 10 35 60 85 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE (MAX5533/MAX5535) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5532/MAX5534) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5533/MAX5535) 7 6 5 4 3 2 100 10 1 MAX5532 toc06 1000 SHUTDOWN SUPPLY CURRENT (nA) 8 1000 MAX5532 toc05 9 SHUTDOWN SUPPLY CURRENT (nA) MAX5532 toc04 10 SUPPLY CURRENT (µA) 9 SUPPLY CURRENT (µA) 4.0 SUPPLY CURRENT (µA) 4.0 10 MAX5532 toc02 4.5 SUPPLY CURRENT (µA) 5.0 MAX5532 toc01 5.0 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5533/MAX5535) MAX5532 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5532/MAX5534) 100 10 1 1 0.1 -40 -15 10 35 60 0.1 -40 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) STANDBY SUPPLY CURRENT vs. TEMPERATURE (MAX5533/MAX5535) SUPPLY CURRENT vs. CLOCK FREQUENCY SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE 4.0 SUPPLY CURRENT (µA) VREF = 3.9V 3.5 VREF = 2.4V 3.0 2.5 VREF = 1.9V 2.0 CS = LOGIC LOW CODE = 0 VREF = 1.2V 1.5 5.0 VDD = 5V 100 10 VDD = 1.8V 1.0 VDD = 5V ALL DIGITAL INPUTS SHORTED TOGETHER 4.5 4.0 SUPPLY CURRENT (mA) 4.5 MAX5532 toc08 1000 MAX5532 toc07 5.0 STANDBY SUPPLY CURRENT (µA) 85 85 MAX5532 toc09 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 1 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 0.01 0.1 1 10 100 1000 10000 100000 FREQUENCY (kHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V) _______________________________________________________________________________________ 7 MAX5532–MAX5535 Typical Operating Characteristics (VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.) 1 0.15 -1 -2 DNL (LSB) 0 INL (LSB) 0 -1 -2 0.10 0.05 -3 -3 0 -4 -4 -0.05 -5 -0.10 -5 500 1000 1500 2000 2500 3000 3500 4000 4500 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 DIGITAL INPUT CODE DNL vs. INPUT CODE (VDD = VREF = 5V) DIGITAL INPUT CODE GAIN ERROR CHANGE vs. TEMPERATURE OFFSET VOLTAGE vs. TEMPERATURE 0.8 0.10 0.05 0 -0.05 VDD = 5V VREF = 3.9V 0.6 OFFSET VOLTAGE (mV) 0.15 0.4 0.2 0 -0.2 -0.4 0.5 0.4 GAIN ERROR CHANGE (LSB) 1.0 MAX5532 toc13 0.20 -0.10 -0.15 0.3 0.2 0.1 0 -0.1 -0.2 -0.8 -0.4 -1.0 -0.5 500 1000 1500 2000 2500 3000 3500 4000 4500 VDD = 5V VREF = 3.9V -0.3 -0.6 -40 -15 10 35 60 -40 85 -15 10 35 85 60 DIGITAL INPUT CODE TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL FEEDTHROUGH RESPONSE DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT SCLK 5V/div DIN 5V/div DAC OUTPUT VOLTAGE (V) CS 5V/div 0.6048 VDD = 1.8V DAC CODE = MIDSCALE VREF = 1.2V 0.6046 0.6044 0.6042 OUT 50mV/div 20µs/div 1.9440 1.9435 1.9430 MAX5532 toc18 0.6050 DAC OUTPUT VOLTAGE (V) MAX5532 toc16 ZERO SCALE MAX5532 toc17 0 500 1000 150 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE MAX5532 toc14 0 VDD = 5.0V DAC CODE = MIDSCALE VREF = 3.9V 1.9425 1.9420 1.9415 1.9410 1.9405 0.6040 -1000-800 -600 -400 -200 0 200 400 600 800 1000 DAC OUTPUT CURRENT (µA) 8 0.20 MAX5532 toc15 1 0.25 MAX5532 toc11 2 MAX5532 toc10 2 INL (LSB) DNL vs. INPUT CODE (VDD = VREF = 1.8V) INL vs. INPUT CODE (VDD = VREF = 5V) MAX5532 toc12 INL vs. INPUT CODE (VDD = VREF = 1.8V) DNL (LSB) MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs 1.9400 -10 -8 -6 -4 -2 0 2 4 6 DAC OUTPUT CURRENT (mA) _______________________________________________________________________________________ 8 10 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT DAC OUTPUT VOLTAGE (V) VDD = 5V 2 VDD = 3V VREF = VDD CODE = MIDSCALE 4.5 1 4.0 3.5 VDD = 5V 3.0 2.5 VOUT 200mV/div VDD = 3V 2.0 1.5 1.0 VDD = 1.8V 0 0.001 0.010 0.100 0.5 1 10 0 0.001 100 VDD = 1.8V 0.01 0.1 1 10 100 OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 5V, VREF = 3.9V) OUTPUT MINIMUM SERIES RESISTANCE vs. LOAD CAPACITANCE MINIMUM SERIES RESISTANCE (Ω) FOR NO OVERSHOOT 500 VDD 2V/div 400 300 200 VOUT 10mV/div 100 0 0.0001 0.001 200µs/div POWER-UP OUTPUT VOLTAGE GLITCH MAX5532 toc24 600 VOUT 500mV/div 100µs/div MAX5532 toc23 MAX5532 toc22 0.01 0.1 1 10 100 20ms/div CAPACITANCE (µF) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE VOUT AC-COUPLED 5mV/div MAX5532 toc26 3.940 VDD = 5V 3.935 3.930 3.925 3.920 3.915 3.910 3.905 3.900 100µs/div 1.220 VDD = 1.8V REFERENCE OUTPUT VOLTAGE (V) MAX5532 toc25 REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT MAX5532 toc27 MAJOR CARRY OUTPUT VOLTAGE GLITCH (CODE 7FFh TO 800h) (VDD = 5V, VREF = 3.9V) REFERENCE OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4 MAX5532 toc20 VREF = VDD CODE = MIDSCALE MAX5532 toc21 5.0 MAX5532 toc19 5 3 OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 1.8V, VREF = 1.2V) DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT 1.219 1.218 1.217 1.216 1.215 1.214 -40 -15 10 25 TEMPERATURE (°C) 60 85 -500 1500 3500 5500 7500 REFERENCE OUTPUT CURRENT (µA) _______________________________________________________________________________________ 9 MAX5532–MAX5535 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.) REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT 3.91 3.90 3.89 MAX5532 toc29 VDD = 5V REFERENCE LINE-TRANSIENT RESPONSE (VREF = 1.2V) MAX5532 toc30 1.21750 NO LOAD 1.21748 REFERENCE OUTPUT VOLTAGE (V) MAX5532 toc28 3.92 REFERENCE OUTPUT VOLTAGE (V) MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs 1.21746 2.8V VDD 1.21744 1.21742 1.8V 1.21740 VREF 500mV/div 1.21738 1.21736 1.21734 1.21732 1.21730 3.88 -500 2000 4500 7000 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 9500 12,000 14,500 100µs/div SUPPLY VOLTAGE (V) REFERENCE OUTPUT CURRENT (µA) REFERENCE LOAD TRANSIENT (VDD = 1.8V) REFERENCE LINE-TRANSIENT RESPONSE (VREF = 3.9V) MAX5532 toc32 MAX5532 toc31 5.5V REFOUT SOURCE CURRENT 0.5mA/div VDD 4.5V VREF 500mV/div VREF 500mV/div 3.9V 200µs/div 100µs/div REFERENCE LOAD TRANSIENT (VDD = 5V) REFERENCE LOAD TRANSIENT (VDD = 1.8V) MAX5532 toc33 MAX5532 toc34 REFOUT SOURCE CURRENT 0.5mA/div REFOUT SINK CURRENT 50µA/div VREF 500mV/div 3.9V VREF 500mV/div 200µs/div 200µs/div 10 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs REFERENCE LOAD TRANSIENT (VDD = 5V) REFERENCE PSRR vs. FREQUENCY MAX5532 toc35 VREF 500mV/div 3.9V MAX5532 toc36 REFOUT SINK CURRENT 100µA/div POWER-SUPPLY REJECTION RATIO (dB) 80 VDD = 1.8V 70 60 50 40 30 20 10 0 0.01 200µs/div 0.1 1 10 100 1000 FREQUENCY (kHz) REFERENCE PSRR vs. FREQUENCY REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V) MAX5532 toc38 MAX5532 toc37 POWER-SUPPLY REJECTION RATIO (dB) 80 VDD = 5V 70 60 50 40 100µV/div 30 20 10 0 0.01 0.1 1 10 100 1000 1s/div FREQUENCY (kHz) REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V) DAC-TO-DAC CROSSTALK MAX5532 toc40 MAX5532 toc39 OUTA 1V/div 100µV/div OUTB AC-COUPLED 10mV/div OUTB AT FULL SCALE 400µs/div 1s/div ______________________________________________________________________________________ 11 MAX5532–MAX5535 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5532/MAX5534), VREF = 3.9V (MAX5533/MAX5535), TA = +25°C, unless otherwise noted.) MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs Pin Description PIN NAME FUNCTION MAX5532 MAX5533 MAX5534 MAX5535 1 1 1 1 CS 2 2 2 2 SCLK Serial-Interface Clock Input 3 3 3 3 DIN Serial-Interface Data Input Active-Low Digital Chip-Select Input 4 — 4 — REFIN — 4 — 4 REFOUT — — 5, 11 5, 11 N.C. — — 6 6 FBB 5 5 7 7 OUTB 6 6 8 8 VDD Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1µF capacitor. 7 7 9 9 GND Ground 8 8 10 10 OUTA — — 12 12 FBA — — EP EP Exposed Paddle Reference Input Reference Output No Connection. Leave N.C. inputs unconnected (floating) or connected to GND. Channel B Feedback Input Channel B Analog Voltage Output Channel A Analog Voltage Output Channel A Feedback Input Exposed Paddle. Connect EP to GND. Functional Diagrams VDD POWERDOWN CONTROL MAX5532 DAC REGISTER INPUT REGISTER SCLK DIN CS REFIN 12-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA DAC REGISTER INPUT REGISTER 12-BIT DAC OUTB GND 12 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs VDD POWERDOWN CONTROL 2-BIT PROGRAMMABLE REFERENCE REF BUF REFOUT MAX5533 INPUT REGISTER SCLK DIN CS DAC REGISTER 12-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA DAC REGISTER INPUT REGISTER 12-BIT DAC OUTB GND VDD POWERDOWN CONTROL MAX5534 DAC REGISTER INPUT REGISTER SCLK DIN CS REFIN 12-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA FBA DAC REGISTER INPUT REGISTER 12-BIT DAC OUTB FBB GND ______________________________________________________________________________________ 13 MAX5532–MAX5535 Functional Diagrams (continued) Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5532–MAX5535 Functional Diagrams (continued) VDD POWERDOWN CONTROL 2-BIT PROGRAMMABLE REFERENCE REF BUF REFOUT MAX5535 INPUT REGISTER SCLK DIN CS DAC REGISTER 12-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA FBA DAC REGISTER INPUT REGISTER 12-BIT DAC OUTB FBB GND Detailed Description The MAX5532–MAX5535 dual, 12-bit, ultra-low-power, voltage-output DACs offer Rail-to-Rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 5µA (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18µA (max). The MAX5533/MAX5535 include an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When VDD is applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5532/ MAX5533 output buffers are configured in unity gain and come in µMAX packages. The MAX5534/MAX5535 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output-amplifier inverting input is available). The MAX5534/MAX5535 come in 4mm x 4mm thin QFN packages. Digital Interface The MAX5532–MAX5535 use a 3-wire serial interface that is compatible with SPI/QSPI/MICROWIRE protocols (Figures 1 and 2). The MAX5532–MAX5535 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. The 16 bits consist of 4 control bits (C3–C0) and 12 data bits (D11–D0) (Table 1). Following the control bits, the data loads MSB first, D11–D0. The control bits C3–C0 control the MAX5532–MAX5535, as outlined in Table 2. Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output. The double-buffered register configuration allows any of the following: • Loading the input registers without updating the DAC registers • Updating the DAC registers from the input registers • Updating all the input and DAC registers simultaneously 14 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs CONTROL DATA BITS MSB C3 LSB C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tCH SCLK tCL tDS C3 DIN tCS0 C2 C1 D0 tDH tCSH tCSS CS tCSW tCS1 Figure 1. Timing Diagram SCLK DIN 1 C3 2 C2 3 C1 CONTROL BITS 4 C0 5 D11 6 D10 7 D9 8 D8 9 D7 10 D6 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 DATA BITS COMMAND EXECUTED CS Figure 2. Register Loading Diagram ______________________________________________________________________________________ 15 MAX5532–MAX5535 Table 1. Serial Write Data Format MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs Table 2. Serial-Interface Programming Commands CONTROL BITS INPUT DATA C3 C2 C1 C0 D11–D0 0 0 0 0 XXXXXXXXXXXX FUNCTION No operation; command is ignored. 0 0 0 1 12-bit data Load input register A from shift register; DAC registers unchanged; DAC outputs unchanged. 0 0 1 0 12–bit data Load input register B from shift register; DAC registers unchanged; DAC outputs unchanged. 0 0 1 1 — Command reserved. Do not use. 0 1 0 0 — Command reserved. Do not use. 0 1 0 1 — Command reserved. Do not use. 0 1 1 0 — Command reserved. Do not use. 0 1 1 1 — Command reserved. Do not use. 1 0 0 0 12-bit data Load DAC registers A and B from respective input registers; DAC outputs A and B updated; MAX5533/MAX5535 enter normal operation if in standby or shutdown; MAX5532/MAX5534 enter normal operation if in shutdown. 12-bit data Load input register A and DAC register A from shift register; DAC output A updated; Load DAC register B from input register B; DAC output B updated; MAX5533/MAX5535 enter normal operation if in standby or shutdown; MAX5532/MAX5534 enter normal operation if in shutdown. Load input register B and DAC register B from shift register; DAC output B updated; Load DAC register A from input register A; DAC output A updated; MAX5533/MAX5535 enter normal operation if in standby or shutdown; MAX5532/MAX5534 enter normal operation if in shutdown. 1 0 0 1 1 0 1 0 12-bit data 1 0 1 1 — 1 1 0 0 D11, D10, XXXXXXXXXX MAX5533/MAX5535 enter standby*, MAX5532/MAX5534 enter shutdown. For the MAX5533/MAX5535, D11 and D10 configure the internal reference voltage (Table 3). 1 1 0 1 D11, D10, XXXXXXXXXX MAX5532–MAX5535 enter normal operation; DAC outputs reflect existing contents of DAC registers. For the MAX5533/MAX5535, D11 and D10 configure the internal reference voltage (Table 3). 1 1 1 0 D11, D10, XXXXXXXXXX MAX5532–MAX5535 enter shutdown; DAC outputs set to high impedance. For the MAX5533/MAX5535, D11 and D10 configure the internal reference voltage (Table 3). 1 1 1 1 12-bit data Command reserved. Do not use. Load input registers A and B and DAC registers A and B from shift register; DAC outputs A and B updated; MAX5533/MAX5535 enter normal operation if in standby or shutdown; MAX5532/MAX5534 enter normal operation if in shutdown. X = Don’t care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown. 16 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs Shutdown Mode The MAX5532–MAX5535 feature a software-programmable shutdown mode that reduces the supply current and the reference input current to 0.18µA (max). Writing an input control word with control bits C[3:0] = 1110 (Table 2) places the device in shutdown mode. In shutdown, the MAX5532/MAX5534 reference input and DAC output buffers go high impedance. Placing the MAX5533/MAX5535 into shutdown turns off the internal reference and the DAC output buffers go high impedance. The serial interface still remains active for all devices. Table 2 shows several commands that bring the MAX5532–MAX5535 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid. Note: For the MAX5533/MAX5535, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. Standby Mode (MAX5533/MAX5535 Only) The MAX5533/MAX5535 feature a software-programmable standby mode that reduces the typical supply current to 3µA (max). Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. For the MAX5533/MAX5535, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation followed immediately by the command to go into standby. Table 2 shows several commands that bring the MAX5533/MAX5535 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid. Reference Input The MAX5532/MAX5534 accept a reference with a voltage range extending from 0 to VDD. The output voltage (VOUT) is represented by a digitally programmable voltage source as: VOUT = (VREF x N / 4096) x gain where N is the numeric value of the DAC’s binary input code (0 to 4095), VREF is the reference voltage, gain is the externally set voltage gain for the MAX5534, and gain is one for the MAX5532. In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5GΩ (typ). Reference Output The MAX5533/MAX5535 internal voltage reference is software configurable to one of four voltages. Upon powerup, the default reference voltage is 1.214V. Configure the reference voltage using D10 and D11 data bits (Table 3) when the control bits are as follows C[3:0] = 1100, 1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation. Table 3. Reference Output Voltage Programming D11 D10 REFERENCE VOLTAGE (V) 0 0 1.214 0 1 1.940 1 0 2.425 1 1 3.885 ______________________________________________________________________________________ 17 MAX5532–MAX5535 Power Modes The MAX5532–MAX5535 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5533/MAX5535. The MAX5533/MAX5535 also offer a standby mode in which all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. It also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation. MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs Applications Information 1-Cell and 2-Cell Circuits See Figure 3 for an illustration of how to power the MAX5532–MAX5535 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices make the MAX5532–MAX5535 ideal for battery-powered applications. Programmable Current Source See the circuit in Figure 4 for an illustration of how to configure the MAX5534/MAX5535 as a programmable current source for driving an LED. The MAX5534/ MAX5535 drive a standard NPN transistor to program the current source. The current source (ILED) is defined in the equation in Figure 4. VDD 536kΩ 1.8V ≤ VALKALINE ≤ 3.3V 2.2V ≤ VLITHIUM ≤ 3.3V +1.25V REFIN DAC VOUT 0.1µF 0.01µF MAX6006 (1µA, 1.25V SHUNT REFERENCE) VOUT (0.30mV / LSB) V × NDAC VOUT = REFIN 4096 1/2 MAX5534 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. GND Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell V+ LED REFIN DAC VOUT ILED REFIN DAC VOUT 1/2 MAX5534 V × NDAC ILED = REFIN 4096 × R 2N3904 1/2 MAX5534 R FB FB R NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 4. Programmable Current Source Driving an LED 18 VOUT VOUT = VBIAS + (IT × R) TRANSDUCER VBIAS IT V × NDAC VBIAS = REFIN 4096 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs See the circuit in Figure 5 for an illustration of how to configure the MAX5534/MAX5535 to bias a current-output transducer. In Figure 5, the output voltage of the MAX5534/MAX5535 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R. Unipolar Output Figure 6 shows the MAX5534 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes. Bipolar Output The MAX5534 output can be configured for bipolar operation as shown in Figure 7. The output voltage is given by the following equation: VOUT_ = VREFIN x [(NA - 2048) / 2048] where NA represents the decimal value of the DAC’s binary input code. Table 5 shows the digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 7. Configurable Output Gain The MAX5534/MAX5535 have force-sense outputs, which provide a connection directly to the inverting terminal of the output op-amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5534/MAX5535 is specified in a unitygain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components. An example of a custom fixed gain using the MAX5534/ MAX5535 force-sense output is shown in Figure 8. In this example, R1 and R2 set the gain for VOUTA. REFIN VOUTA = [(VREFIN x NA) / 4096] x [1 + (R2 / R1)] where NA represents the numeric value of the DAC input code. Self-Biased Two-Electrode Potentiostat Application See the circuit in Figure 10 for an illustration of how to use the MAX5535 to bias a two-electrode potentiostat on the input of an ADC. Power Supply and Bypassing Considerations Bypass the power supply with a 0.1µF capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed pad to ground. Layout Considerations Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Table 4. Unipolar Code Table (Gain = +1) DAC CONTENTS MSB LSB ANALOG OUTPUT 1111 1111 1111 +VREF (4095/4096) 1000 0000 0001 +VREF (2049/4096) 1000 0000 0000 +VREF (2048/4096) = +VREF / 2 0111 1111 1111 +VREF (2047/4096) 0000 0000 0001 +VREF (1/4096) 0000 0000 0000 0V Table 5. Bipolar Code Table (Gain = +1) DAC OUT_ DAC CONTENTS MSB MAX5534 FB_ VREFIN × NA VOUT = 4096 NA IS THE DAC INPUT CODE (0 TO 4095 DECIMAL). Figure 6. Unipolar Output Circuit LSB ANALOG OUTPUT 1111 1111 1111 +VREF (2047/2048) 1000 0000 0001 +VREF (1/2048) 1000 0000 0000 0V 0111 1111 1111 -VREF (1/2048) 0000 0000 0001 -VREF (2047/2048) 0000 0000 0000 -VREF (2048/2048) = -VREF ______________________________________________________________________________________ 19 MAX5532–MAX5535 Voltage Biasing a Current-Output Transducer MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs V 255 - NPOT × NDAC VOUT = REFIN 1+ 4096 255 ( 10kΩ ) NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE. 10kΩ 1.8V ≤ VDD ≤ 5.5V V+ REFIN DAC VOUT VOUT VOUT DAC OUT_ REFIN H CS1 1/2 MAX5534 MAX5401 SOT-POT 100kΩ V- 1/2 MAX5534 FB FB_ W SCLK 5PPM/°C RATIOMETRIC TEMPCO DIN CS2 L Figure 9. Software-Configurable Output Gain Figure 7. Bipolar Output Circuit REFIN DAC REF VOUTA VOUT1 R2 VOUT1 = FBA VREFIN × NDACA R2 1+ 4096 R1 ( ) DAC DAC TO ADC WE 1/2 MAX5535 VOUT2 SENSOR VREFIN × NDACB VOUT2 = 4096 FBB RF FB_ R1 VOUTB TO ADC IF NDACA IS THE NUMERIC VALUE OF THE DAC A INPUT CODE. MAX5534 OUT_ CE NDACB IS THE NUMERIC VALUE OF THE DAC B INPUT CODE. BAND GAP REFOUT TO ADC CL Figure 8. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference Figure 10. Self-Biased Two-Electrode Potentiostat Application 20 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs REF OUTA DAC TO ADC IF TOP VIEW RF FBA WE MAX5535 CS 1 SCLK 2 DIN 3 FBA N.C. OUTA 12 11 10 9 GND 8 VDD 7 OUTB SENSOR REF CE DAC OUTB 4 FBB BAND GAP MAX5534 MAX5535 REFIN(MAX5534) REFOUT(MAX5535) REFOUT 5 6 N.C. FBB TO ADC CL THIN QFN Figure 11. Driven Two-Electrode Potentiostat Application Chip Information TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS ______________________________________________________________________________________ 21 MAX5532–MAX5535 Pin Configurations (continued) Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 22 ______________________________________________________________________________________ B 1 2 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 B 2 ______________________________________________________________________________________ 2 23 MAX5532–MAX5535 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 4X S 8 E 0.50–0.1 8 INCHES DIM A A1 A2 b H c D e E H 0.6–0.1 1 L 1 α 0.6–0.1 S BOTTOM VIEW D MIN 0.002 0.030 MAX 0.043 0.006 0.037 0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC 8LUMAXD.EPS MAX5532–MAX5535 Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95 0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 5.03 4.78 0.41 0.66 0 6 0.5250 BSC TOP VIEW A1 A2 A α c e b L SIDE VIEW FRONT VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 8L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0036 REV. J 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.