AS1520, AS1521 D a ta S he e t 1 0 - B i t , S i n g l e - S u p p l y, L o w - P o w e r, 4 0 0 / 3 0 0 k s ps , 8-Channel A/D Converters 1 General Description 2 Key Features The AS1520/AS1521 are low-power, 8/4-channel, 400/ 300ksps, 10-bit analog-to-digital (A/D) converters specifically designed to operate with single-supply devices. Superior AC characteristics, very low power consumption, and highly-reliable packaging make these ultrasmall devices perfect for battery-powered remote-sensor and data-acquisition devices. The successive-approximation register (SAR), highspeed sampling, high-bandwidth track/hold circuitry, and multi-mode operation combine to make these devices highly-flexible and configurable. Both devices require low supply current (2.8mA @ 400ksps, AS1520; 2.2mA @ 300ksps, AS1521) and feature a reduced-power mode and a power-down mode to lower power consumption at slower throughput rates. The devices operate from a single supply (+4.5 to +5.5V, AS1520; +2.7 to +3.6V, AS1521). Both devices contain an internal 2.5V reference, an integrated reference buffer, and feature support for an external reference (1V to VDD). Data accesses are made via the high-speed, 4-wire, SPI, QSPI-, and Microwire-compatible serial interface. The devices are available in a 20-pin TSSOP package. 17 Input Shift Register AS1520/ AS1521 Analog Input Software-Configurable Analog Input Types: - 8-Channel Single-Ended - 8-Channel Pseudo Differential Referenced to COM - 4-Channel Pseudo Differential - 4-Channel Fully Differential ! Software-Configurable Input Range ! Internal +2.5V Reference ! Low-Current Operation: - 2.8mA @ 400ksps (AS1520) - 2.2mA @ 300ksps (AS1521) - 0.4mA in Reduced-Power Mode - 0.5µA in Full Power-Down Mode ! SPI/QSPI/Microwire/TMS320-Compatible ! 20-pin TSSOP Package 3 Applications DOUT 15 CH0 1 20 VDD1 CH1 2 19 VDD2 10 CH2 3 18 SCLK VDD3 CH3 4 17 CSN Track/ Hold IN 19 VDD2 OUT REF 20 COM REFADJ 11 ! CH4 5 10-Bit SAR 1:8 12 Sampling Rate: - 400ksps (AS1520) - 300ksps (AS1521) SSTRB Control Logic CH0:CH7 9 ! 14 Output Shift Register CSN 18 DIN Single-Supply Operation: - +4.5 to +5.5V (AS1520) - +2.7 to +3.6V (AS1521) The devices are ideal for remote sensors, data-acquisition and data-logging devices, pen-digitizers, process control, or any other space-limited A/D application with low power-consumption requirements. Figure 1. Block Diagram and Pin Assignments SCLK 16 ! +1.2V REF 17kΩ VDD1 Av ≈ 2.05 +2.50V REF www.austriamicrosystems.com CH5 6 AS1520/ AS1521 16 DIN 15 SSTRB CH6 7 14 DOUT CH7 8 13 GND COM 9 12 REFADJ VDD3 10 11 REF 13 GND Revision 1.00 1 - 29 AS1520/AS1521 Data Sheet Contents 1 General Description ................................................................................................................................ 1 2 Key Features .......................................................................................................................................... 1 3 Applications ............................................................................................................................................ 1 4 Pinout ..................................................................................................................................................... 3 Pin Assignments ..................................................................................................................................................... 3 Pin Descriptions ..................................................................................................................................................... 3 5 Absolute Maximum Ratings .................................................................................................................... 4 6 Electrical Characteristics ........................................................................................................................ 5 AS1520 Electrical Characteristics .......................................................................................................................... 5 AS1521 Electrical Characteristics .......................................................................................................................... 7 Timing Characteristics ............................................................................................................................................ 9 7 Typical Operating Characteristics ......................................................................................................... 11 8 Detailed Description ............................................................................................................................. 14 Analog Input ......................................................................................................................................................... 14 Input Protection ............................................................................................................................................. 14 Track/Hold ............................................................................................................................................................ 14 Control Register ................................................................................................................................................... 15 Analog Input Configuration ................................................................................................................................... 15 Channel Selection ................................................................................................................................................ 16 Single-Ended Input ........................................................................................................................................ 16 Differential Input ............................................................................................................................................ 16 Starting a Conversion ........................................................................................................................................... 17 Transfer Functions ................................................................................................................................................ 18 Power Modes ....................................................................................................................................................... 19 Reduced Power Mode ................................................................................................................................... 20 Full Power-Down Mode ................................................................................................................................. 20 Reference ............................................................................................................................................................. 21 Internal Reference ......................................................................................................................................... 21 External Reference ....................................................................................................................................... 22 9 Application Information ......................................................................................................................... 23 Initialization ........................................................................................................................................................... 23 Serial Interface ..................................................................................................................................................... 23 Serial Interface Configuration ........................................................................................................................ 23 QSPI Interface ............................................................................................................................................... 24 Quick Evaluation Circuit ....................................................................................................................................... 25 Layout Considerations .......................................................................................................................................... 26 10 Package Drawings and Markings ....................................................................................................... 27 11 Ordering Information ........................................................................................................................... 28 www.austriamicrosystems.com Revision 1.00 2 - 29 AS1520/AS1521 Data Sheet - P i n o u t 4 Pinout Pin Assignments Figure 2. Pin Assignments (Top View) CH0 1 20 VDD1 CH1 2 19 VDD2 CH2 3 18 SCLK CH3 4 17 CSN CH4 5 CH5 6 AS1520/ AS1521 16 DIN 15 SSTRB CH6 7 14 DOUT CH7 8 13 GND COM 9 12 REFADJ VDD3 10 11 REF Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Description 1:8 CH0:CH7 9 COM Common Analog Inputs. Tie this pin to ground in single-ended mode. 10 VDD3 Positive Supply Voltage 11 REF Reference-Buffer Output/A/DC Reference Input. This pin serves as the reference voltage for analog-to-digital conversions. In internal reference mode, the reference buffer provides a +2.50V nominal output, externally adjustable at pin REFADJ. In external reference mode, disable the internal buffer by pulling pin REFADJ to VDD1. 12 REFADJ Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie this pin to VDD1. 13 GND 14 DOUT Serial Data Output. Data is clocked out at the rising edge of pin SCLK. DOUT is high impedance when CSN is high. 15 SSTRB Serial Strobe Output. SSTRB pulses high for one clock period before the MSB is clocked out. SSTRB is high impedance when CSN is high. 16 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK. 17 CSN Active-Low Chip Select. Data will not be clocked into pin DIN unless CSN is low. When CSN is high, pins DOUT and SSTRB are high impedance. 18 SCLK Serial Clock Input. This pin clocks data into and out of the serial interface, and is used to set the conversion speed. Note: The duty cycle must be between 40 and 60%. 19 VDD2 Positive Supply Voltage 20 VDD1 Positive Supply Voltage Analog Sampling Inputs. These eight pins serve as analog sampling inputs. Analog and Digital Ground www.austriamicrosystems.com Revision 1.00 3 - 29 AS1520/AS1521 Data Sheet - A b s o l u t e Maximum Ratings 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units VDD1, VDD2, VDD3 to GND -0.3 +7 V VDD1 to VDD2 to VDD3 -0.3 +0.3 V CH0:CH7, COM to GND -0.3 VDD1 + +0.3 V REF, REFADJ to GND -0.3 VDD1 + +0.3 V DIN, SCLK, CSN, to GND -0.3 VDD2 + +0.3 V DOUT, SSTRB to GND -0.3 VDD2 + +0.3 V DOUT, SSTRB Sink Current 25 mA Continuous Power Dissipation (TAMB = +70ºC) 559 mW Operating Temperature Range -40 +85 ºC Storage Temperature Range -60 +150 ºC Package Body Temperature www.austriamicrosystems.com +260 ºC Revision 1.00 Comments Derate 7.0mW/ºC above +70ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). 4 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics 6 Electrical Characteristics AS1520 Electrical Characteristics VDD1 = VDD2 = VDD3 = +4.5 to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TAMB = TMIN to TMAX (unless otherwise specified). Typ values at TAMB = +25ºC. Table 3. AS1520 Electrical Characteristics Symbol Parameter DC Accuracy Conditions Resolution INL DNL Min Typ Max Units -0.5 +0.5 LSB -1 -3 +1 +3 LSB LSB 1 10 2 Relative Accuracy Differential Nonlinearity Offset Error No missing codes over temperature Bits 3 -3 +3 LSB Gain Error Gain-Error Temperature ppm/ ±1.6 Coefficient °C Channel-to-Channel ±0.2 LSB Offset Error Matching Dynamic Specifications: 100kHz sinewave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bit RANGE (page 15) = 0, pseudo-differential input mode Signal-to-Noise plus SINAD 60 dB Distortion Ratio THD Total Harmonic Distortion Up to the 5th harmonic 70 dB Spurious-Free SFDR 70 dB Dynamic Range IMD Intermodulation Distortion fIN1 = 99kHz, fIN2 = 102kHz 76 dB Channel-to-Channel fIN = 200kHz, VIN = 2.5Vp-p -85 dB 4 Crosstalk Full-Power Bandwidth -3dB point 6 MHz Full-Linear Bandwidth SINAD > 68dB 450 kHz Conversion Rate 5 tCONV Conversion Time tACQ Track/Hold Acquisition Time tAD Aperture Delay tAJ Aperture Jitter fSCLK Serial Clock Frequency Duty Cycle Analog Inputs: CH0:CH7, COM VCHx - Input Voltage Range: SingleEnded, Pseudo-Differential, VCHy 6 (COM) and Differential Multiplexer Leakage Current Input Capacitance Internal Reference VREF REF Output Voltage REF Short-Circuit Current REF Output Temperature TCVREF Coefficient Load Regulation CBYPREF 7 2.5 7 <50 0.5 40 Bit RANGE (page 15) = 1 Bit RANGE (page 15) = 0 On/off leakage current, VCHx = 0 or VDD1 TAMB = +25ºC 6.4 60 0 VREF -VREF +VREF /2 /2 -1 ±0.001 +1 18 2.48 2.50 30 2.52 ±25 0 to 1mA output load Capacitive Bypass at REF www.austriamicrosystems.com µs 390 1.2 4.7 Revision 1.00 4.0 10 ns ns ps MHz % V µA pF V mA ppm/ °C mV/ mA µF 5 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics Table 3. AS1520 Electrical Characteristics (Continued) Symbol Parameter Conditions Capacitive Bypass at CBYPREF ADJ REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments, from 1.22V REFADJ Buffer Disable To power down the internal reference Threshold Buffer Voltage Gain External Reference: Reference buffer disabled, reference applied to pin REF REF Input Voltage Range Min 0.01 Max Units 10 µF 1.22 ±100 V mV VDD1 1 1.4 2.045 8 REF Input Current Typ V/V VDD1 + 50mV 1.0 VREF = 2.50V, fSCLK = 6.4MHz VREF = 2.50V, fSCLK = 0 Power-Down, fSCLK = 0 V 200 V 350 320 5 µA Digital Inputs: DIN, SCLK, CSN VINH Input High Voltage VINL Input Low Voltage VHYST Input Hysteresis IIN Input Leakage CIN Input Capacitance Digital Outputs: DOUT, SSTRB VOL Output Voltage Low VOH Output Voltage High IL Tri-State Leakage Current COUT Tri-State Output Capacitance Power Supply VDD1, 9 VDD2, Positive Supply Voltage VDD3 IVDD1, IVDD2, IVDD3 Supply Current 0.7 x VDD -1 V +1 V µA pF 5 ISINK = 5mA ISOURCE = 1mA CSN = VDD2 CSN = VDD2 0.4 4 -10 +10 5 4.5 VDD1 = VDD2 = VDD3 = 5.5V Normal Operation with 10 External Reference Normal Operation with 10 Internal Reference 11 Power-Supply Rejection 0.3 x VDD 0.2 VIN = 0 or VDD2 Reduced-Power Mode Full Power-Down Mode PSR V VDD1 = VDD2 = VDD3 = 5V ±10% -2 V V µA pF 5.5 V 2.8 3.3 3.3 3.8 0.4 0.8 0.5 2 µA ±0.1 +2 mV mA 1. Tested at VDD1 = VDD2 = VDD3 = +5V, COM = GND, bit RANGE (page 15) = 1, single-ended input mode. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. Offset nulled. 4. Ground on channel; sinewave applied to all off channels. 5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1. 7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA is a result of production test limitations. 8. AS1520/AS1521 performance is limited by the device noise floor, typically 300µVp-p. www.austriamicrosystems.com Revision 1.00 6 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics 9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) = VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 11. For guaranteed specifications beyond the limits, contact austriamicrosystems, AG. 10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz @ GND to VDD2. 11. SCLK = DIN = GND, CSN = VDD2. AS1521 Electrical Characteristics VDD1 = VDD2 = VDD3 = +2.7 to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TAMB = TMIN to TMAX (unless otherwise specified). Typ values at TAMB = +25ºC. Table 4. AS1521 Electrical Characteristics Symbol Parameter DC Accuracy Conditions Resolution INL DNL Min Typ Max Units -0.5 +0.5 LSB -1 -3 +1 +3 LSB LSB 1 10 2 Relative Accuracy Differential Nonlinearity Offset Error No missing codes over temperature Bits 3 -3 +3 Gain Error Gain-Error Temperature ±1.6 Coefficient Channel-to-Channel Offset ±0.2 Error Matching Dynamic Specifications: 75kHz sinewave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bit RANGE (page 15) = 0, pseudo-differential input mode Signal-to-Noise plus SINAD 60 Distortion Ratio THD Total Harmonic Distortion Up to the 5th harmonic 70 Spurious-Free Dynamic SFDR 70 Range 76 IMD Intermodulation Distortion fIN1 = 73kHz, fIN2 = 77kHz Channel-to-Channel fIN = 150kHz, VIN = 2.5Vp-p 80 4 Crosstalk Full-Power Bandwidth -3dB point 6 Full-Linear Bandwidth SINAD > 68dB 350 Conversion Rate tCONV 5 Conversion Time tACQ Track/Hold Acquisition Time tAD Aperture Delay tAJ Aperture Jitter Serial Clock Frequency fSCLK Duty Cycle Analog Inputs: CH0:CH7, COM VCHx - Input Voltage Range: SingleEnded, Pseudo-Differential, VCHy 6 (COM) and Differential Multiplexer Leakage Current Input Capacitance Internal Reference REF Output Voltage VREF REF Short-Circuit Current www.austriamicrosystems.com Normal operation 3.3 520 7 <50 Bit RANGE (page 15) = 1 Bit RANGE (page 15) = 0 On/off leakage current, VCHx = 0 or AVDD TAMB = +25°C Revision 1.00 0.5 40 4.8 60 0 VREF +VREF -VREF /2 /2 -1 ±0.001 +1 18 2.48 ppm/ °C LSB dB dB dB dB dB MHz kHz µs Normal operation Normal operation LSB 2.50 30 2.52 ns ns ps MHz % V µA pF V mA 7 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics Table 4. AS1521 Electrical Characteristics (Continued) Symbol CBYPREF 4.7 10 Units ppm/ °C mV/ mA µF CBYPREF 0.01 10 µF TCVREF Parameter REF Output Temperature Coefficient Load Regulation Conditions Typ Max ±25 7 0 to 0.75mA output load Capacitive Bypass at REF Capacitive Bypass ADJ at REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments, from 1.22V REFADJ Buffer To power down the internal reference Disable Threshold Buffer Voltage Gain External Reference: Reference buffer disabled, reference applied to REF REF Input Voltage Range Min 8 REF Input Current 0.6 2.0 1.22 ±100 V mV VDD1 -1 1.4 2.045 1.0 VREF = 2.50V, fSCLK= 4.8MHz VREF = 2.50V, fSCLK = 0 In power-down, fSCLK = 0 200 V V/V VDD1 + 50mV 350 320 5 V µA Digital Inputs: DIN, SCLK, CSN VINH Input High Voltage VINL Input Low Voltage VHYST Input Hysteresis Input Leakage IIN Input Capacitance CIN Digital Outputs: DOUT, SSTRB Output Voltage Low VOL VOH Output Voltage High IL Tri-State Leakage Current Tri-State Output COUT Capacitance Power Supply VDD1, 9 VDD2, Positive Supply Voltage VDD3 IVDD1, IVDD2, IVDD3 PSR Supply Current Power-Supply Rejection www.austriamicrosystems.com 0.7 x VDD V 0.3 x VDD V +1 V µA pF 0.45 V 0.8 VIN = 0 or VDD2 -1 5 ISINK = 5mA ISOURCE = 0.5mA CSN = VDD2 VDD2 0.5V -10 CSN = VDD2 V +10 5 2.7 VDD1 = VDD2 = VDD3 = 5.5V Normal Operation with External 10 Reference Normal Operation with Internal 10 Reference Reduced-Power 11 Mode Full Power-Down 11 Mode VDD1 = VDD2 = VDD3 = 2.7 to 3.6V, Mid-Scale Input Revision 1.00 µA pF 3.6 2.2 2.7 2.7 3.2 V mA -2 0.4 0.8 0.5 2 µA ±0.1 +2 mV 8 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics 1. Tested at VDD1 = VDD2 = VDD3 = +3V; COM = GND; bit RANGE (page 15) = 1, single-ended input mode. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. 3. Offset nulled. 4. Ground on channel; sinewave applied to all off channels. 5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. 6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1. 7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result of production test limitations. 8. AS1520/AS1521 performance is limited by the device noise floor, typically 300µVp-p. 9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) = VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 11. For guaranteed specifications beyond the limits, contact austriamicrosystems, AG. 10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 4.8MHz @ GND to VDD2. 11. SCLK = DIN = GND, CSN = VDD2. Timing Characteristics Table 5. AS1520 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +4.5 to +5.5V; TAMB = TMIN to TMAX (unless otherwise specified). Symbol Parameter tCP SCLK Period Conditions Min Typ Max tCH SCLK Pulse Width High 62 ns tCL SCLK Pulse Width Low 62 ns tDS DIN to SCLK Setup 35 ns tDH DIN to SCLK Hold 0 ns 156 Units ns tCSS CSN Fall to SCLK Rise Setup 35 ns tCS0 SCLK Rise to CSN Fall Ignore 35 ns tDOH SCLK Rise to DOUT Hold CLOAD = 20pF 10 20 ns tSTH SCLK Rise to SSTRB Hold CLOAD = 20pF 10 20 ns tSTV SCLK Rise to DOUT Valid CLOAD = 20pF 80 ns tDOV SCLK Rise to SSTRB Valid CLOAD = 20pF 80 ns tDOD CSN Rise to DOUT Disable CLOAD = 20pF 10 65 ns tSTD CSN Rise to SSTRB Disable CLOAD = 20pF 10 65 ns tDOE CSN Fall to DOUT Enable CLOAD = 20pF 65 ns tSTE CSN Fall to SSTRB Enable CLOAD = 20pF 65 ns tCSW CSN Pulse Width High 100 ns Table 6. AS1521 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to TMAX (unless otherwise specified). Symbol Parameter tCP SCLK Period Conditions Min 208 Typ Max Units tCH SCLK Pulse Width High 83 ns tCL SCLK Pulse Width Low 83 ns tDS DIN to SCLK Setup 45 ns ns tDH DIN to SCLK Hold 0 ns tCSS CSN Fall to SCLK Rise Setup 45 ns tCS0 SCLK Rise to CSN Fall ignore 45 ns www.austriamicrosystems.com Revision 1.00 9 - 29 AS1520/AS1521 Data Sheet - E l e c t r i c a l Characteristics Table 6. AS1521 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to TMAX (unless otherwise specified). (Continued) Symbol Parameter Conditions Min Typ tDOH SCLK Rise to DOUT Hold CLOAD = 20pF 13 20 13 20 Max Units ns tSTH SCLK Rise to SSTRB Hold CLOAD = 20pF tDOV SCLK Rise to DOUT Valid CLOAD = 20pF 100 ns ns tSTV SCLK Rise to SSTRB Valid CLOAD = 20pF 100 ns tDOD CSN Rise to DOUT Disable CLOAD = 20pF 13 85 ns tSTD CSN Rise to SSTRB Disable CLOAD = 20pF 13 85 ns tDOE CSN Fall to DOUT Enable CLOAD = 20pF 85 ns tSTE CSN Fall to SSTRB Enable CLOAD = 20pF 85 tCSW CSN Pulse Width High 100 ns ns Figure 3. DOUT Enable-Time Load Circuits VDD2 DOUT 6kΩ CLOAD 20pF 6kΩ DGND DOUT CLOAD 20pF GND High-impedance to VOH and VOL to VOH DGND High-impedance to VOL and VOH to VOL Figure 4. DOUT Disable-Time Load Circuits VDD2 DOUT 6kΩ CLOAD 20pF 6kΩ DGND DOUT CLOAD 20pF GND VOH to high-impedance DGND VOL to high-impedance www.austriamicrosystems.com Revision 1.00 10 - 29 AS1520/AS1521 Data Sheet - Ty p i c a l Operating Characteristics 7 Typical Operating Characteristics Same conditions as stated in Electrical Characteristics on page 5. Figure 6. DNL vs. Digital Output Code 1 1 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) . INL (LSB) . Figure 5. INL vs. Digital Output Code 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 200 400 600 800 0 1000 200 Figure 7. FFT @ 10kHz; RANGE = 1, MODE = 1 600 800 1000 Figure 8. FFT @ 75kHz; RANGE = 0, MODE = 1 20 20 0 0 FSample = 312.5ksps NFFT = 16384 -20 FSample = 312.5ksps NFFT = 16384 -20 -40 FFT (dBC) . FFT (dBC) . 400 Digital Output Code Digital Output Code -60 -80 -100 -40 -60 -80 -100 -120 -120 -140 -140 -160 -160 -180 -180 0 20 40 60 0 80 100 120 140 160 20 40 60 80 100 120 140 160 Input Signal Frequency (kHz) Input Signal Frequency (kHz) Figure 9. ENOB vs. VREF; 1st Order 300kHz Low Pass Filter Figure 10. ENOB vs. Input Signal Frequency; 1st Order 1MHz Low Pass Filter 9.95 9.95 AS1521: fsig = 75kHz 9.9 ENOB (Bit) . ENOB (Bit) . 9.9 AS1520: fsig = 100kHz 9.85 9.8 9.85 9.8 9.75 9.75 1 2 3 4 5 0 Voltage (V) www.austriamicrosystems.com 100 200 300 400 Frequency (kHz) Revision 1.00 11 - 29 AS1520/AS1521 Data Sheet - Ty p i c a l Operating Characteristics Figure 11. IVDD vs. VDD (Static) Figure 12. IVDD vs. Temperature; Internal Reference 4 4 Internal Reference 3 Supply Current (mA) e Supply Current (mA) e 3.5 2.5 External Reference 2 1.5 1 0.5 0 3.75 3.5 AS1520 3.25 3 2.75 AS1521 2.5 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 -40 -15 Supply Voltage (V) 10 35 60 85 Temperature (°C) Figure 13. IVDD vs. VDD (Converting) Figure 14. IVDD vs. Temperature (Static) 3 2 Supply Current (mA) Supply Current (mA) e Normal Operation; Internal Reference 2.5 2 1.5 1 Reduced Power Mode; Internal Reference 0.5 Reduced Power Mode; External Reference 1.5 1 AS1520, Reduced Power Mode, Internal Ref. AS1521, Reduced Power Mode, Internal Ref. 0.5 AS1520, Reduced Power Mode, External Ref. AS1521, Reduced Power Mode, External Ref. 0 0 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 -40 -15 10 35 60 85 Temperature (°C) Supply Voltage (V) Figure 15. VREF vs. Temperature Reference Voltage (V) . 2.51 2.505 2.5 2.495 2.49 -40 -15 10 35 60 85 Temperature (°C) www.austriamicrosystems.com Revision 1.00 12 - 29 AS1520/AS1521 Data Sheet - Ty p i c a l Operating Characteristics Figure 16. Offset Error vs. Temperature Figure 17. Offset Error vs. VDD 2 2 Offset Error (LSB) Offset Error (LSB) . 3 . 3 1 0 -1 -2 -3 -40 1 0 -1 -2 -3 -5 30 65 2.7 3.1 Temperature (°C) 4.3 4.7 5.1 5.5 5.1 5.5 Figure 19. Gain Error vs. VDD 3 3 2 2 Gain Error (LSB) . Gain Error (LSB) . 3.9 Supply Voltage (V) Figure 18. Gain Error vs. Temperature 1 0 -1 1 0 -1 -2 -2 -3 -40 3.5 -3 -5 30 65 2.7 www.austriamicrosystems.com 3.1 3.5 3.9 4.3 4.7 Supply Voltage (V) Temperature (°C) Revision 1.00 13 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description 8 Detailed Description Analog Input The equivalent input circuit (Figure 20) shows the input architecture: track/hold circuitry, input multiplexer, input comparator, switched-capacitor DAC, and internal reference. A flexible serial interface provides easy connections to various microprocessors. Figure 20. Equivalent Input Circuit REF CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Analog Input Multiplexer CHOLD 13pF + AIN+ CSWITCH 11pF – + Sample Switch CHOLD 13pF AIN- CSWITCH 11pF – Comparator RIN – + CSWITCH includes all parasitics The input tracking circuitry has a 6MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals modulated at frequencies exceeding the AS1520/AS1521 sampling rate. Note: To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recommended Input Protection Internal protection diodes (which clamp the analog input to VDD1 and GND) allow the channel inputs to swing from (GND to 0.3V) to (VDD1 + 0.3V) without damaging the devices. However, for accurate conversions near full scale, the inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV. Note: If the analog input exceeds 50mV beyond the supply voltage, do not allow the input current to exceed 2mA. Track/Hold The track/hold stage enters tracking mode on the rising edge of SCLK which clocks in bit MODE of the 8-bit control byte (see Figure 21 on page 17). The track/hold stage enters hold mode on the falling clock edge after bit PD0 of the 8bit control byte has been shifted in. The time required for the track/hold circuit to acquire an input signal is a function of how quickly the input capacitance is charged. If the input signal source impedance is high, the acquisition time lengthens. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired. tACQ is never less than 390ns (AS1520) or 520ns (AS1521), and is calculated by: tACQ = 7(RS + RIN)18pF (EQ 1) Where:: RIN = 800Ω RS = the source impedance of the input signal. Note: Source impedances below 2kΩ do not significantly affect the AC performance of the devices. www.austriamicrosystems.com Revision 1.00 14 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Control Register The control register on the AS1520/AS1521 is a 8-bit, write-only register. Data is written to this register using the CSN, DIN and SCLK pins. The control register format is shown in Table 7 and the function of the bits are defined in Table 8. The AS1520/AS1521 operating modes are selected by sending an 8-bit data word to the internal shift register via pin DIN. After pin CSN is pulled low, the first logic 1 on pin DIN is interpreted as a start bit. A start bit is defined as one of the following: The first logic 1 bit clocked into pin DIN (with CSN low) any time the AS1520/AS1521 is idle, e.g., after VDD1 and VDD2 are applied. ! The first logic 1 bit clocked into pin DIN after bit 6 of a conversion in progress is clocked out of pin DOUT. Figure 22 on page 17 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If CSN is tied low and SCLK is continuous, guarantee a start bit by first clocking in sixteen 0s. The fastest speed at which the devices can operate is 16 clocks per conversion (with CSN held low between conversions). ! Table 7. Control Byte Format Bit 7 START (MSB) Bit 6 SEL2 Bit 5 SEL1 Bit 4 SEL0 Bit 3 RANGE Bit 2 MODE Bit 1 PD1 Bit 0 PD0 (LSB) Table 8. Bit Descriptions Bit 7 Name START 6:4 SEL2:SEL0 3 RANGE 2 MODE 1:0 PD1:PD0 Description The first logic 1 bit after CSN goes low signifies the start of a control byte. These three bits select which of the eight channels and pin COM are used for the conversion (see Table 10 and Table 11). This bit selects the analog input range of the AS1520/AS1521. 0 = The analog input range extends from -VREF/2 to +VREF/2. 1= The analog input range extends from 0V to VREF. This bit in conjunction with bit RANGE changes the analog input configuration. 0 = The voltage difference between two selectable channels is converted. This setting selects two's complement coding (see Table 10 on page 16 and Table 11 on page 16). 1 = One of the eight input channels is referenced to COM. This setting also selects binary coding. Selects the AS1520/AS1521 operating mode: PD1 PD0 Mode 0 0 Full power-down mode. 0 1 Reduced-power mode. 1 0 Reduced-power mode. 1 1 Normal operation. Analog Input Configuration Table 9. Analog Input Configuration Analog Input Configuration 8-Channel Single-Ended 1 1 Binary Comments AIN+ from 0 to VREF. COM should be tied to GND. 8-Channel Pseudo Differential referenced to COM 8-Channel Pseudo Differential referenced to COM 4-Channel Pseudo Differential 4-Channel Pseudo Differential 1 1 Binary AIN+ from COM to COM + VREF 1 0 Binary AIN+ from -VREF/2+COM to + VREF/2+COM 0 0 1 0 Two's Complement Two's Complement 4-Channel Fully Differential 0 0 Two's Complement AIN+ - AIN- from 0 to VREF AIN+ - AIN- from -VREF/2 to +VREF/2 AIN+ - AIN- from -VREF/2 to +VREF/2, fully differential input signal. www.austriamicrosystems.com Mode Range Coding Revision 1.00 15 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Channel Selection Depending on the setting of bit MODE (page 15), the internal inputs of the ADC (AIN+ and AIN-) are connected differently to the input channels (CH0:CH7 and COM). Single-Ended Input Table 10. Input Channel Selection for MODE = 1 SEL2 SEL1 SEL0 CH0 0 0 0 AIN+ 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM AIN- AIN+ AINAIN+ AINAIN+ AIN- AIN+ AINAIN+ AINAIN+ AINAIN+ AIN- Note: In single-ended mode pin COM should be connected to GND pin. Differential Input Table 11. Input Channel Selection for MODE = 0 SEL2 SEL1 SEL0 CH0 CH1 0 0 0 AIN+ AIN- 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 www.austriamicrosystems.com AIN- CH2 CH3 AIN+ AIN- CH4 CH5 AIN+ AIN- CH6 CH7 AIN+ AIN- AIN- AIN+ AIN+ AIN- AIN+ AIN- Revision 1.00 AIN+ 16 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Starting a Conversion A conversion is started by clocking a control byte into pin DIN. With CSN low, each rising edge on SCLK clocks a bit from DIN into the internal shift register, starting with the MSB. A conversion will only start when a logic 1 is written to the START bit of the 8-bit control register. Figure 21. Single Conversion Timing Waveforms CSN tACQ SCLK 1 DIN 4 8 Start SEL2 SEL1 SEL0 RANGE MODE PD1 9 12 20 16 24 PD0 High-Z High-Z SSTRB RB1 RB2 RB3 High-Z High-Z B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 DOUT Idle Acquire Single Conversion Idle Figure 22. Continuous 16-Clock Conversion Timing Waveforms CSN DIN S Control Byte 0 1 8 S Control Byte 1 12 16 1 8 S Control Byte 2 12 16 1 8 S 12 ... 16 SCLK High-Z DOUT B9 B4 B0 Conversion Result 0 B9 B4 B0 Conversion Result 1 B9 B4 Conversion Result 2 High-Z SSTRB www.austriamicrosystems.com Revision 1.00 17 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Figure 23. Detailed Serial Interface Timing Waveforms CSN tCL tCSS tCSO tCH tCP tCSW SCLK tDS tDH tDOH DIN tDOV tDOD tDOE DOUT tSTH tSTE tSTV tSTD SSTRB The external serial clock shifts data in and out of the devices and drives the analog-to-digital conversion steps. Two clock periods after the last bit of the control byte is written the output pin SSTRB pulses high for one clock period. The serial data is shifted out at DOUT on each of the next 12 SCLK rising edges (see Figure 21 on page 17). Pins SSTRB and DOUT go into a high-impedance state when CSN goes high. The conversion must complete in 120µs or less, or consequently, droop on the sample-and-hold capacitors may degrade conversion results. Figure 23 shows detailed serial-interface timing waveforms. Transfer Functions Output coding and transfer function depend on the control register bits MODE (page 15) and RANGE (page 15). Figure 24. Straight Binary Transfer Function for RANGE = 1 and MODE = 1 11...111 Figure 25. Straight Binary Transfer Function for RANGE = 0 and MODE = 1 11...111 Full Scale (FS) Transition 11...1110 Full Scale = VREF Zero Scale = 0 1LSB = VREF/1024 Full Scale = +VREF/2 Zero Scale = -VREF/2 1LSB = VREF/1024 Output Code 11....101 Output Code 11....101 Full Scale (FS) Transition 11...1110 00...011 00...011 00...010 00...010 00...001 00...001 00...000 00...000 0 1 2 3 FS - 3/2LSB ZS Input Voltage AIN+ - AIN- (LSB) www.austriamicrosystems.com ZS+1LSB FS - 3/2LSB Input Voltage AIN+ - AIN- (LSB) Revision 1.00 18 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Figure 26. Two’s Complement Transfer Function for RANGE = 1 and MODE = 0 011....111 Full Scale = VREF -Full Scale = 0 Zero Scale = VREF/2 1LSB = VREF/1024 011....111 011...110 000...010 Output Code Output Code 011...110 Figure 27. Two’s Complement Transfer Function for RANGE = 0 and MODE = 0 000...001 000...000 111...111 000...010 000...001 000...000 111...111 111...110 111...110 111...101 111...101 100...001 100...001 100...000 100...000 -FS ZS Full Scale = +VREF/2 -Full Scale = -VREF/2 Zero Scale = 0 1LSB = VREF/1024 +FS - 1LSB -FS Input Voltage AIN+ - AIN- (LSB) ZS +FS - 1LSB Input Voltage AIN+ - AIN- (LSB) Power Modes Power consumption can be reduced by placing the AS1520/AS1521 in reduced power mode or in full power-down mode between conversions. The power mode is selected using bits PD1 and PD0 of the 8-bit control byte. Table 12 lists the three operating modes with the corresponding supply current and active device circuits. For data rates achievable in full power-down mode see Full Power-Down Mode on page 20. Table 12. Software Controlled Power Modes Total Supply Current PD1/PD0 (page 23) 00 01 10 11 * Mode During Conversion Device Circuits After Conversion * AS1520 AS1521 AS1520 AS1521 Input Comparator Reference Full Power-Down Mode 2.8mA 2.2mA 0.5µA 0.5µA Off Off Reduced-Power Mode 2.8mA 2.2mA 0.4mA 0.4mA Reduced Power On Normal Operation 2.8mA 2.2mA 2.0mA 1.8mA Full Power On Circuit operation between conversions; during conversion all circuits are fully powered up. The selected power-down mode (as shown in Table 12) is initiated after an analog-to-digital conversion is completed. In all power modes the serial interface remains active, waiting for a new control byte to start conversion (see Figure 30 on page 21). Once the conversion is completed, the AS1520/AS1521 goes into the selected power mode until a new control byte is shifted in. In reduced power mode the AS1520/AS1521 will be able to start conversion immediately when running at decreased clock rates. In full power down mode wait until the internal reference has stabilized (dependant on the values of the capacitance of REF and REFADJ). During initialization the AS1520/AS1521 immediately go into normal operation mode and are ready to convert after 4µs when using an external reference. When using the internal reference, wait until the internal reference has stabilized (dependant on the values of the capacitance of REF and REFADJ). www.austriamicrosystems.com Revision 1.00 19 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Reduced Power Mode Reduced power mode is activated using bits PD1 and PD0 (see Table 12). When reduced power mode is asserted, the AS1520/AS1521 completes any conversion in progress and enters reduced power mode. The next start of conversion puts the AS1520/AS1521 into normal operation mode. The 8-bit control byte shifted into the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and PD0 = 1, reduced power mode starts immediately after the conversion (see Figure 28). The reduced-power mode achieves the lowest power consumption at speeds close to the maximum sample rate. Figure 29 shows the AS1521 power consumption in reduced-power mode and normal operating mode (see Table 12 on page 19) with the internal reference and maximum clock speed. Figure 28. Reduced-Power Mode Timing Waveforms (AS1521) DIN 1 1 0 1 ReducedPower Mode 1 0 ReducedPower Mode 0 1 ReducedPower Mode 2.50V (Always On) REF 2.2mA VDD1+VDD2 +VDD3 1 2.2mA Normal Mode Conversion 0.4mA 2.2mA Normal Mode Conversion Normal Mode Conversion 0.4mA Reduced Power Mode Reduced Power Mode 0.4mA Reduced Power Mode Note: The clock speed in reduced-power mode should be limited to 4.8MHz. Full power-down mode may provide increased power savings in applications where the devices are inactive for long periods of time, where intermittent bursts of high-speed conversions are required. Figure 29. Normal Operation and Reduced Power Mode using Internal Reference (AS1521) 3000 Supply Current (µA) . 2500 Normal Operation 2000 1500 1000 Reduced Power Mode 500 0 0.001 0.1 10 1000 Sampling Rate (ksps) Full Power-Down Mode Full power-down is activated using bits PD1 and PD0 (see Table 12). Full power-down mode offers the lowest power consumption at up to 1000 conversions per-channel per-second. When full power-down is asserted, the AS1520/ AS1521 completes any conversion in progress and powers down into specified low-quiescent current state. The start of the next conversion puts the AS1520/AS1521 into normal operation mode. The 8-bit control byte shifted into the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and PD0 = 0, full power-down mode starts immediately after the conversion (see Figure 30 on page 21) www.austriamicrosystems.com Revision 1.00 20 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description A 0.01µF bypass capacitor plus the internal 17kΩ reference resistor at REFADJ form an R/C filter with a 170µs time constant. To achieve full 10-bit accuracy, 7 time constants (1.4ms) are required after power-up if the bypass capacitor is fully discharged between conversions. Waiting this 1.4ms in reduced-power mode instead of normal operation mode can further reduce power consumption. This is achieved by using the sequence shown in Figure 30 on page 21. Figure 31 on page 21 shows the AS1521 power consumption for conversions using full power-down mode (PD1 = PD0 = 0 (see Table 12), an external reference, and the maximum clock speed. One dummy conversion to power-up the device is required, but no wait-time is necessary to start the second conversion, thereby achieving lower power consumption up to the full sampling rate. Figure 30. Full Power-Down Timing Waveforms (AS1521) 1 0 0 1 10 1 00 1 DIN Full PowerDown REFADJ ReducedPower Mode Full PowerDown 1.22V 1.22V γ = R/C = 17Ωk x 0.01µF REF IVDD1+IVDD2 +IVDD3 2.5V 2.5V 2.2mA 2.2mA Normal Mode Conversion 0mA Full PowerDown Normal Mode Dummy Conversion 2.2mA 0.4mA Reduced Power Mode Normal Mode Conversion 0mA Full PowerDown Figure 31. Average Supply Current vs. Sampling Rate (AS1521, FULLPD, and External Reference) Supply Current (µA) . 100000 1 Channel 100 0.1 0.001 0.01 0.1 1 10 100 Sampling Rate (ksps) Reference The AS1520/AS1521 can operate with the internal or an external reference. Internal Reference The internal reference is selected by placing a capacitor between REFADJ and GND. The internally trimmed 1.22V bandgap voltage available at REFADJ is buffered with a gain of 2.045V/V to pin REF, where 2.5V are available. A decoupling capacitor is needed at pin REF. www.austriamicrosystems.com Revision 1.00 21 - 29 AS1520/AS1521 Data Sheet - D e t a i l e d Description Additionally the bandgap voltage can be adjusted about ±100mV by forcing a voltage to the REFADJ pin. The REFADJ input impedance is typically 17kΩ. Figure 32 shows a possible arrangement. Figure 32. Reference Adjust Circuit +3.3V 24kΩ 100kΩ 510kΩ 12 REFADJ AS1520/ AS1521 CLOAD 0.01µF DGND GND External Reference An external reference can be connected directly at pin REF. To use the external reference, the internal buffer must be disabled by connecting pin REFADJ to pin VDD. The input resistance is typically 15kΩ. During conversion, an external reference at pin REF must deliver up to 350µA DC load current and have 10Ω or less output impedance. If the reference has a higher output impedance or is noisy, bypass it with a 4.7µF capacitor placed as close to pin REF as possible. Note: Using the REFADJ input makes buffering the external reference unnecessary. www.austriamicrosystems.com Revision 1.00 22 - 29 AS1520/AS1521 Data Sheet - A p p l i c a t i o n Information 9 Application Information Initialization When power is first applied to the AS1520/AS1521 internal power-on reset circuitry sets the devices for normal operation. At this point, the devices can perform data conversions with CSN held low. Note: The device requires 10µs after the power supplies stabilize; no conversions should be initiated during this time. The digital output at pin DOUT will be all 0s until an analog-to-digital conversion is initiated. Serial Interface The AS1520/AS1521 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0). Note: Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the circuit shown in Figure 33 on page 24, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the AS1520/AS1521, and two more 8-bit transfers to clock out the 10-bit conversion result). Serial Interface Configuration The following steps describe how to configure the serial interface: 1. Confirm that the CPU serial interface is in master mode (so the CPU generates the serial clock). 2. Choose a clock frequency from 500kHz to 6.4MHz (AS1520) or 4.8MHz (AS1521). 3. Set up the control byte and call it TB1. TB1 should be in the format 1XXXXXXX binary, where the Xs indicate the selected channel, conversion mode, and power mode. 4. Use a general-purpose I/O line on the CPU to pull CSN low. 5. Transmit TB1 and simultaneously receive a byte (RB1). Ignore this byte. 6. Transmit a byte of all zeros ($00h) and simultaneously receive byte RB2. 7. Transmit a byte of all zeros ($00h) and simultaneously receive byte RB3. 8. Pull CSN high. Bytes RB2 and RB3 (see Figure 21 on page 17) contain the results of the conversion, padded with three leading zeros and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive track/hold droop, make sure the total conversion time does not exceed 120µs. www.austriamicrosystems.com Revision 1.00 23 - 29 AS1520/AS1521 Data Sheet - A p p l i c a t i o n Information Figure 33. Operational Diagram +3 to +5V 1 CH0 20 VDD1 . . . +2.5V Analog Inputs 8 CH7 AS1520/ AS1521 11 REF 10µF CPU 17 I/O CSN 18 SCLK 16 SCK (SK) DIN 14 DOUT MOSI (SO) MISO (SI) 15 SSTRB 12 REFADJ 0.1µF 0.1µF 13 GND 9 COM 4.7µF VDD 19 VDD2 10 VDD3 VSS QSPI Interface The AS1520/AS1521 can interface with QSPI using the circuit in Figure 34 (fSCLK = 4.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without affecting CPU performance, since QSPI incorporates a micro-sequencer. Figure 34. QSPI Interface Connections 1 CH0 19 VDD2 . . . +2.5V Analog Inputs 8 CH7 9 COM 11 REF 12 REFADJ 4.7µF 20 VDD1 0.1µF +3 or +5V + 10µF 10 VDD3 13 GND AS1520/ AS1521 17 CSN 18 SCLK 16 DIN 14 DOUT CPU PCSO Power Supplies +3 or +5V SCK MOSI MISO GND 15 SSTRB 0.1µF www.austriamicrosystems.com Revision 1.00 24 - 29 AS1520/AS1521 Data Sheet - A p p l i c a t i o n Information Quick Evaluation Circuit In order to quickly evaluate the analog performance of the AS1520/AS1521, use the circuit shown in Figure 35. Figure 35. Evaluation Circuit Diagram +3 or +5V 20 VDD1 19 VDD2 10 VDD3 +2.5V Analog Input 8 CH7 10µF 13 GND AS1520/ AS1521 0.1µF 0.1µF 17 CSN TBA 18 9 COM SCLK 16 11 REF DIN 14 DOUT 12 REFADJ 4.7µF External Clock To VDD2 15 SSTRB 0.1µF Connecting DIN to VDD2 shifts in control bytes of $FFh, which trigger single-ended conversions (bit RANGE (page 15) = 1) on CH7 without powering down between conversions. The SSTRB output pulses high for one clock period before the MSB of the 10-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 16 clock cycles is required per conversion. Note: All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK. www.austriamicrosystems.com Revision 1.00 25 - 29 AS1520/AS1521 Data Sheet - A p p l i c a t i o n Information Layout Considerations The AS1520/AS1521 require proper layout and design procedures for optimum performance. ! Use printed circuit boards; wirewrap boards should not be used. ! Analog and digital traces should be separate and should not run parallel to each other (especially clock traces). ! Digital traces should not run beneath the AS1520/AS1521. ! Use a single-point analog ground at GND, separate from the digital ground (see Figure 36). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. ! High-frequency noise in the VDD power supply may affect the AS1520/AS1521 high-speed comparator. Bypass this supply to the single-point analog ground with 0.1µF and 4.7µF bypass capacitors. Bypass capacitors should be as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a 10Ω resistor can be connected as a low-pass filter to attenuate supply noise (see Figure 36). Figure 36. Recommended GND Design GND DGND VDD2 VDD Digital Circuitry 19 + VDD2 9 Power Supplies COM 13 GND GND + 20 VDD1 VDD1 10Ω (Optional) www.austriamicrosystems.com AS1520/ AS1521 Revision 1.00 10 VDD3 26 - 29 AS1520/AS1521 Data Sheet - P a c k a g e Drawings and Markings 10 Package Drawings and Markings Figure 37. 20-pin TSSOP Package Notes: 1. All dimensions are in millimeters; angles in degrees. 2. Dimensioning and tolerancing per ASME Y14.5M – 1994. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per side. 4. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 6. Terminal numbers are for reference only. 7. Datums A and B to be determined at datum plane H. 8. Dimensions D and E1 are to be determined at datum plane H. 9. This dimension applies only to variations with an even number of leads per side. 10. Cross section A-A to be determined at 0.10 to 0.25mm from the leadtip. Symbol A A1 A2 L R R1 b b1 c c1 θ1 L1 aaa bbb ccc ddd e θ2 θ3 D E1 E e N www.austriamicrosystems.com Revision 1.00 Min 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0º Typ 0.90 0.60 0.22 1.0REF 0.10 0.10 0.05 0.20 0.65BSC 12ºREF 12ºREF Variations 6.40 6.50 4.30 4.40 6.4BSC 0.65BSC 20 Max 1.10 0.15 0.95 0.75 0.30 0.25 0.20 0.16 8º Notes 1,2 1,2 1,2 1,2 1,2 1,2 1,2,5 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 6.60 4.50 1,2,3,8 1,2,4,8 1,2 1,2 1,2,6 27 - 29 AS1520/AS1521 Data Sheet - O r d e r i n g Information 11 Ordering Information The devices are available as the standard products shown in Table 13. Table 13. Ordering Information Model Description Delivery Form Package AS1520-BTST 10-bit ADC, 8-channel, 400ksps Tape and Reel 20-pin TSSOP AS1520-BTSU 10-bit ADC, 8-channel, 400ksps Tubes 20-pin TSSOP AS1521-BTST 10-bit ADC, 8-channel, 300ksps Tape and Reel 20-pin TSSOP AS1521-BTSU 10-bit ADC, 8-channel, 300ksps Tubes 20-pin TSSOP www.austriamicrosystems.com Revision 1.00 28 - 29 AS1520/AS1521 Data Sheet Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.00 29 - 29