AD AD9433

12-Bit, 105 MSPS/125 MSPS,
IF Sampling ADC
AD9433
IF sampling up to 350 MHz
SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS
SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS
SFDR: 72 dBc, fIN = 150 MHz at 105 MSPS
2 V p-p analog input range
On-chip clock duty cycle stabilization
On-chip reference and track-and-hold
SFDR optimization circuit
Excellent linearity
DNL: ±0.25 LSB (typical)
INL: ±0.5 LSB (typical)
750 MHz full power analog bandwidth
Power dissipation: 1.35 W (typical) at 125 MSPS
Twos complement or offset binary data format
5.0 V analog supply operation
2.5 V to 3.3 V TTL/CMOS outputs
APPLICATIONS
Cellular infrastructure communication systems
3G single- and multicarrier receivers
IF sampling schemes
Wideband carrier frequency systems
Point-to-point radios
LMDS, wireless broadband
MMDS base station units
Cable reverse path
Communications test equipment
Radar and satellite ground systems
FUNCTIONAL BLOCK DIAGRAM
AIN
ENCODE
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external reference or driver components are required for many applications.
The digital outputs are TTL-/CMOS-compatible, and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
ENCODE
TIMING
GND
PIPELINE
ADC
12
REF
OUTPUT
STAGING
12
D11 TO D0
DFS
SFDR
MODE
VREFOUT
VREFIN
Figure 1.
A user-selectable, on-chip proprietary circuit optimizes
spurious-free dynamic range (SFDR) vs. signal-to-noise and
distortion (SINAD) ratio performance for different input signal
frequencies, providing as much as 83 dBc SFDR performance
over the dc to 70 MHz band.
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is userselectable for offset binary or twos complement and provides
an overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a 52-lead thin quad flat package (TQFP_EP) that
is specified over the industrial temperature range of −40°C to
+85°C. The AD9433 is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
1.
GENERAL INTRODUCTION
The AD9433 is a 12-bit, monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
designed for ease of use. The product operates up to a 125 MSPS
conversion rate and is optimized for outstanding dynamic performance in wideband and high IF carrier systems.
T/H
AIN
ENCODE
VDD
AD9433
VCC
2.
3.
4.
IF Sampling.
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G wideband
cellular IF sampling receivers.
Pin-Compatibility with the AD9432.
The AD9433 has the same footprint and pin layout as the
AD9432 12-bit 80 MSPS/105 MSPS ADC.
SFDR Performance.
A user-selectable, on-chip circuit optimizes SFDR
performance as much as 83 dBc from dc to 70 MHz.
Sampling Rate.
At 125 MSPS, the AD9433 is ideally suited for wireless and
wired broadband applications such as LMDS/MMDS and
cable reverse path.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
01977-001
FEATURES
AD9433
TABLE OF CONTENTS
Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Terminology .................................................................................... 14 General Introduction ....................................................................... 1 Equivalent Circuits ......................................................................... 16 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 17 Product Highlights ........................................................................... 1 Encode Input ............................................................................... 17 Revision History ............................................................................... 2 Encode Voltage Level Definition.............................................. 17 Specifications..................................................................................... 3 Analog Input ............................................................................... 18 DC Specifications ......................................................................... 3 SFDR Optimization.................................................................... 18 AC Specifications.......................................................................... 4 Digital Outputs ........................................................................... 18 Switching Specifications .............................................................. 5 Voltage Reference ....................................................................... 18 Timing Diagram ........................................................................... 5 Timing ......................................................................................... 18 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 19 Explanation of Test Levels ........................................................... 6 Layout Information .................................................................... 19 Thermal Characteristics .............................................................. 6 Replacing the AD9432 with the AD9433 ................................ 19 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 20 REVISION HISTORY
6/09—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Added TQFP_EP Package ................................................. Universal
Deleted LQFP_ED Package ............................................... Universal
Changes to Thermal Characteristics Section ................................ 6
Changes to Pin Configuration and Function Descriptions
Section ................................................................................................ 7
Deleted Evaluation Board Section ................................................ 16
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
10/01—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD9433
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.3 V, VCC = 5 V; internal reference; differential encode input, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
THERMAL DRIFT
Offset Error
Gain Error1
Reference
REFERENCE
Internal Reference Voltage
(VREFOUT)
Output Current (VREFOUT)
Input Current (VREFIN)
ANALOG INPUTS (AIN, AIN)
Input Voltage Range
Common-Mode Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
VCC
VDD
Power Dissipation 3
IVCC3
IVDD3
Power Supply Rejection Ratio
(PSRR)
ENCODE INPUTS
Internal Common-Mode Bias
Differential Input
(ENCODE, ENCODE)
Input Voltage Range
Input Common-Mode Range
Input Resistance
Input Capacitance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input High Current (VIN = 5 V)
Input Low Current (VIN = 0 V)
Temp
Test
Level
Min
105 MSPS
Typ
Max
12
Full
Full
25°C
25°C
Full
25°C
Full
VI
VI
I
I
VI
I
VI
−5
−7
−0.75
−1
−1.0
−1.3
Full
Full
Full
V
V
V
Full
I
Full
Full
V
IV
100
Full
Full
Full
Full
Full
V
V
VI
V
V
2.0
4.0
3
4
750
Full
Full
Full
Full
Full
25°C
IV
IV
VI
VI
VI
I
Full
Full
V
V
Full
Full
Full
25°C
IV
IV
VI
V
−0.5
2.0
Full
Full
Full
Full
I
I
V
V
2.0
Guaranteed
0
+5
±1
+3
±0.25
+0.75
+1
±0.5
+1.0
+1.3
Min
−5
−7
−0.75
−1
−1.0
−1.3
−50
−125
±80
2.4
2.5
125 MSPS
Typ
12
Guaranteed
0
+5
±1
+3
±0.3
+0.75
+1
±0.5
+1.0
+1.3
−50
−125
±80
2.6
2.4
2.5
4.75
2.7
5.0
1275
255
12.5
±3
4
2
5.25
3.3
1425
285
14
4.75
2.7
2.0
4.0
3
4
750
5.0
1350
270
16
±3
3.75
500
−0.5
2.0
6
3
V
50
μA
μA
4
5.25
3.3
1500
300
18
6
3
2.0
50
50
Rev. A | Page 3 of 20
0.8
50
50
V p-p
V
kΩ
pF
MHz
V
V
mW
mA
mA
mV/V
V
mV
VCC + 0.05
4.25
0.8
mV
% FS
LSB
LSB
LSB
LSB
2.6
3.75
500
VCC + 0.05
4.25
Unit
Bits
ppm/°C
ppm/°C
ppm/°C
100
50
2
Max
V
V
kΩ
pF
V
V
μA
μA
AD9433
Parameter
DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
Output Coding
1
2
3
Temp
Test
Level
Full
Full
VI
VI
105 MSPS
Typ
Max
Min
125 MSPS
Typ
Min
Max
VDD − 0.05
VDD − 0.05
0.05
Twos complement or offset binary
0.05
Twos complement or offset binary
Unit
V
V
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
SFDR mode disabled (SFDR MODE = GND) for DNL and INL specifications.
Power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0). IVCC and IVDD measured with 10.3 MHz analog input @ −0.5 dBFS.
AC SPECIFICATIONS
VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE 1
Signal-to-Noise Ratio (SNR) (Without Harmonics)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Signal-to-Noise and Distortion (SINAD) Ratio
(with Harmonics)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Effective Number of Bits (ENOB)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Second-Order and Third-Order Harmonic
Distortion
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Worst Other Harmonic or Spur (Excluding
Second-Order and Third-Order Harmonics)
fIN = 10.3 MHz
fIN = 49 MHz
fIN = 70 MHz
fIN = 150 MHz
fIN = 250 MHz
Two-Tone Intermodulation Distortion (IMD3)
fIN1 = 49.3 MHz; fIN2 = 50.3 MHz
fIN1 = 150 MHz; fIN2 = 151 MHz
1
Temp
Test
Level
25°C
25°C
25°C
25°C
25°C
I
I
V
V
V
66.5
65.5
68.0
67.5
67.0
65.4
63.7
66.0
64.0
67.7
66.0
65.4
62.0
60.0
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
I
I
V
V
V
66.0
64.0
68.0
67.5
66.9
64.0
61.2
65.0
63.5
67.0
65.5
64.5
61.5
57.7
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
I
I
V
V
V
10.9
10.7
10.6
10.0
9.4
Bits
Bits
Bits
Bits
Bits
25°C
25°C
25°C
25°C
25°C
I
I
V
V
V
−78
−73
−85
−80
−83
−72
−67
−76
−72
−85
−76
−78
−67
−65
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
I
I
V
V
V
−88
−82
−92
−89
−87
−87
−85
−84
−82
−90
−87
−85
−84
−76
dBc
dBc
dBc
dBc
dBc
25°C
25°C
V
V
−90
−76
dBc
dBc
Min
105 MSPS
Typ
Max
Min
11.1
11.0
10.9
10.4
9.9
−92
−80
125 MSPS
Typ
Max
Unit
SNR/harmonics based on an analog input voltage of −0.5 dBFS referenced to a 2 V full-scale input range. Harmonics are specified with the SFDR mode enabled
(SFDR MODE = 5 V). SNR/SINAD specified with the SFDR mode disabled (SFDR MODE = ground).
Rev. A | Page 4 of 20
AD9433
SWITCHING SPECIFICATIONS
VDD = 3.3 V, VCC = 5 V; differential encode input, unless otherwise noted.
Table 3.
Parameter
Encode Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter) 1
Output Valid Time (tV) 2
Output Propagation Delay (tPD)2
Output Rise Time (tR)2
Output Fall Time (tF)2
Out-of-Range Recovery Time
Transient Response Time
Latency
1
2
Test
Level
IV
IV
IV
V
V
VI
VI
V
V
V
V
IV
Temp
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
25°C
25°C
Full
Min
10
2.9
2.9
105 MSPS
Typ
Max
105
2.5
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
Min
10
2.4
2.4
2.5
5.5
125 MSPS
Typ
Max
125
2.1
0.25
4.0
4.0
2.1
1.9
2
2
10
Unit
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
5.5
Aperture uncertainty includes contribution of the AD9433, crystal clock reference, and encode drive circuit.
tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is not
to exceed an ac load of 10 pF or a dc current of 50 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAM
SAMPLE N – 1
SAMPLE N
SAMPLE N + 9
SAMPLE N + 10
AIN
tA
SAMPLE N + 1
tEH
tEL
SAMPLE N + 8
1/fS
ENCODE
ENCODE
D11 TO D0
DATA N – 11
DATA N – 10
DATA
N–9
DATA
N–2
DATA N – 1
Figure 2. Timing Diagram
Rev. A | Page 5 of 20
tV
DATA N
DATA N + 1
01977-003
tPD
AD9433
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 4.
Parameter
VDD
VCC
Analog Inputs
Digital Inputs
Digital Output Current
Operating Temperature Range (TA)
Storage Temperature Range
Maximum Junction Temperature (TJ)
Table 5 lists AD9433 thermal characteristics for simulated typical
performance in a 4-layer JEDEC board, horizontal orientation.
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to VCC + 0.5 V
−0.5 V to VDD + 0.5 V
20 mA
−40°C to +85°C
−65°C to +125°C
150°C
Table 5. Thermal Resistance
Package Type
52-Lead TQFP_EP (SV-52-2)1
No Airflow
1.0 m/s Airflow
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA
θJMA
θJC
2
19.3
16
Bottom of package (exposed pad soldered to ground plane).
ESD CAUTION
EXPLANATION OF TEST LEVELS
I
II
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
Rev. A | Page 6 of 20
Unit
°C/W
°C/W
°C/W
AD9433
GND
DFS
SFDR MODE
GND
VCC
VREFIN
VREFOUT
VCC
GND
AIN
AIN
GND
VCC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
39
GND
38
GND
3
37
VCC
GND
4
36
VCC
VCC
5
GND
VCC
6
AD9433
35
34
GND
ENCODE
7
TOP VIEW
(Not to Scale)
33
GND
ENCODE
8
32
VDD
GND
9
31
DGND
VCC 10
30
D0 (LSB)
GND 11
29
D1
DGND 12
28
D2
VDD 13
27
D3
GND
1
VCC
2
GND
PIN 1
NOTES
1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE MUST
BE SOLDERED TO THE GROUND PLANE. SOLDERING THE EXPOSED
PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER
JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE.
01977-002
D4
D5
DGND
VDD
VDD
DGND
D6
D7
D8
D9
D10
OR
D11 (MSB)
14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1, 3, 4, 9, 11, 33,
34, 35, 38, 39, 40,
43, 48, 51
2, 5, 6, 10, 36, 37,
44, 47, 52
7
8
12, 21, 24, 31
13, 22, 23, 32
14
15 to 20, 25 to 30
41
42
45
46
49
50
Mnemonic
GND
Description
Analog Ground.
VCC
Analog Supply (5 V).
ENCODE
ENCODE
DGND
VDD
OR
D11 to D6, D5 to D0
DFS
SFDR MODE
Encode Clock for ADC, Complementary.
Encode Clock for ADC, True. ADC samples on rising edge of ENCODE.
Digital Output Ground.
Digital Output Power Supply (3 V).
Out-of-Range Output.
Digital Output.
Data Format Select. Logic low = twos complement, logic high = offset binary; floats low.
CMOS Control Pin. This pin enables SFDR mode, a proprietary circuit that can improve the SFDR
performance of the AD9433. SFDR mode is useful in applications where the dynamic range of
the system is limited by discrete spurious frequency content caused by nonlinearities in the
ADC transfer function. Set this pin to 0 for normal operation; floats low.
Reference Input for ADC (2.5 V Typical). Bypass with 0.1 μF capacitor to ground.
Internal Reference Output (2.5 V Typical).
Analog Input, True.
Analog Input, Complementary.
The exposed paddle on the underside of the package must be soldered to the ground plane.
Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximizing the thermal capability of the package.
VREFIN
VREFOUT
AIN
AIN
Exposed Pad (EP)
Rev. A | Page 7 of 20
AD9433
TYPICAL PERFORMANCE CHARACTERISTICS
0
–95
SNR = 67.5dB
SFDR = 85dBFS
–10
–90
–20
WORST OTHER
–85
–40
HARMONICS (dBc)
AMPLITUDE (dBFS)
–30
–50
–60
–70
–80
–90
–100
–80
THIRD HARMONIC
–75
SECOND HARMONIC
–70
–65
0
13.1
26.3
FREQUENCY (MHz)
39.4
52.5
–60
01977-009
Figure 4. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
SNR = 68dB
SFDR = 80dBFS
–20
250
68
11.1
67
10.9
10.8
–80
–90
–110
13.1
26.3
FREQUENCY (MHz)
39.4
52.5
Figure 5. FFT: fS = 105 MSPS, fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Disabled
SINAD
63
10.3
62
10.1
61
9.9
60
01977-010
0
10.4
64
0
50
100
150
AIN (MHz)
200
250
ENOB (Bits)
–70
10.6
65
9.8
300
01977-013
–60
–100
Figure 8. SNR/SINAD and ENOB vs. AIN Frequency, Differential AIN @ −0.5 dBFS,
fS = 105 MSPS, SFDR Mode Disabled
0
100
SNR = 67.7dB
SFDR = 76dBFS
–10
95
–20
–30
THIRD HARMONIC (dBc)
90
–40
SNR/SINAD (dB)
AMPLITUDE (dBFS)
200
SNR
–50
–50
–60
–70
–80
–90
85
80
SECOND HARMONIC (dBc)
75
SNR
70
–100
65
–110
SINAD
0
15.6
31.2
FREQUENCY (MHz)
46.8
62.5
60
10
01977-011
–120
100
150
AIN (MHz)
66
–40
SNR/SINAD (dB)
AMPLITUDE (dBFS)
–30
–120
50
Figure 7. Harmonics (Second, Third, Worst Other) vs. AIN Frequency,
AIN @ −0.5 dBFS, fS = 105 MSPS, SFDR Mode Enabled
0
–10
0
Figure 6. FFT: fS = 125 MSPS, fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
Rev. A | Page 8 of 20
30
50
70
90
ENCODE (MSPS)
110
130
01977-014
–120
01977-012
–110
Figure 9. SNR/SINAD and Harmonic Distortion vs. Encode Frequency,
Differential AIN @ −0.5 dBFS
AD9433
IMD3 = 92dBFS
–20
AMPLITUDE (dBFS)
–30
69
11.3
67
10.9
65
SNR/SINAD (dB)
–40
–50
–60
–70
–80
–90
–100
10.6
SNR
SINAD
63
ENOB (Bits)
0
–10
10.3
61
9.9
59
9.6
57
9.3
–110
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
Figure 10. FFT: fS = 105 MSPS, fIN = 49.3 MHz and 50.3 MHz,
Differential AIN @ −7 dBFS for Each Tone, SFDR Mode Enabled
90
SFDR (dBc)
SNR/SFDR (dB)
DYNAMIC PERFORMANCE (dB)
90
SNR (dBFS)
70
60
SFDR (dBFS)
40
30
20
90dBFS
REFERENCE
80.3
AIN (MHz)
170.3
250.3
–80
–70
–60
–50
–40
–30
AIN LEVEL (dBFS)
THIRD HARMONIC
80
SECOND HARMONIC
70
SNR
60
50
40
30
20
10
–20
–10
0
0
3.5
01977-016
10
0
–90
49.3
100
100
50
10.3
Figure 13. SNR/SINAD and ENOB vs. AIN Frequency, Differential AIN @ −0.5 dBFS,
fS = 125 MSPS, SFDR Mode Enabled
110
80
8.9
55
01977-018
7.5
Figure 11. SNR and SFDR vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz,
Differential AIN, SFDR Mode Enabled
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
AIN COMMON-MODE VOLTAGE (V)
4.4
4.5
01977-019
0
01977-015
–120
Figure 14. Dynamic Performance vs. AIN Common-Mode Voltage,
Differential AIN @ −0.5 dBFS, fIN = 49.3 MHz, fS = 105 MSPS
110
69
68
100
66
90
–40°C
SNR (dB)
THIRD-ORDER IMD (dB)
67
80
65
64
+25°C
63
70
62
60
+85°C
–80
–70
–60
–50
–40
–30
AIN LEVEL (dBFS)
–20
–10
0
60
01977-017
50
–90
Figure 12. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz
and 50.3 MHz, Differential AIN, SFDR Mode Enabled
Rev. A | Page 9 of 20
10.3
49.3
80.3
AIN (MHz)
170.3
250.3
01977-020
61
Figure 15. SNR vs. AIN Frequency over Temperature, fS = 105 MSPS,
Differential AIN, SFDR Mode Disabled
AD9433
–95
300
18
280
15
WORST OTHER (dBc)
THIRD HARMONIC (dBc)
12
ICC (mA)
260
–80
SECOND HARMONIC (dBc)
–75
ICC (mA)
9
240
6
220
IDD (mA)
10
20
30
40
50
60
DUTY CYCLE HIGH (%)
70
80
90
180
0
25
0.50
0.50
0.25
0.25
INL (LSB)
0.75
0
–0.25
–0.25
–0.50
–0.50
0
512
1024
1536
2048
2560
OUTPUT CODE
3072
3584
4096
–0.75
01977-022
Figure 17. Integral Nonlinearity vs. Output Code with SFDR Mode Disabled
0
512
1024
1536
2048
2560
OUTPUT CODE
3072
3584
4096
Figure 20. Integral Nonlinearity vs. Output Code with SFDR Mode Enabled
0.5
0
0.4
–10
–20
0.3
–30
AMPLITUDE (dBFS)
0.2
0.1
0
–0.1
–0.2
–40
–50
–60
–70
–80
–90
–0.3
–100
–110
–0.5
–120
0
512
1024
1536
2048
2560
OUTPUT CODE
3072
3584
Figure 18. Differential Nonlinearity vs. Output Code
4096
01977-023
–0.4
0
7.68
15.36
FREQUENCY (MHz)
23.04
30.72
01977-026
INL (LSB)
0.75
–0.75
0
125
100
Figure 19. IDD and ICC vs. Encode Rate, fIN = 10.3 MHz,
Differential AIN @ −0.5 dBFS
Figure 16. Dynamic Performance vs. Encode Duty Cycle, fS = 105 MSPS,
fIN = 49.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled
0
50
75
ENCODE FREQUENCY (MHz)
01977-025
0
3
200
01977-024
SNR (dB)
–70
–65
DNL (LSB)
IDD (mA)
–85
01977-021
DYNAMIC PERFORMANCE (dB)
–90
Figure 21. FFT: fS = 61.44 MSPS, fIN = 46.08 MHz, Four WCDMA Carriers,
Differential AIN, SFDR Mode Enabled
Rev. A | Page 10 of 20
AD9433
0
0
SNR = 66.8dB
SFDR = 83dBFS
–20
–20
–30
–30
AMPLITUDE (dBFS)
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
–120
Figure 22. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
100
SFDR (dBFS)
90
–30
SNR (dBFS)
80
SNR/SFDR (dB)
–40
–50
–60
–70
–80
70
60
SFDR (dBc)
50
40
80dBFS REFERENCE LINE
–100
20
fS = 105MSPS
fIN = 70.3MHz
–110
10
DIFFERENTIAL AIN
SFDR ENABLED
7.5
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
0
–90
01977-030
0
Figure 23. FFT: fS = 105 MSPS, fIN = 70.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Disabled
–80
–70
–60
–50
–40
–30
AIN LEVEL (dBFS)
–20
–10
0
01977-031
30
–90
–120
52.5
110
SNR = 67dB
SFDR = 80dBFS
–20
AMPLITUDE (dBFS)
7.5
Figure 25. FFT: fS = 105 MSPS, fIN = 69.3 MHz and 70.3 MHz,
Differential AIN @ −7 dBFS for Each Tone, SFDR Mode Enabled
0
–10
Figure 26. SNR and SFDR vs. AIN Level, fS = 105 MSPS, fIN = 70.3 MHz,
Differential AIN, SFDR Mode Enabled
0
–110
SNR = 65.5dB
SFDR = 78dBFS
–10
–20
–100
THIRD-ORDER IMD (dBFS)
–30
AMPLITUDE (dBFS)
0
01977-029
–40
–120
IMD3 = 85dBc
–10
01977-027
AMPLITUDE (dBFS)
–10
–40
–50
–60
–70
–80
–90
–100
–90
–80
–70
–60
0
6.2
12.5
18.7
25.0 31.2 37.5 43.7
FREQUENCY (MHz)
50.0
56.2
62.5
–50
–90
01977-028
–120
Figure 24. FFT: fS = 125 MSPS, fIN = 70.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
–80
–70
–60
–50
–40
–30
AIN LEVEL (dBFS)
–20
–10
0
01977-032
–110
Figure 27. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 70.3 MHz
and 69.3 MHz, Differential AIN, SFDR Mode Enabled
Rev. A | Page 11 of 20
AD9433
0
0
–30
AMPLITUDE (dBFS)
–20
–30
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–110
–110
0
7.5
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
–120
12.5
18.7
25.0 31.2 37.5 43.7
FREQUENCY (MHz)
50.0
56.2 62.5
–30
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
–120
01977-034
7.5
Figure 29. FFT: fS = 105 MSPS, fIN = 250.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
0
6.2
12.5
18.7
25.0 31.2 37.5 43.7
FREQUENCY (MHz)
50.0
56.2 62.5
01977-037
AMPLITUDE (dBFS)
–20
0
SNR = 54.6dB
SFDR = 58dBFS
–10
–30
Figure 32. FFT: fS = 125 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
–110
0
SNR = 55.3dB
SFDR = 61dBFS
–10
–100
–20
–90
THIRD-ORDER IMD (dBFS)
–30
–40
–50
–60
–70
–80
–90
–80
–70
–60
–50
–40
–30
–20
–100
7.5
15.0
22.5
30.0
37.5
FREQUENCY (MHz)
45.0
52.5
0
–90
01977-035
0
Figure 30. FFT: fS = 105 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
–80
–70
–60
–50
–40
–30
AIN LEVEL (dBFS)
–20
–10
0
01977-038
–10
–110
–120
6.25
0
SNR = 61.2dB
SFDR = 67dBFS
–20
–120
0
Figure 31. FFT: fS = 125 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
0
–10
AMPLITUDE (dBFS)
–50
–100
Figure 28. FFT: fS = 105 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS,
SFDR Mode Enabled
AMPLITUDE (dBFS)
–40
–90
01977-033
AMPLITUDE (dBFS)
–20
–120
SNR = 62dB
SFDR = 70dBFS
–10
01977-036
SNR = 64dB
SFDR = 78dBFS
–10
Figure 33. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 150.3 MHz
and 151.3 MHz, Differential AIN, SFDR Mode Enabled
Rev. A | Page 12 of 20
0
–10
–20
–20
–30
–30
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
0
9.6
19.2
FREQUENCY (MHz)
28.8
38.4
–120
Figure 34. FFT: fS = 76.8 MSPS, fIN = 59.6 MHz, Two WCDMA Carriers,
Differential AIN, SFDR Mode Enabled
0
11.52
23.04
FREQUENCY (MHz)
34.56
46.08
01977-040
AMPLITUDE (dBFS)
0
–10
01977-039
AMPLITUDE (dBFS)
AD9433
Figure 35. FFT: fS = 92.16 MSPS, fIN = 70.3 MHz, WCDMA @ 70.0 MHz,
SFDR Mode Enabled
Rev. A | Page 13 of 20
AD9433
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential voltage is computed by
rotating the input phase 180° and taking the peak measurement again. The difference is then computed between both
peak measurements.
Differential Nonlinearity (DNL)
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
measured SNR based on the following equation:
Gain Error
The difference between the measured and the ideal full-scale
input voltage range of the ADC.
Harmonic Distortion
The ratio of the rms signal amplitude fundamental frequency
to the rms signal amplitude of a single harmonic component
(second, third, and so on); reported in dBc.
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Maximum Conversion Rate
The maximum encode rate at which parametric testing is
performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Noise (for Any Range within the ADC)
Noise can be calculated using the following equation:
− SNRdBc − Signal dBFS
⎛ FS
VNOISE = Z × 0.001 × 10 ⎜⎜ dBm
10
⎝
⎞
⎟⎟
⎠
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal and quantization
noise.
⎛ Full − Scale Amplitude ⎞
⎟
SNR MEASURED − 1.76 dB + 20 log ⎜
⎜ Input Amplitude ⎟
⎝
⎠
ENOB =
6.02
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
encode pulse should be left in the Logic 1 state to achieve the
rated performance. Pulse width low is the minimum amount
of time that the encode pulse should be left in the Logic 0 state.
At a given clock rate, these specifications define an acceptable
encode duty cycle.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
PowerFullScale
⎛
⎜ V 2 FullScale
rms
= 10 log ⎜
Z
⎜
⎜
0.001
⎝
⎞
⎟
⎟
⎟
⎟
⎠
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Rev. A | Page 14 of 20
AD9433
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(degrades as signal level is lowered) or in dBFS (always related
back to converter full scale).
Two-Tone SFDR
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in
dBc (degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the worst third-order intermodulation product;
reported in dBc. Products are located at 2f1 − f2 and 2f2 − f1.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second-order and
third-order harmonic); reported in dBc.
Rev. A | Page 15 of 20
AD9433
EQUIVALENT CIRCUITS
VCC
VCC
VREFIN
01977-008
01977-006
VREFOUT
Figure 39. Voltage Reference Output Circuit
Figure 36. Voltage Reference Input Circuit
VCC
VCC
3.75kΩ
3.75kΩ
8kΩ
AIN
AIN
8kΩ
ENCODE
ENCODE
15kΩ
01977-005
15kΩ
24kΩ
01977-007
24kΩ
Figure 37. Analog Input Circuit
Figure 40. Encode Input Circuit
VDD
01977-004
Dx
Figure 38. Digital Output Circuit
Rev. A | Page 16 of 20
AD9433
THEORY OF OPERATION
The AD9433 is a 12-bit pipeline converter that uses a switchedcapacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to and beyond the
Nyquist limit. DNL transitional errors are calibrated at final test
to a typical accuracy of 0.25 LSB or less.
ENCODE
The ENCODE and ENCODE inputs are internally biased
to 3.75 V (nominal) and support either differential or singleended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained using
an MC10EL16 translator in the circuit to directly drive the
encode inputs (see Figure 41).
0.1µF
CLOCK
SOURCE
100Ω
01977-042
AD9433
T1-4T
ENCODE
ENCODE
HMS2812
DIODES
Figure 43. Transformer-Coupled Encode Circuit
ENCODE VOLTAGE LEVEL DEFINITION
The voltage level definitions for driving ENCODE and ENCODE
in single-ended and differential mode are shown in Figure 44.
ENCODE
VIHD
VID
VICM, VECM
ENCODE
01977-041
ENCODE
ENCODE
Figure 41. Using PECL to Drive the ENCODE Inputs
VILD
VIHS
VICM, VECM
Often, the cleanest clock source is a crystal oscillator producing
a pure, single-ended sine wave. In this configuration, or with
any roughly symmetrical, single-ended clock source, the signal
can be ac-coupled to the encode input. To minimize jitter, the
signal amplitude should be maximized within the input range
described in Table 7. The 12 kΩ resistors to ground at each of
the inputs, in parallel with the internal bias resistors, set the
common-mode voltage to approximately 2.5 V, allowing the
maximum swing at the input. The ENCODE input should be
bypassed with a capacitor to ground to reduce noise. This ensures
that the internal bias voltage is centered on the encode signal.
For best dynamic performance, impedances at ENCODE and
ENCODE should match.
ENCODE
VILS
01977-044
510Ω
12kΩ
Figure 43 shows another preferred method for clocking the
AD9433. The clock source (low jitter) is converted from singleended to differential using an RF transformer. The back-to-back
Schottky diodes across the transformer secondary limit clock
excursions into the AD9433 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock
from feeding through to other portions of the AD9433 and limits
the noise presented to the encode inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate
limiting resistor (typically 100 Ω) is placed in series with the
primary.
AD9433
510Ω
25Ω
Figure 42. Single-Ended Sine Source Encode Circuit
ENCODE
PECL
GATE
ENCODE
50Ω
01977-043
The AD9433 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling edge
of ENCODE if driven differentially) and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. This circuit is
always on and cannot be disabled by the user.
12kΩ
0.1µF
50Ω
SINE
SOURCE
ENCODE INPUT
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the ADC output.
For this reason, considerable care has been taken in the design
of the encode input of the AD9433, and the user is advised to
give commensurate thought to the clock source.
AD9433
0.1µF
0.1µF
Figure 44. Differential and Single-Ended Input Levels
Table 7. Encode Inputs
Input
Differential Signal Amplitude
(VID)
Input Voltage Range
(VIHD, VILD, VIHS, VILS)
Internal Common-Mode Bias
(VICM)
External Common-Mode Bias
(VECM)
Rev. A | Page 17 of 20
Min
200 mV
Nominal
750 mV
Max
5.5 V
VCC + 0.5 V
−0.5 V
3.75 V
2.0 V
4.25 V
AD9433
ANALOG INPUT
The analog input to the AD9433 is a differential buffer. The
input buffer is self-biased by an on-chip resistor divider that
sets the dc common-mode voltage to a nominal 4 V (see the
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. The minimum input offset
voltage is obtained when driving from a source with a low
differential source impedance, such as a transformer in ac
applications (see Figure 45). Capacitive coupling at the inputs
increases the input offset voltage by as much as 50 mV.
25Ω
0.1µF
AIN
25Ω
01977-045
AIN
1:1
Table 8. Offset Binary Output Coding (DFS = 1, VREF = 2.5 V)
Figure 45. Transformer-Coupled Analog Input Circuit
In the highest frequency applications, two transformers connected in series may be necessary to minimize even-order
harmonic distortion. The first transformer isolates and converts
the signal to a differential signal, but the grounded input on the
primary side degrades amplitude balance on the secondary
winding. Capacitive coupling between the windings causes
this imbalance. Because one input to the first transformer is
grounded, there is little or no capacitive coupling, resulting in
an amplitude mismatch at the output of the first transformer. A
second transformer improves the amplitude balance, and thus
improves the harmonic distortion. A wideband transformer,
such as the ADT1-1WT from Mini-Circuits®, is recommended
for these applications, because the bandwidth through the two
transformers is reduced by √2.
AD9433
AIN
25Ω
25Ω
1:1
1:1
AIN
Code
4095
…
2048
2047
…
0
AIN − AIN (V)
+1.000
…
0
−0.00049
…
−1.000
Digital Output
1111 1111 1111
…
1000 0000 0000
0111 1111 1111
…
0000 0000 0000
Table 9. Twos Complement Output Coding
(DFS = 0, VREF = 2.5 V)
Code
+2047
…
0
−1
…
−2048
AIN − AIN (V)
+1.000
…
0
−0.00049
…
−1.000
Digital Output
0111 1111 1111
…
0000 0000 0000
1111 1111 1111
…
1000 0000 0000
VOLTAGE REFERENCE
0.1µF
01977-046
50Ω
ANALOG
SIGNAL
SOURCE
DIGITAL OUTPUTS
The digital outputs are 3 V (2.7 V to 3.3 V) TTL-/CMOScompatible for lower power consumption. The output data
format is selectable through the data format select (DFS)
CMOS input. DFS = 1 selects offset binary; DFS = 0 selects
twos complement coding (see Table 8 and Table 9).
AD9433
50Ω
ANALOG
SIGNAL
SOURCE
Enabling this circuit gives the circuit a dynamic transfer function,
meaning that the voltage threshold between two adjacent output
codes can change from clock cycle to clock cycle. While improving
spurious frequency content, this dynamic aspect of the transfer
function may be inappropriate for some time domain applications
of the converter. Connecting the SFDR MODE pin to ground
disables this function. The improvement in the linearity of the
converter and its effect on spurious free dynamic range is shown
in Figure 4 and Figure 5 and in Figure 22 and Figure 23.
Figure 46. Driving the Analog Input with Two Transformers for Improved
Even-Order Harmonics
Driving the ADC single-ended degrades performance, particularly even-order harmonics. For best dynamic performance,
impedances at AIN and AIN should match. Special care was
taken in the design of the analog input section of the AD9433
to prevent damage and corruption of data when the input is
overdriven.
SFDR OPTIMIZATION
When set to Logic 1, the SFDR MODE pin enables a proprietary
circuit that can improve the spurious-free dynamic range (SFDR)
performance of the AD9433. This pin is useful in applications
where the dynamic range of the system is limited by discrete
spurious frequency content caused by nonlinearities in the
ADC transfer function.
A stable and accurate 2.5 V voltage reference is built into the
AD9433 (VREFOUT). In normal operation, the internal reference is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF
decoupling capacitor at VREFIN. The input range can be adjusted
by varying the reference voltage applied to the AD9433. No appreciable degradation in performance occurs when the reference is
adjusted ±5%. The full-scale range of the ADC tracks reference
voltage changes linearly.
TIMING
The AD9433 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figure 2). The
length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9433;
these transients can detract from the dynamic performance of
the converter. The minimum guaranteed conversion rate of the
AD9433 is 10 MSPS. At internal clock rates below 10 MSPS,
dynamic performance may degrade.
Rev. A | Page 18 of 20
AD9433
APPLICATIONS INFORMATION
LAYOUT INFORMATION
REPLACING THE AD9432 WITH THE AD9433
A multilayer board is recommended to achieve best results. It is
highly recommended that high quality, ceramic chip capacitors be
used to decouple each supply pin to ground directly at the device.
The AD9433 is pin-compatible with the AD9432, although there
are two control pins on the AD9433 that are do not connect (DNC)
and supply (VCC) connections on the AD9432 (see Table 10).
The pinout of the AD9433 facilitates ease of use in the implementation of high frequency, high resolution design practices.
All of the digital outputs and their supply and ground pin
connections are segregated on one side of the package, with
the inputs on the opposite side for isolation purposes.
Table 10. AD9432/AD9433 Pin Differences
Care should be taken when routing the digital output traces.
To prevent coupling through the digital outputs into the analog
portion of the AD9433 (VCC, AIN, and VREF), minimal capacitive
loading should be placed on these outputs.
Pin
41
42
AD9433
DFS
SFDR MODE
Using the AD9433 in an AD9432 pin assignment configures the
AD9433 as follows:
•
•
It is recommended that a fanout of only one gate be used for all
AD9433 digital outputs.
The layout of the encode circuit is equally critical and should be
treated as an analog input. Any noise received on this circuitry
results in corruption in the digitization process and lower overall performance. The encode clock must be isolated from the
digital outputs and the analog inputs.
AD9432
DNC
VCC
The SFDR improvement circuit is enabled.
The DFS pin floats low, selecting twos complement coding
for the digital outputs. (Twos complement coding is the
only output coding available on the AD9432.)
Table 11 summarizes the differences between the AD9432 and
AD9433 analog and encode input common-mode voltages.
These inputs can be ac-coupled so that the devices can be used
interchangeably.
Table 11. AD9432/AD9433 Analog and Encode Input
Common-Mode Voltages
Input Pins
ENCODE/ENCODE
AIN/AIN
Rev. A | Page 19 of 20
Common-Mode Voltage
AD9432
AD9433
1.6 V
3.75 V
3.0 V
4.0 V
AD9433
OUTLINE DIMENSIONS
1.20
MAX
12.00 BSC
SQ
52
10.00
BSC SQ
TOP VIEW
0° MIN
0.15
0.05
1
PIN 1
(PINS DOWN)
1.05
1.00
0.95
39
39
SEATING
PLANE
52
40
40
1
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.30 BSC
SQ
EXPOSED
PAD
BOTTOM VIEW
13
27
14
26
VIEW A
(PINS UP)
27
26
0.65
BSC
LEAD PITCH
13
14
0.38
0.32
0.22
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ACC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
072508-A
0.75
0.60
0.45
Figure 47. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-52-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9433BSVZ-105 1
AD9433BSVZ-1251
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Z = RoHS Compliant Part.
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01977-0-6/09(A)
Rev. A | Page 20 of 20
Package Option
SV-52-2
SV-52-2