a 14-Bit, 40 MSPS/65 MSPS A/D Converter AD6644 FEATURES 65 MSPS Guaranteed Sample Rate 40 MSPS Version Available Sampling Jitter < 300 fs 100 dB Multitone SFDR 1.3 W Power Dissipation Differential Analog Inputs Digital Outputs Two’s Complement Format 3.3 V CMOS-Compatible Data Ready for Output Latching Designed for multichannel, multimode receivers, the AD6644 is part of ADI’s new SoftCell™ transceiver chipset. The AD6644 achieves 100 dB multitone, spurious-free dynamic range (SFDR) through the Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) which are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio is 74 dB. The AD6644 is also useful in single channel digital receivers designed for use in wide-channel bandwidth systems (CDMA, W-CDMA). With oversampling, harmonics can be placed outside the analysis bandwidth. Oversampling also facilitates the use of decimation receivers (such as the AD6620), allowing the noise floor in the analysis bandwidth to be reduced. By replacing traditional analog filters with predictable digital components, modern receivers can be built using fewer “RF” components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability. APPLICATIONS Multichannel, Multimode Receivers AMPS, IS-136, CDMA, GSM, Third Generation Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation The AD6644 is built on Analog Devices’ high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-terminal LowProfile Quad Plastic Flatpack (LQFP) specified from –25°C to +85°C. PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD6644 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included onchip to provide a complete conversion solution. The AD6644 provides CMOS-compatible digital outputs. It is the third generation in a wideband ADC family, preceded by the AD9042 (12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.) 1. Guaranteed sample rate is 65 MSPS. 2. Fully differential analog input stage. 3. Digital outputs may be run on 3.3 V supply for easy interface to digital ASICs. 4. Complete Solution: reference and track-and-hold. 5. Packaged in small, surface-mount, plastic, 52-terminal LQFP. FUNCTIONAL BLOCK DIAGRAM AVCC DVCC A1 TH1 AIN TH2 A2 TH4 TH3 TH5 ADC3 AIN VREF ADC1 2.4V DAC1 ADC2 5 ENCODE ENCODE 6 DAC2 AD6644 5 DIGITAL ERROR CORRECTION LOGIC INTERNAL TIMING MSB GND DMID OVR DRY D13 D12 LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SoftCell is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD6644–SPECIFICATIONS DC SPECIFICATIONS (AV CC = 5 V, DVCC = 3.3 V; TMIN = –25ⴗC, TMAX = +85ⴗC) Parameter Temp Test Level Min AD6644AST-40 Typ Max RESOLUTION AD6644AST-65 Typ Max Min 14 14 Unit Bits ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Full Full Full Full Full II II II II V TEMPERATURE DRIFT Offset Error Gain Error Full Full V V 10 95 10 95 ppm/°C ppm/°C –10 –10 –1.0 Guaranteed 3 –6 ± 0.25 ± 0.50 +10 +10 +1.5 Guaranteed 3 –6 ± 0.25 ± 0.50 –10 –10 –1.0 +10 +10 +1.5 mV % FS LSB LSB POWER SUPPLY REJECTION (PSRR) Full V ± 1.0 ± 1.0 mV/V REFERENCE OUT (VREF) Full V 2.4 2.4 V ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Full Full 25°C V V V 2.2 1 1.5 2.2 1 1.5 V p-p kΩ pF Full Full II II Full Full Full POWER SUPPLY Supply Voltage AVCC1 DVCC Supply Current IAVCC (AVCC = 5.0 V) IDVCC (DVCC = 3.3 V) POWER CONSUMPTION 4.85 3.0 5.0 3.3 5.25 3.6 II II 245 30 II 1.3 4.85 3.0 5.0 3.3 5.25 3.6 V V 276 36 245 30 276 36 mA mA 1.5 1.3 1.5 W NOTES 1 AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –25ⴗC, TMAX = +85ⴗC) Parameter Temp Test Level ENCODE INPUTS (ENC, ENC) Differential Input Voltage1 Differential Input Resistance Differential Input Capacitance Full 25°C 25°C IV V V Full Full V V Full V LOGIC OUTPUTS (D13–D0, DRY, OVR) Logic Compatibility Logic “1” Voltage2 Logic “0” Voltage2 Output Coding DMID Min AD6644AST-40 Typ Max 0.4 AD6644AST-65 Typ Max Min 0.4 10 2.5 V p-p kΩ pF 10 2.5 CMOS 2.5 0.4 Two’s Complement DVCC/2 Unit CMOS 2.5 0.4 Two’s Complement DVCC/2 V V V NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power. 2 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF will degrade performance. Specifications subject to change without notice. SWITCHING SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = –25ⴗC, TMAX = +85ⴗC) Parameter Temp Test Level Maximum Conversion Rate Minimum Conversion Rate ENCODE Pulsewidth High ENCODE Pulsewidth Low Full Full Full Full II IV IV IV Min AD6644AST-40 Typ Max 40 Min AD6644AST-65 Typ Max 65 15 10 10 15 6.5 6.5 Unit MSPS MSPS ns ns Specifications subject to change without notice. –2– REV. 0 AD6644 AC SPECIFICATIONS1 (AV CC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = –25ⴗC, TMAX = +85ⴗC) Temp Test Level 2.2 MHz 15.5 MHz 30.5 MHz 25°C 25°C 25°C II II II 74.5 74.0 73.5 72 72 72 74.5 74.0 73.5 dB dB dB 2.2 MHz 15.5 MHz 30.5 MHz 25°C 25°C 25°C II II V 74.5 74.0 73.0 72 72 74.5 74.0 73.0 dB dB dB WORST HARMONIC (2ND or 3RD)2 Analog Input 2.2 MHz @ –1 dBFS 15.5 MHz 30.5 MHz 25°C 25°C 25°C II II V 92 90 85 83 83 92 90 85 dBc dBc dBc WORST HARMONIC (4TH or Higher)2 Analog Input 2.2 MHz @ –1 dBFS 15.5 MHz 30.5 MHz 25°C 25°C 25°C II II V 93 92 92 85 85 93 92 92 dBc dBc dBc TWO-TONE SFDR2, 3, 4 Full V 100 100 dBFS Full V 90 90 dBc 25°C V 250 250 MHz Parameter SNR Analog Input @ –1 dBFS SINAD2 Analog Input @ –1 dBFS TWO-TONE IMD REJECTION F1, F2 @ –7 dBFS AD6644AST-40 Typ Max Min Min AD6644AST-65 Typ Max Unit 2, 4 ANALOG INPUT BANDWIDTH NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 AVCC = 5 V to 5.25 V for rated ac performance. 3 Analog input signal power swept from –7 dBFS to –100 dBFS. 4 F1 = 15 MHz, F2 = 15.5 MHz. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter (AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = –25ⴗC, TMAX = +85ⴗC, CLOAD = 10 pF) Name Temp Test Level tENC tENC tENCH tENCL Full Full Full Full V V IV IV 6.2 6.2 tDR tE_DR Full IV 2.6 Full Full IV IV 10.3 15.1 Full Full Full IV IV IV 3.8 3.0 3.0 Full Full IV IV 6.2 15.9 Min AD6644AST-40/65 Typ Max Unit 1 ENCODE INPUT PARAMETERS Encode Period1 @ 65 MSPS Encode Period1 @ 40 MSPS Encode Pulsewidth High2 @ 65 MSPS Encode Pulsewidth Low @ 65 MSPS ENCODE/DATA READY Encode Rising to Data Ready Falling Encode Rising to Data Ready Rising @ 65 MSPS (50% Duty Cycle) @ 40 MSPS (50% Duty Cycle) ENCODE/DATA (D13:0), OVR ENC to DATA Falling Low ENC to DATA Rising Low ENCODE to DATA Delay (Hold Time)3 ENCODE to DATA Delay (Setup Time)4 Encode = 65 MSPS (50% Duty Cycle) Encode = 40 MSPS (50% Duty Cycle) REV. 0 tE_FL tE_RL tH_E tS_E –3– 15.4 25 7.7 7.7 9.2 9.2 ns ns ns ns 3.4 tENCH + tDR 11.1 15.9 4.6 ns 12.3 17.1 ns ns 5.5 4.3 4.3 tENC – tE_FL 9.8 19.4 9.2 6.4 6.4 ns ns ns 11.6 21.2 ns ns AD6644–SPECIFICATIONS Parameter Name DATA READY (DRY5)/DATA, OVR Data Ready to DATA Delay (Hold Time)2 Encode = 65 MSPS (50% Duty Cycle) Encode = 40 MSPS (50% Duty Cycle) Data Ready to DATA Delay (Setup Time)2 @ 65 MSPS (50% Duty Cycle) @ 40 MSPS (50% Duty Cycle) Temp Test Level Min Full Full IV IV 8.0 12.8 Full Full IV IV 3.2 8.0 AD6644AST-40/65 Typ Max tH_DR Note 6 8.6 13.4 Note 6 5.5 10.3 tS_DR Unit 9.4 14.2 ns ns 6.5 11.3 ns ns APERTURE DELAY tA 25°C V 100 ps APERTURE UNCERTAINTY (JITTER) tJ 25°C V 0.2 ps rms NOTES 1 Several timing parameters are a function of t ENC and tENCH. 2 To compensate for a change in duty cycle for t H_DR and tS_DR use the following equation: NewtH_DR = (tH_DR – % Change(tENCH)) × tENC/2 NewtS_DR = (tS_DR – % Change(tENCH)) × tENC/2. 3 ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter. 4 ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t S_E for a given encode use the following equation: NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 × 10–9 – 15.38 × 10–9 + 9.8 × 10–9 = 19.4 × 10 –9). 5 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 6 Data Ready to DATA Delay(t H_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t ENC and duty cycle. In order to calculate t H_DR and tS_DR for a given encode use the following equations: NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: Newt H_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 8.6 × 10–9 = 13.4 × 10–9 NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 5.5 × 10–9 = 10.3 × 10–9. Specifications subject to change without notice. tA Nⴙ3 N AIN Nⴙ1 Nⴙ2 Nⴙ4 t ENC ENC, ENC t ENCH t ENCL Nⴙ1 N Nⴙ2 t E_FL t E_DR t E_RL D[13:0], OVR Nⴙ3 N–3 t H_E t S_E N–2 N–1 t DR Nⴙ4 t S_DR N t H_DR DRY Figure 1. Timing Diagram –4– REV. 0 AD6644 ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current Min Max Unit 0 0 0 7 7 AVCC 25 AVCC 4 V V V mA V mA +85 150 300 +150 °C °C °C °C 0 ENVIRONMENTAL2 Operating Temperature Range (Ambient) –25 Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) –65 EXPLANATION OF TEST LEVELS Test Level I II 100% production tested. 100% production tested at 25°C, and guaranteed by design and characterization at temperature extremes. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (52-terminal LQFP); θJA = 33°C/W; θJC = 11°C/W. These measurements were taken on a 6 layer board in still air with a solid ground plane. ORDERING GUIDE Model Temperature Range Package Description Package Option AD6644AST-40 AD6644AST-65 AD6644ST/PCB –25°C to +85°C (Ambient) –25°C to +85°C (Ambient) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) Evaluation Board with AD6644AST–65 ST-52 ST-52 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD6644 PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 33, 43 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 DVCC GND 3.3 V Power Supply (Digital) Output Stage Only. Ground. VREF 5 6 8, 9, 14, 16, 18, 22, 26, 28, 30 11 12 20 ENCODE ENCODE AVCC AIN AIN C1 24 C2 31 32 35 36 37–41, 44–50 51 52 DNC OVR DMID D0 (LSB) D1–D5, D6–D12 D13 (MSB) DRY 2.4 V (Analog Reference). Bypass to ground with 0.1 µF microwave chip capacitor. Encode Input; conversion initiated on rising edge. Complement of ENCODE; differential input. 5 V Analog Power Supply. Analog Input. Complement of AIN; Differential Analog Input. Internal Voltage Reference; bypass to ground with 0.1 µF microwave chip capacitor. Internal Voltage Reference; bypass to ground with 0.1 µF microwave chip capacitor. Do not connect this pin. Overrange Bit; high indicates analog input exceeds ± FS. Output Data Voltage Midpoint; approximately equal to (DVCC)/2. Digital Output Bit (Least Significant Bit); Two’s Complement Digital Output Bits in Two’s Complement. Digital Output Bit (Most Significant Bit); Two’s Complement. Data Ready Output. D4 GND D5 D6 DVCC D8 D7 D10 D9 D12 D11 DRY D13 (MSB) PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 DVCC 1 39 PIN 1 IDENTIFIER GND 2 VREF 3 38 36 D1 D0 (LSB) 37 GND 4 ENCODE 5 ENCODE 6 GND 7 D3 D2 35 DMID AD6644 34 TOP VIEW (Not to Scale) 33 GND DVCC 32 OVR AVCC 9 GND 10 AIN 11 31 DNC AVCC AIN 12 GND 13 28 GND AVCC 27 GND AVCC 8 30 29 C2 GND AVCC GND C1 GND AVCC GND GND AVCC AVCC GND AVCC 14 15 16 17 18 19 20 21 22 23 24 25 26 DNC = DO NOT CONNECT –6– REV. 0 AD6644 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Noise (For Any Range Within the ADC) FSdBm – SignaldBFS 10 Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements. VNOISE = | Z | ×0.001 × 10 Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) Differential Nonlinearity The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. The deviation of any code width from an ideal 1 LSB step. Signal-to-Noise Ratio (Without Harmonics) Encode Pulsewidth/Duty Cycle The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable ENCODE duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection V Full Scale rms | Z |Input = 10 log 0.001 2 PowerFull Scale Harmonic Distortion, 2nd The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, 3rd The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least-square curve fit. REV. 0 –7– AD6644 EQUIVALENT CIRCUITS DVCC VCH AVCC CURRENT MIRROR AIN BUF T/H 500⍀ VCL VREF BUF VCH AVCC DVCC VREF 500⍀ AIN D0–D13, OVR, DRY T/H BUF VCL Figure 2. Analog Input Stage CURRENT MIRROR Figure 5. Digital Output Stage LOADS AVCC AVCC AVCC AVCC 10k⍀ AVCC AVCC 10k⍀ ENCODE ENCODE 2.4V VREF 10k⍀ 10k⍀ 100A LOADS Figure 3. ENCODE Inputs Figure 6. 2.4 V Reference AVCC DVCC VREF AVCC 10k⍀ AVCC DMID CURRENT MIRROR 10k⍀ C1 OR C2 Figure 4. Compensation Pin, C1 or C2 Figure 7. DMID Reference –8– REV. 0 Typical Performance Characteristics– AD6644 0 75.0 ENCODE = 65MSPS AIN = 2.2MHz @ –1dBFS SNR = 74.5dB SFDR = 92dBc –10 –20 –30 ENCODE = 65MSPS, AIN = –1dBFS TEMP = –25 C, ⴙ25 C, ⴙ85 C 74.5 T = –25 C –40 74.0 SNR – dB –50 –60 –70 –80 T = ⴙ85 C T = ⴙ25 C 73.5 73.0 –90 –100 72.5 –110 –120 –130 0 5 10 15 20 FREQUENCY – MHz 25 72.0 30 5 0 Figure 8. Single Tone at 2.2 MHz 10 15 20 FREQUENCY – MHz 25 30 Figure 11. Noise vs. Analog Frequency (Nyquist) 94 0 ENCODE = 65MSPS AIN = 15.5MHz @ –1dBFS SNR = 74dB SFDR = 90dBc –20 –30 ENCODE = 65MSPS, AIN = –1dBFS WORST-CASE HARMONIC – dBc –10 –40 –50 –60 –70 –80 –90 –100 –110 TEMP = ⴚ25 C, ⴙ25 C, ⴙ85 C 92 90 T = ⴙ25 C T = ⴚ25 C, ⴙ85 C 88 86 84 82 –120 –130 0 5 10 15 20 FREQUENCY – MHz 25 80 30 5 0 Figure 9. Single Tone at 15.5 MHz 10 15 20 25 ANALOG INPUT FREQUENCY – MHz 30 Figure 12. Harmonics vs. Analog Frequency (Nyquist) 75 0 ENCODE = 65MSPS AIN = 30MHz @ –1dBFS SNR = 73.5dB SFDR = 85dBc –10 –20 –30 LOW NOISE ANALOG SOURCE 74 73 –40 SNR – dB –50 –60 –70 –80 –90 72 PHASE NOISE OF ANALOG SOURCE DEGRADES PERFORMANCE 71 70 –100 –110 69 AIN = –1dBFS ENCODE = 65MSPS –120 –130 0 5 10 15 20 FREQUENCY – MHz 25 68 30 0 Figure 10. Single Tone at 30 MHz REV. 0 10 20 30 40 50 60 70 80 ANALOG FREQUENCY – MHz 90 100 Figure 13. Noise vs. Analog Frequency (IF) –9– AD6644 100 0 95 WORST OTHER SPUR –10 ENCODE = 65MSPS AIN = –1dBFS 90 HARMONICS – dBc ENCODE = 65MSPS AIN = 15MHz, 15.5MHz @ –7dBFS NO DITHER –20 –30 –40 85 –50 80 –60 75 –70 –80 70 –90 HARMONICS (2nd, 3rd) –100 65 –110 60 –120 55 0 10 20 30 40 60 50 70 80 ANALOG FREQUENCY – MHz 90 –130 100 Figure 14. Harmonics vs. Analog Frequency (IF) 10 15 20 FREQUENCY – MHz 25 30 Figure 17. Two Tones at 15 MHz and 15.5 MHz 120 110 WORST-CASE SPURIOUS – dBFS and dBc WORST-CASE SPURIOUS – dBFS and dBc 5 0 110 dBFS 100 ENCODE = 65MSPS AIN = 15.5MHz 90 80 dBc 70 60 SFDR = 90dB REFERENCE LINE 50 40 30 20 10 0 –80 –70 –20 –10 –60 –50 –30 –40 ANALOG INPUT POWER LEVEL – dBFS dBFS 100 ENCODE = 65MSPS F1 = 15MHz F2 = 15.5MHz 90 80 60 SFDR = 90dB REFERENCE LINE 50 40 30 20 10 0 –77 0 dBc 70 Figure 15. Single Tone SFDR –57 –47 –37 –67 –27 –17 INPUT POWER LEVEL – (F1 = F2) dBFS –7 Figure 18. Two-Tone SFDR 100 0 ENCODE = 65MSPS AIN = 19MHz, 19.5MHz @ –7dBFS NO DITHER –20 AIN = 2.2MHz @ –1dBFS SNR, WORST SPURIOUS – dB and dBc –10 –30 –40 –50 –60 –70 –80 –90 –100 –110 95 WORST SPUR 90 85 80 75 SNR 70 65 –120 60 –130 0 5 10 15 20 FREQUENCY – MHz 25 30 Figure 16. Two Tones at 19 MHz and 19.5 MHz 0 10 20 40 50 60 70 30 ENCODE FREQUENCY – MHz 80 90 Figure 19. SNR, Worst Spurious vs. Encode –10– REV. 0 AD6644 0 0 ENCODE = 65MSPS AIN = 15.5MHz @ –29.5dBFS NO DITHER –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0 5 10 ENCODE = 65MSPS AIN = 15.5MHz @ –29.5dBFS DITHER @ –19dBm –10 15 20 FREQUENCY – MHz 25 30 0 Figure 20. 1M FFT Without Dither 90 70 60 50 40 SFDR = 90dB REFERENCE LINE 30 20 10 0 –90 –80 –20 –10 –70 –60 –50 –40 –30 ANALOG INPUT POWER LEVEL – dBFS SNR, WORST SPURIOUS – dB and dBc 30 ENCODE = 65MSPS AIN = 15.5MHz DITHER = –19dBm 70 60 50 SFDR = 100dB REFERENCE LINE 40 30 SFDR = 90dB REFERENCE LINE 20 WORST SPUR ENCODE = 65MSPS 85 30.5MHz 80 SNR 2.2MHz 75 30.5MHz 70 –10.0 5.0 –5.0 10.0 0 ENCODE INPUT POWER – dBm –80 –60 –20 –70 –50 –40 –30 –10 ANALOG INPUT POWER LEVEL – dBFS Figure 24. SFDR with Dither 2.2MHz 15.0 Figure 22. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 25) REV. 0 80 0 –90 0 95 65 –15.0 25 10 Figure 21. SFDR Without Dither 90 15 20 FREQUENCY – MHz 100 ENCODE = 65MSPS AIN = 15.5MHz NO DITHER WORST-CASE SPURIOUS – dBc WORST-CASE SPURIOUS – dBc 80 10 Figure 23. 1M FFT with Dither 100 90 5 –11– 0 AD6644 THEORY OF OPERATION 0.1F The AD6644 analog-to-digital converter (ADC) employs a three stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. CLOCK SOURCE T1–4T ENCODE 100⍀ AD6644 ENCODE As shown in the functional block diagram, the AD6644 has complementary analog input pins, AIN and AIN . Each analog input is centered at 2.4 V and should swing ± 0.55 V around this reference (Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peakto-peak. Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. HSMS2812 DIODES Figure 25. Crystal Clock Oscillator – Differential Encode If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola. VT 0.1F ENCODE ECL/ PECL AD6644 0.1F ENCODE VT Figure 26. Differential ECL for Encode Analog Input As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6644 is differential. Differential inputs allow much improvement in performance on-chip as signals are processed through the analog stages. Most of the improvement is a result of differential analog stages having high rejection of even order harmonics. There are also benefits at the PCB level. First, differential inputs have high commonmode rejection to stray signals such as ground and power noise. Also, they provide good rejection to common-mode signals such as local oscillator feedthrough. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two's complement. APPLYING THE AD6644 Encoding the AD6644 The AD6644 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz input signals when using a high-jitter clock source. See Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance” for complete details. For optimum performance, the AD6644 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Shown below is one preferred method for clocking the AD6644. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6644 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD6644, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω) is placed in the series with the primary. The AD6644 input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to a 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6644 should be ac-coupled to the input pins. Since the differential input impedance of the AD6644 is 1 kΩ, the analog input power requirement is only –2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high-input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6644 is to use a 4:1 RF transformer. For example, if RT were set to 60.4 Ω and RS were set to 25 Ω, along with a 4:1 transformer, the input would match to a 50 Ω source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The terminating resistor (RT) should be placed on the primary side of the transformer. ANALOG INPUT SIGNAL T1–4T RS AIN RT AD6644 RS AIN 0.1F Figure 27. Transformer-Coupled Analog Input Circuit –12– REV. 0 AD6644 In applications where dc-coupling is required, a new differential output op amp from Analog Devices, the AD8138, can be used to drive the AD6644 (Figure 28). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements. CF 499⍀ VIN 0.1F 25⍀ VOCM AD8138 499⍀ 25⍀ AIN AD6644 AIN Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6644, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one gate be used for all AD6644 digital outputs. The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs. 5V 499⍀ tion of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. DIGITAL OUTPUTS VREF Jitter Considerations The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter. 499⍀ CF Figure 28. DC-Coupled Analog Input Circuit Power Supplies Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be “received” by the AD6644. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 µF chip capacitors. 1/ 2 2 2 V (1 + ε ) SNR = –20 × log N + (2 × π × f ANALOG × t J RMS )2 + NOISEN RMS 2 2 Output Loading Care must be taken when designing the data receivers for the AD6644. It is recommended that the digital outputs drive a series resistor (e.g. 100 Ω) followed by a gate like 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 30. The digital outputs of the AD6644 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ⫻ 1 V ⫼ 1 ns) of dynamic current per bit will flow in or out of the device. A full scale transition can cause up to 140 mA (14 bits ⫻ 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close to the AD6644 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD6644. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads. fANALOG = analog input frequency. tJ RMS = rms jitter of the encode (rms sum of encode source and internal encode circuitry). ε = average DNL of the ADC (typically 0.41 LSB). N = Number of bits in the ADC. VNOISE RMS = V rms thermal noise referred to the analog input of the ADC (typically 2.5 LSB). For a 14-bit analog-to-digital converter like the AD6644, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD6644 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices’ Application Note AN-501, “Aperture Uncertainty and ADC System Performance.” Layout Information The schematic of the evaluation board (Figure 30) represents a typical implementation of the AD6644. A multilayer board is recommended to achieve the best results. It is highly recommended that high-quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6644 facilitates ease of use in the implementaREV. 0 80 AIN = 30MHz AIN = 70MHz 75 SNR – dB The AD6644 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD6644 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs. (1) 70 AIN = 110MHz 65 AIN = 150MHz 60 AIN = 190MHz 55 0 0.1 0.2 0.3 0.4 JITTER – ps Figure 29. SNR vs. Jitter –13– 0.5 0.6 AD6644 EVALUATION BOARD The evaluation board for the AD6644 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock, and the analog inputs. The evaluation board includes the option for an onboard clock oscillator for ENCODE. Power to the analog supply pins of the AD6644 is connected via the power terminal block (PCTB2). Power for the digital interface is supplied via pin 1 of J6. The J2 connector mates directly with SoftCell Receive Signal Processor (AD6620, AD6624) evaluation boards, allowing complete evaluation of system performance. The analog input is connected via a BNC connector AIN, which is transformer-coupled to the AD6644 inputs. The transformer has a turns ratio of 1:4 to reduce the amount of input power required to drive the AD6644. The Encode signal may be generated using an onboard crystal oscillator, U5. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled OPT_CLK or BNC connector labeled ENCODE. If an external source is used, it must be a high-quality and very low-phase noise source. The AD6644 output data is latched using 74LCX574 (U7, U2) latches. The clock for these latches is determined by selecting jumper E3–E4 or E4–E5. E3 to E5 is a just a gate delayed version of the clock, while connecting E4 to E5 utilizes the Data Ready of the AD6644 to latch the output data. A clock is also distributed with the output data (J2) that is labeled BUFLAT (Pin 19 and 20, J2). AD6644ST/PCB Bill of Material Item Quantity Reference Description 1 2 2 19 Tantalum Chip Capacitor 10 µF Ceramic Chip Capacitor 0508, 0.1 µF 3 4 5 6 7 8 9 10 11 12 13 8 1 1 4 2 1 1 2 1 1 4 C1, C2 C3, C7, C8, C9, C10, C11, C16, C30, C31, C32, C4, C22, C23, C24, C25, C26, C27, C28, C29 C12, C13, C14, C17, C18, C19, C20, C21 CR1 E3, E4, E5 F1, F2, F3, F4 J1, J6 J2 J3 J4, J5 R1 R2 R3, R4, R5, R8 14 15 16 17 18 2 1 1 1 30 19 20 21 22 2 1 2 1 R6, R7 R9 R10 R35 R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65 T2, T3 U1 U2, U7 U3 23 24 2 1 U4, U6 U5 –14– Ceramic Chip Capacitor 0508, 0.01 µF HSMS2812 Surface Mount Diode 3-Pin Header Ferrite (Optional) PCTB2 50-Pin Double Row Header SMA Connector BNC Connector Surface-Mount Resistor 1206, 100 Ω Surface-Mount Resistor 1206, 60.4 Ω Surface-Mount Resistor 0805, 499 Ω (Optional, DC-Coupling Only) Surface-Mount Resistor 0805, 25 Ω Surface-Mount Resistor 0805, 348 Ω Surface-Mount Resistor 0805, 615 Ω Surface-Mount Resistor 0805, 49.9 Ω Surface-Mount Resistor 0402, 100 Ω Surface-Mount Transformer Mini-Circuits T4–1, 1:4 Ratio AD6644AST 14-Bit 65 MSPS A/D Converter 74LCX574 Octal Latch AD8138 Single-to-Differential Amplifier (Optional – DC Coupling Only) NC7SZ32 Two Input OR Gate CTS Reeves Full-Size MX045 Crystal Clock Oscillator REV. 0 K1115 2 AIN J5 2 ENC J4 1 1 8 Figure 30. AD6644ST/PCB Schematic (GS02357D Schematic) R2 60.4⍀ R1 100⍀ C3 100nF T2 6 4 1 3P3VD R8 499⍀ DR_OUT 6 3 T1–4T 4 1 2 1:4 5 6 T3 4 5 C30 100nF CR1 VREF R4 499⍀ 2 Vⴙ 3 V– GND 1 8 2 U3 R5 499⍀ 5VA C27 100nF 1 3 ENC ENC E5 E3 R7 25⍀ VREF E4 C32 100NF OPT_LAT NC7SZ32 4 HSMS2812 C28 100nF GND 3 AD8138 R3 499⍀ C29 100nF 1:4 1 2 T1–4T 3 R9 348⍀ 2 ⴙV R10 615⍀ U4 5 3P3V 5VA R6 25⍀ GND 5VA 5VA GND AIN AIN GND 13 12 11 10 9 8 7 6 5 GND 4 3 3P3V 1 GND 2 U1 BUFLAT GND AIN AIN AD6644ST GND GND GND AVCC DNC AVCC OVR DVCC 14 15 16 17 18 19 20 21 22 23 24 25 26 AVCC GND AVCC GND ENC ENC DMID D1 D0 VREF GND D2 D3 GND DVCC 52 51 50 49 48 47 46 45 44 43 42 41 40 NOTE: THE DOTTED LINE REPRESENTS AN OPTIONAL ANALOG DRIVE INPUT C4 100nF R35 49.9⍀ GND OUT OPT_CLK J3 7 SMA 2 DR_OUT DRY AVCC 1 D13 GND C22 100nF AVCC 14 GND VCC AVCC NC D12 D11 D10 D9 D8 GND C1 5VA GND 5VA GND 5VA GND 1 GND AVCC F3 FERRITE GND D5 U5 3P3V GND D7 D6 DVCC GND C2 GND 3P3V PCTB2 1 2 J1 C8 100nF GND 5VA GND BNC BNC D4 AVCC –15– 30 5VA 29 GND 28 5VA 27 GND 31 32 PREF 34 GND 33 3P3V 35 36 37 38 39 1 C9 100nF 2 F1 FERRITE C1 10F GND C7 100nF GND 5VA REV. 0 C10 100nF C2 10F R43 R42 R41 R40 R39 R38 R36 R45 R46 R47 R48 R49 R50 R51 R44 C11 100nF C16 100nF GND 1 100⍀ 2 100⍀ 3 100⍀ 4 100⍀ 5 100⍀ 6 100⍀ 7 100⍀ 8 GND 9 GND 10 GND 1 100⍀ 2 100⍀ 3 100⍀ 4 100⍀ 5 100⍀ 6 100⍀ 7 100⍀ 8 100⍀ 9 GND 10 U7 20 19 19 20 C12 10nF C17 10nF C13 10nF C18 10nF 74LCX574 Q0 18 Q1 17 D2 Q2 16 Q3 D3 15 D4 Q4 14 D5 Q5 13 D6 Q6 12 D7 Q7 11 GND CLOCK D0 D1 OUT_EN VCC U2 GND 3 ⴙV 100⍀ 100⍀ 100⍀ 100⍀ 100⍀ 100⍀ 100⍀ H2 H3 H4 4 C20 10nF C14 10nF 1 2 F4 FERRITE C19 10nF C23 100nF B05 B04 B03 B02 B01 B00 GND GND GND GND GND GND OVR GND B13 B12 B11 B10 B09 B08 B07 B06 GND 20 28 30 27 29 38 37 48 50 C25 100nF 3P3V C26 100nF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 3P3VD HEADR50 46 47 49 44 42 45 43 41 40 36 35 39 34 33 32 26 25 31 24 23 22 18 19 21 16 17 14 12 15 13 11 8 10 9 6 7 5 2 4 3 J2 2 1 1 F2 FERRITE C24 100nF 5VA PCTB2 1 C21 10nF H1 MOUNTING HOLES BUFLAT 3P3VD R63 R62 R61 R60 R59 R58 R37 NC7SZ32 2 1 U6 5 3P3VD 3P3VD R65 100⍀ 100⍀ R52 R53 100⍀ R54 100⍀ 100⍀ R55 100⍀ R56 100⍀ R57 R64 100⍀ BUFLAT BUFLAT 74LCX574 Q0 18 Q1 17 D2 Q2 16 D3 Q3 15 D4 Q4 14 D5 Q5 13 D6 Q6 12 D7 Q7 11 GND CLOCK D0 D1 OUT_EN VCC J6 2 AD6644 AD6644 Figure 31. AD6644ST/PCB Top Side Silkscreen Figure 32. AD6644ST/PCB Top Side Copper –16– REV. 0 AD6644 Figure 33. AD6644ST/PCB Bottom Side Silkscreen Figure 34. AD6644ST/PCB Bottom Side Copper REV. 0 –17– AD6644 Figure 35. AD6644ST/PCB Ground Layer – Layers 2 and 5 (Negative) Figure 36. AD6644ST/PCB “Split” Power Layer – Layers 3 and 4 (Negative) –18– REV. 0 AD6644 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) 39 27 40 26 SEATING PLANE 0.394 (10.0) SQ TOP VIEW (PINS DOWN) 14 52 0.006 (0.15) 0.002 (0.05) 1 13 0.026 (0.65) BSC 0.015 (0.38) 0.009 (0.22) PRINTED IN U.S.A. 0.057 (1.45) 0.053 (1.35) C3812–5–4/00 (rev. 0) 52-Terminal Plastic Low Profile Quad Flatpack (ST-52) REV. 0 –19–