Quad-Channel Digital Isolators, 5KV ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Low power operation 5 V operation: 1.0 mA per channel max @ 0–2 Mbps 3.5 mA per channel max @ 10 Mbps 31 mA per channel max @ 90 Mbps 3 V operation: 0.7 mA per channel max @ 0–2 Mbps 2.1 mA per channel max @ 10 Mbps 20 mA per channel max @ 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: DC–90 Mbps (NRZ) Precise timing characteristics: 2 ns max. pulsewidth distortion 2 ns max. channel-to-channel matching High common-mode transient immunity: > 25 kV/μs Output enable function Wide body SOIC 16-lead package Safety and regulatory approvals (pending) UL recognition: 5000 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805):2001-12;EN 60950:2000 VIORM = 848 V peak IEC 60601-1 The ADuM240x are four-channel digital isolators based on Analog Devices’ iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. In comparison to the 2.5KV ADuM140x product family, ADuM240x models have increased insulation thickness to achieve the higher 5.0KV isolation rating. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple, iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these iCoupler products. Furthermore, iCoupler devices run at one-tenth to one-sixth the power consumption of optocouplers at comparable signal data rates. The ADuM240x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see Ordering Guide). All ADuM240x models operate with the supply voltage of either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM240x provides low pulse width distortion (<2 ns for CRWZ grade), and tight channel-to-channel matching (<2 ns for CRWZ grade). Unlike other optocoupler alternatives, the ADuM240x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. APPLICATIONS General-purpose, high voltage, multichannel isolation Medical Equipment Motor Drives Power Supplies 16 GND1 2 VIA 3 ENCODE DECODE 15 GND2 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VID ENCODE DECODE 11 VOD NC 7 10 VE2 GND1 8 9 6 Vdd1 1 VDD2 GND2 16 Vdd2 GND1 2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VOD 6 DECODE ENCODE VE1 7 03786-0-001 VDD1 1 Figure 1. ADuM2400 Functional Block Diagram GND1 8 VDD1 1 GND1 2 16 VDD2 15 GND2 VIA 3 ENCODE DECODE 14 VOA VIB 4 ENCODE DECODE 13 VOB VOC 5 DECODE ENCODE 12 VIC 11 VID VOD DECODE ENCODE 11 VID 10 VE2 VE1 7 10 VE2 GND1 8 9 GND2 9 GND2 Figure 2. ADuM2401 Functional Block Diagram 6 Figure 3. ADuM2402 Functional Block Diagram Rev. PrD October 5, 2004 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 03786-0-003 FUNCTIONAL BLOCK DIAGRAMS One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data ELECTRICAL CHARACTERISTICS—5 V OPERATION1 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADuM2400, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2402, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 or VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Symbol Typ Max Unit IDDI(Q) IDDO(Q) 0.50 0.19 0.53 0.21 mA mA IDD1(Q) IDD2(Q) 2.2 0.9 2.8 1.4 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1(10) IDD2(10) 8.6 2.6 10.6 3.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1(90) IDD2(90) 76 21 100 25 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1(Q) IDD2(Q) 1.8 1.2 2.4 1.8 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1(10) IDD2(10) 7.1 4.1 9.0 5.0 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1(90) IDD2(90) 62 35 82 43 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1(Q), IDD2(Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. IDD1(10), IDD2(10) 5.6 7.0 mA 5 MHz logic signal freq. IDD1(90), IDD2(90) 49 62 mA 45 MHz logic signal freq. 0.01 10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 ≤ VE1, VE2 ≤ VDD1 or VDD2 IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min –10 2.0 Test Conditions V 0.8 VDD1,VDD2 – 0.1 5.0 VDD1,VDD2 – 0.4 4.8 0.0 0.04 0.2 Rev. PrD| Page 2 of 23 0.1 0.1 0.4 V V V V V IOx = –20 µA, VIx = VIxH IOx = –4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL Preliminary Technical Data Parameter SWITCHING SPECIFICATIONS ADuM240xARW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH-tPHL|5 Propagation Delay Skew6 Channel-to-Channel Matching7 ADuM240xBRW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 ADuM240xCRW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10%–90%) Common-Mode Transient Immunity at Logic High Output8 Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate Input Dynamic Supply Current, per Channel9 Output Dynamic Supply Current, per Channel9 ADuM2400/ADuM2401/ADuM2402 Symbol Min Typ PW tPHL, tPLH PWD tPSK tPSKCD/OD 1 50 65 PW Max Unit Test Conditions 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 100 40 50 50 tPSK tPSKCD 15 3 ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns CL = 15 pF, CMOS signal levels 11.1 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 100 10 20 32 50 3 5 PW tPSK tPSKCD 10 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 90 18 8.3 120 27 0.5 3 32 2 tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/DD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.2 0.19 0.05 Mbps mA/Mbps mA/Mbps fr IDDI(D) IDDO(D) See Notes on next page. Rev. PrD | Page 3 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data NOTES 1 All voltages are relative to their respective ground. 2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20 . See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations. 3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating perchannel supply current for a given data rate. Rev. PrD| Page 4 of 23 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 ELECTRICAL CHARACTERISTICS—3 V OPERATION1 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent Output Supply Current, per Channel, Quiescent ADuM2400, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM2402, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 or VDD2 Supply Current 90 Mbps (CRWZ Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Symbol Typ Max Unit IDDI(Q) IDDO(Q) 0.26 0.11 0.31 0.14 mA mA IDD1(Q) IDD2(Q) 1.2 0.5 1.9 0.9 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1(10) IDD2(10) 4.5 1.4 6.5 2.0 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1(90) IDD2(90) 42 11 65 15 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1(Q) IDD2(Q) 1.0 0.7 1.6 1.2 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1(10) IDD2(10) 3.7 2.2 5.4 3.0 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1(90) IDD2(90) 34 19 52 27 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1(Q), IDD2(Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. IDD1(10), IDD2(10) 3.0 4.2 mA 5 MHz logic signal freq. IDD1(90), IDD2(90) 27 39 mA 45 MHz logic signal freq. 0.01 10 µA 0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2 IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL Min –10 1.6 Test Conditions V 0.4 VDD1,VDD2 – 0.1 3.0 VDD1,VDD2 – 0.4 2.8 0.0 0.04 0.2 Rev. PrD | Page 5 of 23 0.1 0.1 0.4 V V V V V IOx = –20 µA, VIx = VIxH IOx = –4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL ADuM2400/ADuM2401/ADuM2402 Parameter SWITCHING SPECIFICATIONS ADuM240xARW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Propagation Delay Skew6 Channel-to-Channel Matching7 ADuM240xBRW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 ADuM240xCRW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10%–90%) Common Mode Transient Immunity at Logic High Output8 Common Mode Transient Immunity at Logic Low Output8 Refresh Rate Input Dynamic Supply Current, per Channel9 Output Dynamic Supply Current, per Channel9 Preliminary Technical Data Symbol Min Typ PW tPHL, tPLH PWD tPSK tPSKCD/OD 1 50 75 PW Max Unit Test Conditions 1000 ns Mbps ns ns ns ns CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels 100 40 50 50 tPSK tPSKCD 22 3 ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns CL = 15pF, CMOS signal levels 11.1 CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels tPHL, tPLH PWD 100 10 20 38 50 3 5 PW tPSK tPSKCD 16 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns CL = 15pF, CMOS signal levels tPHL, tPLH PWD 90 20 8.3 120 34 0.5 3 45 2 tPHZ, tPLH 6 8 ns CL = 15pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels VIx = VDD1/DD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 3 35 ns kV/µs |CML| 25 35 kV/µs 1.1 0.10 0.03 Mbps mA/Mbps mA/Mbps fr IDDI(D) IDDO(D) See Notes on next page. Rev. PrD| Page 6 of 23 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 NOTES 1 All voltages are relative to their respective ground. 2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20 . See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations. 3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating perchannel supply current for a given data rate. Rev. PrD | Page 7 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA=25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. Table 3. Parameter DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADuM2400, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 90 Mbps (CRWZ Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM2401, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 90 Mbps (CRWZ Grade Only) VDD1 Supply Current Symbol Min Typ Max Unit Test Conditions 0.50 0.26 0.53 0.31 mA mA 0.11 0.19 0.14 0.21 mA mA 2.2 1.2 2.8 1.9 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 0.5 0.9 0.9 1.4 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 8.6 4.5 10.6 6.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 1.4 2.6 2.0 3.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 76 42 100 65 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 11 21 15 25 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 1.8 1.0 2.4 1.6 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 0.7 1.2 1.2 1.8 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 7.1 3.7 9.0 5.4 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 2.2 4.1 3.0 5.0 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDDI(Q) IDDO(Q) IDD1(Q) IDD2(Q) IDD1(10) IDD2(10) IDD1(90) IDD2(90) IDD1(Q) IDD2(Q) IDD1(10) IDD2(10) IDD1(90) Rev. PrD| Page 8 of 23 Preliminary Technical Data Parameter 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM2402, Total Supply Current, Four Channels2 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ and CRWZ Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 90 Mbps (CRWZ Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation For All Models Input Currents Logic High Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS ADuM240xARW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Propagation Delay Skew6 Channel-to-Channel Matching7 ADuM240xBRW ADuM2400/ADuM2401/ADuM2402 Symbol Min Typ 62 34 Max 82 52 Unit mA mA Test Conditions 45 MHz logic signal freq. 45 MHz logic signal freq. 19 35 27 43 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 1.5 0.9 2.1 1.5 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 0.9 1.5 1.5 2.1 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 5.6 3.0 7.0 4.2 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 3.0 5.6 4.2 7.0 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 49 27 62 39 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 27 49 39 62 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 0.01 10 µA 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2 IDD2(90) IDD1(Q) IDD2(Q) IDD1(10) IDD2(10) IDD1(90) IDD2(90) IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH –10 2.0 1.6 V V VIL, VEL 0.8 0.4 VOAH, VOBH, VOCH, VODH VOAL,VOBL, VOCL, VODL VDD1/VDD2 – 0.1 VDD1/ VDD2 VDD1/VDD2 – 0.4 VDD1/ VDD2 – 0.2 0.0 0.1 0.04 0.1 0.2 0.4 PW tPHL, tPLH PWD tPSK tPSKCD/OD 1000 1 50 Rev. PrD | Page 9 of 23 70 100 40 50 50 V V V IOx = –20 µA, VIx = VIxH V IOx = –4 mA, VIx = VIxH V V V IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL ns Mbps ns ns ns ns CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels ADuM2400/ADuM2401/ADuM2402 Parameter Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH – tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 ADuM240xCRW Minimum Pulsewidth3 Maximum Data Rate4 Propagation Delay5 Pulsewidth Distortion, |tPLH-tPHL|5 Change Versus Temperature Propagation Delay Skew6 Channel-to-Channel Matching, Co-Directional Channels7 Channel-to-Channel Matching, Opposing-Directional Channels7 For All Models Output Disable Propagation Delay (High/Low to High Impedance) Output Enable Propagation Delay (High Impedance to High/Low) Output Rise/Fall Time (10-90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output8 Common-Mode Transient Immunity at Logic Low Output8 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current, per Channel9 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current, per Channel9 5 V/3 V Operation 3 V/5 V Operation Preliminary Technical Data Symbol PW tPSK tPSKCD 22 3 Unit ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns CL = 15pF, CMOS signal levels 11.1 CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels tPHL, tPLH PWD Min Typ Max 100 10 15 35 50 3 5 PW tPSK tPSKCD 14 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns CL = 15pF, CMOS signal levels tPHL, tPLH PWD 90 20 8.3 120 30 0.5 3 Test Conditions CL = 15pF,CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels CL = 15pF, CMOS signal levels 40 2 tPHZ, tPLH 6 8 ns CL = 15pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15pF, CMOS signal levels tR/tf CL = 15pF, CMOS signal levels |CMH| 25 3.0 2.5 35 ns ns kV/µs |CML| 25 35 kV/µs 1.2 1.1 Mbps Mbps 0.19 0.10 mA/Mbps mA/Mbps 0.03 0.05 mA/Mbps mA/Mbps fr IDDI(D) IDDI(D) See Notes on next page. Rev. PrD| Page 10 of 23 VIx = VDD1/DD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 NOTES 1 All voltages are relative to their respective ground. 2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations. 3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating perchannel supply current for a given data rate. Rev. PrD | Page 11 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 Symbol RI-O CI-O CI θjci θjco Min Typ 1012 2.2 4.0 33 28 Max Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside NOTES 1 Device considered a two-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION (PENDING) The ADuM240x will approved upon product release by the following organizations: Table 5. UL1 Recognized under 1577 component recognition program1 CSA Approved under CSA Component Acceptance Notice #5A Double insulation, 5000 V rms isolation voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms maximum working voltage Approved per IEC 60601-1 Reinforced insulation, 250 V rms maximum working voltage VDE2 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2):2003-012 Basic insulation, 848 V peak Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01, DIN EN 60950 (VDE 0805):2001-12; EN 60950:2000 Reinforced insulation, 565 V peak NOTES 1 In accordance with UL1577, each ADuM240x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 5 µA). 2 In accordance with DIN EN 60747-5-2, each ADuM240x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 7.45 min. Unit V rms mm Minimum External Tracking (Creepage) L(I02) 8.10 min. mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group 0.025 min. mm >175 V IIIa Rev. PrD| Page 12 of 23 Conditions 1 minute duration. Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation distance through insulation. DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89, Table 1). Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS (PENDING) Table 7. Description Installation classification per DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 600 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1) VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5p C After Input and/or Safety Test Subgroup 2/3) VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5p C Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Maximum value allowed in the event of a failure, also see Thermal Derating Curve, Figure 4) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS, VIO = 500 V Symbol Characteristic Unit VIORM VPR I–IV I–III 40/105/21 2 848 1590 V peak V peak 1356 V peak 1018 V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. "*" marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage. 350 RECOMMENDED OPERATING CONDITIONS Table 8. Parameter Operating Temperature Supply Voltages1 Input Signal Rise and Fall Times 250 SIDE #2 200 SIDE #1 100 50 0 0 50 100 150 CASE TEMPERATURE (°C) Symbol TA VDD1, VDD 2 Min –40 2.7 Max +105 5.5 1.0 Unit °C V ms NOTE 1 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section on page 19 for information on immunity to external magnetic fields. 150 200 03787-0-003 SAFETY-LIMITING CURRENT (mA) 300 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Rev. PrD | Page 13 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Storage Temperature Ambient Operating Temperature Supply Voltages1 Input Voltage1, 2 Output Voltage1, 2 Average Output Current, Per Pin3 Side 1 Side 2 Common-Mode Transients4 Symbol TST TA VDD1, VDD2 VIA, VIB, VIC, VID, VE1,VE2 VOA, VOB, VOC, VOD Min –65 –40 –0.5 –0.5 –0.5 Max 150 105 7.0 VDDI + 0.5 VDDO + 0.5 Unit °C °C V V V IO1 IO2 –18 –22 –100 18 22 +100 mA mA kV/µs NOTES 1 All voltages are relative to their respective ground. 2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient temperature = 25°C, unless otherwise noted. Table 10. Truth Table (Positive Logic) VIX Input1 H L X X X X VEX Input H or NC H or NC L H or NC L X VDDI State1 Powered Powered Powered Unpowered Unpowered Powered VDDO State1 Powered Powered Powered Powered Powered Unpowered VOX Output1 Note H L Z H Outputs returns to input state within 1 µs of VDDI power restoration. Z Indeterminate Outputs returns to input state within 1 µs of VDDO power restoration if VEX state is H or NC. Outputs returns to high impedance state within 8 ns of VDDO power restoration if VEX state is L. NOTE 1 VIX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. Rev. PrD| Page 14 of 23 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONS VDD1 1 16 VDD2 2 *GND1 15 GND2* VIA 3 ADuM2400 VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM2401 VDD1 11 VOD VOD 6 11 VID VOD NC 7 10 VE2 VE1 7 10 VE2 VE1 *GND1 8 9 GND2* *GND1 8 9 GND2* 03786-0-005 Figure 5. ADuM2400 Pin Configuration NC = NO CONNECT 16 VDD2 GND2* *GND 3 ADuM2402 VIA 14 VOA TOP VIEW 4 VIB (Not to Scale) 13 VOB 5 VOC 12 VIC VID 6 NC = NO CONNECT 2 1 14 VOA TOP VIEW VIB 4 (Not to Scale) 13 VOB VIC 5 12 VOC 14 VOA TOP VIEW VIB 4 (Not to Scale) 13 VOB VIC 5 12 VOC 1 *GND1 03786-0-006 Figure 6. ADuM2401 Pin Configuration 6 7 8 15 11 VID 10 VE2 9 GND2* NC = NO CONNECT 03786-0-007 Figure 7. ADuM2402 Pin Configuration * Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended. Output enable Pin 10 on the ADuM2400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM2401/ADuM2402 may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM2401 and ADuM2402) and Pin 10 (for all models) to an external logic high or low is recommended. Rev. PrD | Page 15 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data PIN FUNCTION DESCRIPTIONS Table 11. ADuM2400 Pin Function Descriptions Table 13. ADuM2402 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VIC VID NC Function Supply voltage for isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1. Logic input A. Logic input B. Logic input C. Logic input D. No Connect. Pin No. 1 2 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VOC VOD VE1 8 9 10 GND1 GND2 VE2 8 9 10 GND1 GND2 VE2 11 12 13 14 15 16 VOD VOC VOB VOA GND2 VDD2 Ground 1. Ground reference for isolator Side 1. Ground 2. Ground reference for isolator Side 2. Output enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. Logic output D. Logic output C. Logic output B. Logic output A. Ground 2. Ground reference for isolator Side 2. Supply voltage for isolator Side 2, 2.7 V to 5.5 V. 11 12 13 14 15 16 VID VIC VOB VOA GND2 VDD2 Table 12. ADuM2401 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VIC VOD VE1 8 9 10 GND1 GND2 VE2 11 12 13 14 15 16 VID VOC VOB VOA GND2 VDD2 Function Supply voltage for isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1. Logic input A. Logic input B. Logic input C. Logic output D. Output enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low. Ground 1. Ground reference for isolator Side 1. Ground 2. Ground reference for isolator Side 2. Output enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled when VE2 is low. Logic input D. Logic output C. Logic output B. Logic output A. Ground 2. Ground reference for isolator Side 2. Supply voltage for isolator Side 1, 2.7 V to 5.5 V. Rev. PrD| Page 16 of 23 Function Supply voltage for isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for isolator Side 1. Logic input A. Logic input B. Logic output C. Logic output D. Output enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs are disabled when VE1 is low. Ground 1. Ground reference for isolator Side 1. Ground 2. Ground reference for isolator Side 2. Output enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs are disabled when VE2 is low. Logic input D. Logic input C. Logic output B. Logic output A. Ground 2. Ground reference for isolator Side 2. Supply voltage for isolator Side 2, 2.7 V to 5.5 V. Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 TYPICAL PERFORMANCE CHARACTERISTICS 20 80 15 60 CURRENT (mA) CURRENT/CHANNEL (mA) 70 10 5V 50 40 5V 30 3V 3V 20 5 0 0 20 40 60 DATA RATE (Mbps) 80 100 0 0 40 60 DATA RATE (Mbps) 80 100 Figure 11. Typical ADuM2400 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation Figure 8. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation 20 6 5 15 4 CURRENT (mA) 3 5V 2 10 10 5V 3V 3V 5 04407-0-012 1 0 0 20 40 60 DATA RATE (Mbps) 80 100 0 0 20 40 60 DATA RATE (Mbps) 80 100 04407-0-015 CURRENT/CHANNEL (mA) 20 04407-0-014 04407-0-011 10 Figure 12. Typical ADuM2400 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Figure 9. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load) 10 50 30 CURRENT (mA) 25 6 4 5V 20 15 5V 10 3V 2 3V 0 0 20 40 60 DATA RATE (Mbps) 80 100 Figure 10. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load) Rev. PrD | Page 17 of 23 0 0 20 40 60 DATA RATE (Mbps) 80 100 Figure 13. Typical ADuM2401 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation 04407-0-016 5 04407-0-013 CURRENT/CHANNEL (mA) 8 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data 40 40 35 PROPAGATION DELAY (ns) CURRENT (mA) 30 25 20 5V 15 3V 10 3V 35 30 5V 0 20 40 60 DATA RATE (Mbps) 80 100 50 45 40 30 25 20 5V 15 3V 10 5 20 40 60 DATA RATE (Mbps) 80 100 04407-0-018 CURRENT (mA) 35 0 –25 0 25 50 TEMPERATURE (°C) 75 Figure 16. Propagation Delay vs. Temperature, C Grade. Figure 14. Typical ADuM2401 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation 0 25 –50 Figure 15. Typical ADuM2402 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. PrD| Page 18 of 23 100 03786-0-023 0 04407-0-017 5 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 APPLICATION INFORMATION PC BOARD LAYOUT VDD1 GND1 VIA VIB VIC/OC VID/OD VE1 GND1 VDD2 GND2 VOA VOB VOC/IC VOD/ID VE2 GND2 03786-0-019 The ADuM240x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 17). Bypass capacitors are most conveniently connected between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for VDD2. The capacitor value should be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pins 1 and 8 and between Pins 9 and 16 should also be considered unless the ground pair on each package side are connected close to the package. In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage. V = (–dβ/dt)∑∏rn2; n = 1, 2,…, N Propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high. β is magnetic flux density (gauss) N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). 03786-0-020 OUTPUT (VOX) where: 50% tPHL 50% Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is therefore either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than 2 µs, a periodic set of "refresh" pulses indicative of the correct input state are sent to ensure "dc correctness" at the output. If the decoder receives no pulses for more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the “receiving” coil is given by: PROPAGATION DELAY-RELATED PARAMETERS tPLH DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The limitation on the ADuM240x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s “receiving” coil is sufficiently large to either falsely set or reset the decoder. The analysis below defines the conditions under which this may occur. The 3 V operating condition of the ADuM240x is examined as it represents the most susceptible mode of operation. Figure 17. Recommended Printed Circuit Board Layout INPUT (VIX) Propagation delay skew refers to the maximum amount the propagation delay differs among multiple ADuM240x components operated under the same conditions. Given the geometry of the receiving coil in the ADuM240x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in below in Figure 19. Figure 18. Propagation Delay Parameters Pulsewidth distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single ADuM240x component. Rev. PrD | Page 19 of 23 ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. 10 1 POWER CONSUMPTION The supply current at a given channel of the ADuM240x isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load. 0.1 0.01 10k 100k 10M 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 03786-0-021 For each input channel, the supply current is given by: 0.001 1k Figure 19. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and will not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst case polarity) it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM240x transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM240x is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM240x to affect the component’s operation. DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 03786-0-022 MAXIMUM ALLOWABLE CURRENT (kA) 1000 IDDI = IDDI(Q) f ≤ 0.5fr IDDI = IDDI(D) × (2f – fr) + IDDI(Q) f > 0.5fr For each output channel, the supply current is given by: IDDO = IDDO(Q) f ≤ 0.5fr IDDO = (IDDO(D) + (0.5 x 10-3 × CLVDDO) × (2f – fr) + IDDO(Q) f > 0.5fr where: IDDI(D), IDDO(D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI(Q), IDDO(Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides perchannel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 14 provide total IDD1 and IDD2 supply current as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations. Figure 20. Maximum Allowable Current for Various Current-to-ADuM240x Spacings Rev. PrD| Page 20 of 23 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1.27 (0.0500) BSC 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 8 1 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) × 45° 0.25 (0.0098) 8° 0.33 (0.0130) 0° 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 21. 16-Lead Standard Small Outline Package [SOIC]— Wide Body (RW-16) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Number of Number of Maximum Maximum Inputs, Data Rate Propagation Inputs, Delay, 5 V (ns) VDD2 Side (Mbps) VDD1 Side Maximum Pulsewidth Distortion (ns) Channel-toChannel Matching, Co-Directional Channels (ns) Package Description Model ADuM2400ARWZ* 4 0 1 100 40 40 ADuM2400BRWZ* 4 0 10 50 3 3 ADuM2400CRWZ* 4 0 100 32 2 2 ADuM2401ARWZ* 3 1 1 100 40 40 ADuM2401BRWZ* 3 1 10 50 3 3 ADuM2401CRWZ* 3 1 100 32 2 2 ADuM2402ARWZ* 2 2 1 100 40 40 ADuM2402BRWZ* 2 2 10 50 3 3 ADuM2402CRWZ* 2 2 100 32 2 2 *Tape and Reel is available. The addition of an “-RL” suffix designates a 13” (1000 units) tape and reel option. Rev. PrD | Page 21 of 23 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free 16-Lead Wide Body SOIC, Pb-Free ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data NOTES Rev. PrD| Page 22 of 23 Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05007-0-10/04(PrD) Rev. PrD | Page 23 of 23