19-5933; Rev 0; 6/11 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC General Description Features The DS3911 is a quad, 10-bit delta-sigma output, nonvolatile (NV) controller that features an on-chip temperature sensor and associated analog-to-digital converter (ADC). The integrated temperature sensor indexes the up to 2NC resolution NV lookup tables (LUTs), encompassing a -40NC to +100NC temperature range. The LUT directly drives the delta-sigma digital-to-analog converter (DAC) outputs. This flexible LUT-based architecture allows the device to provide a temperature-compensated DAC output with arbitrary slope. Programming is accomplished by an I2C-compatible interface that operates at speeds of up to 400kHz. SFour 10-Bit Delta-Sigma Outputs SOn-Chip Temperature Sensor and ADC SFour Temperature-Indexed LUTs, Up to 2NC Resolution SI2C-Compatible Serial Interface SAddress Pins Allow Up to Four DS3911s to Share the Same I2C Bus S2.8V to 5.5V Digital Supply S-40NC to +100NC Operating Temperature Range S3mm x 5mm, 14-Pin TDFN Package Applications Ordering Information appears at end of data sheet. Active Optical Cables For related parts and recommended products to use with this part, refer to www.maxim-ic.com/DS3911.related. Optical Transceivers Linear and Nonlinear Compensation Instrumentation and Industrial Controls Typical Operating Circuit 3.3V VCC RPU I2C MASTER DS3911 SDA SCL A1 A0 GND I2C SLAVE TEMP SENSOR VREF 3.3V VCC 0.1µF 3.3V 100Ω VREF GND EEPROM LUT 10-BIT DAC DAC0 EEPROM LUT 10-BIT DAC DAC1 EEPROM LUT 10-BIT DAC DAC2 EEPROM LUT 10-BIT DAC DAC3 0.1µF 2.5V R1 R2 C1 C2 MODSET APCSET LASER DRIVER MODSET APCSET LASER DRIVER MODSET APCSET LASER DRIVER MODSET APCSET LASER DRIVER ����������������������������������������������������������������� Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC ABSOLUTE MAXIMUM RATINGS Voltage Range on SDA, SCL, and VCC Relative to GND.................................................-0.3V to +6.0V Voltage Range on DAC0, DAC1, DAC2, DAC3, VREF, A0, A1 Relative to GND............... -0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70NC) TDFN (derate 21.7mW/NC above +70NC)................1739.1mW Operating Temperature Range......................... -40NC to +100NC Programming Temperature Range..................... -40NC to +85NC Storage Temperature Range............................. -55NC to +125NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +100NC, unless otherwise noted.) PARAMETER SYMBOL Supply Voltage VCC Input Logic 1 (SCL, SDA, A0, A1) VIH Input Logic 0 (SCL, SDA, A0, A1) VIL CONDITIONS (Note 1) MIN TYP 2.8 0.7 x VCC -0.3 MAX UNITS 5.5 V VCC + 0.3 V +0.3 x VCC V DC ELECTRICAL CHARACTERISTICS (VCC = +2.8V to +5.5V, TA = -40NC to +100NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Input Leakage (SDA, SCL, A0, A1) IL VCC Supply Current ICC (Note 2) Low-Level Output Voltage (SDA) VOL 3mA sink current TYP -1 I/O Capacitance CI/O Power-On Recall Voltage VPOR (Note 3) tD (Note 4) Power-Up Recall Delay MIN 0.9 0 5 1.6 MAX UNITS +1 FA 2.0 mA 0.4 V 10 pF 2.7 V 5 ms MAX UNITS DAC ELECTRICAL CHARACTERISTICS (VCC = +2.8V to +5.5V, TA = -40NC to +100NC, unless otherwise noted.) PARAMETER Delta-Sigma Clock Frequency Reference Voltage Input (VREF) SYMBOL CONDITIONS MIN fDS VREF TYP 2.1 Minimum 0.1FF to GND Output Range 2.4 VCC V 0 VREF V 10 Bits 100 I See the Delta-Sigma DAC Output and Control section for details Output Resolution Output Impedance RDS MHz 35 ����������������������������������������������������������������� Maxim Integrated Products 2 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC TEMPERATURE SENSOR CHARACTERISTICS (VCC = +2.8V to +5.5V, TA = -40NC to +100NC, unless otherwise noted.) PARAMETER SYMBOL Temperature Error CONDITIONS MIN TYP TA = -40NC to +100NC Update Rate (Temperature and Supply Conversion Time) tFRAME MAX UNITS Q5 NC 16 ms ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.8V to +5.5V, TA = -40NC to +100NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Resolution LSB Full-scale voltage of 6.5536V 800 Input/Supply Accuracy ACC At factory setting 0.25 1 %FS Input Supply Offset VOS (Note 5) 0 5 LSB Update Rate (Temperature and Supply Conversion Time) tFRAME FV 16 ms I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.8V to +5.5V, TA = -40NC to +100NC, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (See Figure 1.) PARAMETER SYMBOL CONDITIONS (Note 6) MIN TYP 0 MAX UNITS 400 kHz SCL Clock Frequency fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs Hold Time (Repeated) START Condition tHD:STA 0.6 Fs Low Period of SCL tLOW 1.3 Fs High Period of SCL tHIGH 0.6 Fs Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 0.9 ns START Set-Up Time tSU:STA 0.6 Fs Fs SDA and SCL Rise Time tR (Note 7) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 7) 20 + 0.1CB 300 ns STOP Set-Up Time tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 7) EEPROM Write Time tW (Note 8) Fs 10 400 pF 20 ms A0, A1 Setup Time tSU:A Before START 0.6 Fs A0, A1 Hold Time tHD:A After STOP 0.6 Fs Input Capacitance on A0, A1, SDA, or SCL CI Startup time tST 5 10 pF 2 ms ����������������������������������������������������������������� Maxim Integrated Products 3 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.8V to +5.5V, unless otherwise noted.) PARAMETER SYMBOL EEPROM Write Cycles (Note 9) CONDITIONS MIN TA = +85NC 10,000 TA = +25NC 50,000 TYP MAX UNITS Writes Note 1: All voltages are referenced to ground. Currents entering the device are specified as positive, and currents exiting the device are specified as negative. Note 2: ICC is specified with SCL = SDA = VCC, and EN bit = 1. Typical values are at VCC = 3.3V and TA = +25NC. Note 3: This is the minimum VCC voltage that causes NV memory to be recalled. Note 4: This is the time from VCC > VPOR until initial memory recall is complete. Note 5: Guaranteed by design. Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 7: CB = total capacitance of one bus line in pF. Note 8: EEPROM write time begins after a STOP condition occurs. Note 9: Guaranteed by characterization. SDA tBUF tF tLOW tHD:STA tSP SCL tHD:STA tHIGH tR tHD:DAT STOP START tSU:STA tSU:STO tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 1. I2C Timing Diagram ����������������������������������������������������������������� Maxim Integrated Products 4 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 1.8 1.6 0.4 0.3 VDD = 3.3V 0.9 0.2 1.2 TA = +25°C 0.1 LSB 1.0 0 0.8 -0.1 0.6 -0.2 0.4 -0.3 0.6 0.2 -0.4 0.5 0 0.7 -20 0 20 40 60 80 200 0 400 600 800 1000 TEMPERATURE (°C) VDD (V) DAC VALUE INL vs. OUTPUT CODE (CURRENT SINK FILTER) FILTERED DAC0 VOLTAGE VARIATION FROM IDEAL vs. DAC2 CODE SWEEP (BOTH VOLTAGE OUTPUT FILTERS) DAC1 DEVIATION FROM AVERAGE CURRENT vs. DAC3 CODE SWEEP (BOTH CURRENT SINK FILTERS) 600 800 DAC0 VALUE = 0000h 400 200 0 -200 -400 DAC0 VALUE = FFC0h -600 -800 -1000 -1200 1000 600 1.25V SOURCE CURRENT (nA) 1000 800 600 400 DAC1 VALUE = 0000h 200 0 -200 DAC0 VALUE = 8000h DAC1 VALUE = FFC0h -400 DAC0 VALUE = 8000h -600 200 0 DAC VALUE 400 600 800 1000 0 200 DAC2 VALUE 0.8 1.0 0.9 0.8 0.7 0.6 0.6 VREF (mA) 0.7 0.5 0.4 800 1000 VREF CURRENT vs. DAC1 CODE SWEEP (CURRENT SINK FILTER) DS3911 toc07 0.9 600 DAC3 VALUE VREF CURRENT vs. DAC0 CODE SWEEP (VOLTAGE OUTPUT FILTER) 1.0 400 DS3911 toc08 400 VREF (mA) 200 1200 DS3911 toc05 DS3911 toc04 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 0 -0.5 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 100 120 VOLTAGE VARIATION FROM IDEAL (µV) -40 DS3911 toc06 1.0 0.8 LSB 0.5 1.4 IDD (mA) IDD (mA) 1.1 INL vs. OUTPUT CODE (VOLTAGE OUTPUT FILTER) DS3911 toc02 DS3911 toc01 2.0 DS3911 toc03 SUPPLY CURRENT vs. TEMPERATURE 1.3 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0 200 400 600 DAC0 VALUE 800 1000 0 200 400 600 800 1000 DAC1 VALUE ����������������������������������������������������������������� Maxim Integrated Products 5 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Multiple Device Connection Diagram 3.3V RPU DS3911 DS3911 SDA SCL TEMP SENSOR 3.3V I2C ADDRESS A1 A0 I2C SLAVE TEMP SENSOR 3.3V LUT LUT EEPROM 63Ω VREF 10-BIT DAC 10-BIT DAC 10-BIT DAC BIASSET MODSET LASER DRIVER LASER DRIVER LUT LUT LUT 10-BIT DAC 10-BIT DAC 10-BIT DAC 10-BIT DAC VREF 0.1µF 10-BIT DAC LUT MODSET LUT BIASSET EEPROM LUT VCC 3.3V MODSET 0.1µF BIASSET VCC MODSET I 2C ADDRESS I2C SLAVE A1 A0 BIASSET I2C MASTER SDA SCL 2.5V LASER DRIVER LASER DRIVER ����������������������������������������������������������������� Maxim Integrated Products 6 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Pin Configuration TOP VIEW DAC0 1 DAC1 2 VREF 3 GND 4 DAC2 5 DAC3 6 N.C. 7 + DS3911 EP 14 VCC 13 SCL 12 SDA 11 A0 10 A1 9 GND 8 N.C. TDFN (3mm x 5mm) Pin Description PIN NAME TYPE FUNCTION 1 DAC0 Output Delta-Sigma DAC Output 2 DAC1 Output Delta-Sigma DAC Output 3 VREF Input 4 GND Supply Ground 5 DAC2 Output Delta-Sigma DAC Output 6 DAC3 Output Delta-Sigma DAC Output DAC Reference Voltage Input 7, 8 N.C. — 9 GND Supply 10 A1 Input I2C Slave Address Input 11 A0 Input I2C Slave Address Input 12 SDA I/O 13 SCL Input 14 VCC Supply — EP — No Internal Connection Ground 2-Wire Serial Data 2-Wire Clock Positive Supply Exposed Pad. Connect to ground. ����������������������������������������������������������������� Maxim Integrated Products 7 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Detailed Description The DS3911 operates in one of two modes: lookup table (LUT) mode or digital-to-analog converter (DAC) mode. In LUT mode, the DAC’s output is controlled as a function of the temperature measured by the device’s internal temperature sensor and the pulse-density modulation profile stored in the associated DAC’s LUT. In DAC mode, the DAC’s output is controlled by the specific DAC’s DAC VALUE register (DAC0 VALUE, DAC1 VALUE, DAC2 VALUE, and DAC3 VALUE) using the I2C interface. Detailed descriptions of these modes as well as additional device features are discussed in subsequent sections. 1kΩ 1kΩ DAC VOLTAGE OUTPUT 0.1µF 0.1µF 1kΩ DAC CURRENT SINK 0.1µF 0.1µF Figure 2 shows two recommended filters. These external RC filter components are chosen to greatly reduce the output ripple while maintaining the desired response time. Using resistors smaller than the recommended values can degrade the output accuracy. The device’s delta-sigma outputs are 10 bits. For illustrative purposes, a 3-bit example is provided. Figure 3 shows each possible output of this 3-bit delta-sigma DAC. DS3911 1kΩ Delta-Sigma DAC Output and Control Four delta-sigma DAC outputs are provided, DAC0 to DAC3. With the addition of an external RC filter, these outputs provide four 10-bit resolution-analog outputs with the full-scale range set by the input VREF pin. Each output is either manually controlled or controlled using a temperature-indexed LUT. A delta-sigma converter produces a digital output using pulse-density modulation. It provides much lower output ripple than a standard digital PWM output, given the same clock rate and filter components. 2kΩ DS3911 The reference input voltage, VREF, is the supply voltage for the output buffer of all DACs. The power supply connected to VREF must be able to support the edge-rate requirements of the delta-sigma outputs. In a typical application, a 0.1FF capacitor should be connected between the VREF and GND pins. Figure 2. Recommended RC Filter for DAC Outputs DAC VALUE REGISTER SETTING (3-BIT EXAMPLE) 0 1 2 3 4 5 6 7 DAC OUPUT Figure 3. 3-Bit (8-Position) Delta-Sigma Example ����������������������������������������������������������������� Maxim Integrated Products 8 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC DAC Power-On Values Each 10-bit DAC is controlled directly by the value in its corresponding DAC VALUE register. Each DAC also has a DAC POR register that contains the power-on-reset (POR) value for the associated DAC, along with two control bits: enable (EN) and polarity (POL). See the Lower Memory Register Descriptions section for complete lower memory descriptions. Lookup Table Mode The device has four nonvolatile memory tables, one for each of the four DACs. Each memory table is associated with an individual DAC as follows: Table 04h (DAC0), Table 05h (DAC1), Table 06h (DAC2), Table 07h (DAC3), and selected by setting the table select bits, TS[3:0], in the CTRL register. Each DAC memory table consists of a DAC LUT table (addresses 80h–AFh) (DAC0 LUT, DAC1 LUT, DAC2 LUT, and DAC3 LUT) and a DAC OFFSET table (addresses F8h–FFh) (DAC0 OFFSET, DAC1 OFFSET, DAC2 OFFSET, and DAC3 OFFSET). Because these four memory tables all share the same address and register mapping, the TS[3:0] bits must be used to select among them. The DAC POR (DAC0 POR, DAC1 POR, DAC2 POR, and DAC3 POR) registers are shadowed EEPROM with functionality controlled by the shadow EEPROM bit (SEE). If the SEE bit is high, the DAC POR registers function as SRAM only. If the SEE bit is low, the registers are shadowed EEPROM and EEPROM write timing, tW, must be observed. Each LUT address represents as little as a 2N change in temperature. Table 1 shows the full temperature-toregister mapping. On power-up, the initial DAC settings are always transferred from the DAC POR registers to the corresponding DAC VALUE registers. The first DAC OFFSET address corresponds to 32N of temperature. After this, every 16N of temperature converts into one DAC OFFSET address slot. Table 2 shows the full temperature-to-register mapping. Manual Control Mode On power-up, the device starts performing temperature conversions and the DAC VALUE register whose corresponding EN bit is set is updated by the LUT controller as described in the Lookup Table Mode section. Clearing the EN bit enables I2C writes to the corresponding DAC VALUE and disables LUT controller updates. This allows the individual DACs whose EN bit is cleared to be controlled by writing the corresponding DAC VALUE register directly. The TINDEX register points to a LUT address slot. The TINDEX register can operate in two modes, as defined by the AEN bit. When the AEN bit is cleared, I2C writes to the TINDEX register are enabled, and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based on the user-selected index. The TINDEX register directly addresses the LUT Table 1. LUT Temperature Mapping ROW (HEX) BYTE 0 BYTE 1 BYTE 2 80h < -36N -36N -32N BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 -24N -20N -16N -12N 4NC LUT -28N 88h -8N -4N 0N +4N +8N +12N +16N +20N 90h +24N +28N +32N +36N +40N +44N +48N +52N +68N +70N 2NC LUT 98h +56N +58N +60N +62N +64N +66N A0h +72N +74N +76N +78N +80N +82N +84N +86N A8h +88N +90N +92N +94N +96N +98N +100N R +102N Table 2. Offset Temperature Mapping ROW (HEX) BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 F8h < -8N -8N +8N +24N +40N +56N +72N R +88N ����������������������������������������������������������������� Maxim Integrated Products 9 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC memory locations by dropping TINDEX and forcing it high. When AEN = 0, any address between 80h and FFh can be addressed. To get known results in the DAC VALUE register, TINDEX should be kept between 80h and AFh. The device monitors the internal temperature by repeatedly polling the temperature sensor’s result at a rate of tFRAME. Each cycle, for the DAC whose corresponding EN bit is set, the device reads the internal temperature once, and, based on that temperature, calculates the TINDEX register. The TINDEX value corresponds directly to the LUT memory address for the given temperature ranges. The DAC OFFSET address is calculated based on the TINDEX value so only one pointer is necessary. These two locations provide the values that eventually become the 10-bit DAC input, DAC VALUE. This data that gets loaded into the DAC VALUE register is a math function of the temperature-indexed LUT value and the temperature-indexed OFFSET value, as follows: DAC[9:0] = LUT Setting + 4 x OFFSET Setting where the DAC[9:0] DAC control value is left-justified in the 16-bit DAC VALUE register. DAC VALUE[15:0] = DAC[9:0] x 64 Example Calculation for DAC1: Assumptions: 1) Temperature is 43NC. 2) DAC1 OFFSET index associated with 43NC is memory table location FCh and contains data = 2Ah. 3) DAC1 LUT index associated with 43NC is memory table location 94h and contains data = 7Bh. DAC1 = 7Bh + 4 x 2Ah = 123h = 291 DAC1 VALUE = 291 x 64 Note: Loss of information occurs if the result of the DAC VALUE math function described above is greater than 10 bits. It is important to set the DAC VALUE and DAC OFFSET values to ensure this overflow does not occur. The eight DAC OFFSET registers can be independently set to achieve any desired temperature coefficient (tempco) on its associated DAC. Figure 4 demonstrates DAC OFFSET LUTs EIGHT REGISTERS PER DAC EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO. FDh DELTA-SIGMA DACs 767 FCh FBh 511 F9h F8h 255 0 DAC LUT BITS 7:0 -40°C FAh DAC LUT BITS 7:0 -8°C DAC LUT BITS 7:0 +8°C DAC LUT BITS 7:0 DAC LUT BITS 7:0 DAC LUT BITS 7:0 FFh FEh DAC LUT BITS 7:0 1023 DAC LUT BITS 7:0 EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE AND NEGATVE TEMPCO. 767 DELTA-SIGMA DACs 1023 DAC OFFSET LUTs EIGHT REGISTERS PER DAC OFFSET MEMORY LOCATIONS FOR THE GIVEN TEMPERATURE +24°C +40°C +56°C +70°C +88°C +104°C FBh FAh F9h 511 F8h 255 0 DAC LUT BITS 7:0 -40°C DAC LUT BITS 7:0 -8°C DAC LUT BITS 7:0 +8°C DAC LUT BITS 7:0 FCh DAC LUT BITS 7:0 FDh DAC LUT BITS 7:0 FEh DAC LUT BITS 7:0 FFh DAC LUT BITS 7:0 +24°C +40°C +56°C +70°C +88°C +104°C Figure 4. DAC OFFSET LUT Examples ���������������������������������������������������������������� Maxim Integrated Products 10 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC DONETEMP bit located in the CTRL register indicates whether a temperature conversion has been completed since the bit was last cleared. 9D MEMORY LOCATION 9C DECREASING TEMPERATURE 9B 9A INCREASING TEMPERATURE 99 98 1°C HYSTERESIS WINDOW 56 58 60 62 64 66 TEMPERATURE (°C) Slave Address Byte and Address Pins Figure 5. LUT Hysteresis LSB MSB 1 0 1 1 0 A1 SLAVE ADDRESS* Supply Voltage Monitoring The device also features an internal 13-bit supply voltage (VCC) monitor. A left-justified value of the supply voltage measurement can be read over I2C at memory addresses 06h–07h. To calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the LSB as shown in the Analog Voltage Monitoring Characteristics electrical specifications table. The DONEVCC bit located in the CTRL register indicates whether a VCC conversion has been completed since the bit was last cleared. A0 R/W READ/WRITE BIT *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1. Figure 6. DS3911 Slave Address Byte The slave address byte consists of a 7-bit slave address plus a R/W bit, as shown in Figure 6. The device’s slave address is determined by the state of the A0 and A1 address pins. These pins allow up to four devices to reside on the same I2C bus. Address pins connected to GND result in a 0 in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a 1 in the corresponding bit positions. For example, the device’s slave address byte is B0h when A0 and A1 are grounded. See the I2C Serial Interface section for more information. I2C Serial Interface how a positive and negative tempco can be achieved by adjusting DAC OFFSET values. The DACs are updated after each temperature conversion. The LUT features 1NC ������������������������������ hysteresis to prevent chattering if the measured temperature falls on the boundary between two windows (Figure 5). This 1NC hysteresis is implemented in the TINDEX register value calculation by adding 1NC to temperature changes of negative slope. Temperature Conversion and Supply Voltage Monitoring Temperature Conversion The device features an internal 12-bit temperature sensor that can drive the LUT and provide a measurement of the ambient temperature over I2C by reading the value stored in memory addresses 04h–05h. The sensor is functional over the entire operating temperature range, and the results are stored in signed two’s-complement format with a 1/16NC resolution. See the Lower Memory, Register 04h–05h: TEMP VALUE section for the temperature sensor’s bit weights. The I2C Definitions The following terminology is commonly used to describe I2C data transfers. See the timing diagram (Figure 1) and the I2C AC Electrical Characteristics table for additional information. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. ���������������������������������������������������������������� Maxim Integrated Products 11 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledge (ACK and NACK): An acknowledge (ACK) or not-acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one (done by releasing SDA) during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data (see Figure 7). A NACK is used to terminate a read sequence, or used as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The device’s slave address is determined by the state of the A0 and A1 address pins as shown in Figure 6. Address pins connected to GND result in a 0 in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a 1 in the corresponding bit positions. When the R/W bit is 0 (such as in B0h), the master is indicating it will write data to the slave. If R/W is set to 1 (B1h in this case), the master is indicating it wants to read from the slave. If an incorrect (nonmatching) slave address is written, the device assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory Address: During an I2C write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication See Figure 7 for I2C communication examples. Writing a Single Byte to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. The master must read the slave’s acknowledgement during all byte write operations. When writing to the device, the DAC’s output adjusts to the new setting once it has acknowledged the new data that is being written, and writes to the EEPROM are written following the STOP condition at the end of the write command. Writing Multiple Bytes to a Slave: I2C write operations of multiple bytes can also be performed. During a single write sequence, up to 8 bytes in one page ���������������������������������������������������������������� Maxim Integrated Products 12 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC can be written at one time. If more than 8 bytes are transmitted in the sequence, only the last 8 transmitted bytes are stored. After the last physical memory location in a particular page (8-byte page write), the address counter automatically wraps back to the first location in the same page for subsequent byte write operations. with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the next method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Recall that the master must NACK the last byte to inform the slave that no additional bytes are to be read. See Figure 7 for I2C communication examples. Acknowledge Polling: Any time a EEPROM byte is written, the device requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the device, which allows communication to continue as soon as the device is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it must NACK to indicate the end of the transfer and generates a STOP condition. During a single read sequence of multiple Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 0 1 1 0 SLAVE ADDRESS* A1 A0 R/W MSB SLAVE ACK READ/ WRITE b7 MSB LSB b6 b5 b4 b3 b2 b1 SLAVE ACK b0 b7 LSB b6 REGISTER ADDRESS b5 b4 b3 b2 b1 b0 SLAVE ACK STOP DATA *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1. EXAMPLE I2C TRANSACTIONS WITH B0h AS THE DEVICE ADDRESS (WHEN A0 AND A1 ARE CONNECTED TO GND) B0h A) SINGLE-BYTE WRITE -WRITE CONTROL REGISTER (00h) START 1 0 1 1 0 0 0 0 B) SINGLE-BYTE READ -READ MODE REGISTER (01h) START 1 0 1 1 0 0 0 0 B0h C) 2-BYTE WRITE -WRITE LUT VALUES FOR REGISTERS (80h−81h) D) 2-BYTE READ -READ TEMPERATURE REGISTER (04h−05h) 00h SLAVE SLAVE 0 0 0 0 0 0 0 0 ACK ACK DATA INTO 00h 01h SLAVE SLAVE 0 0 0 0 0 0 0 1 ACK ACK REPEATED START B0h 80h START 1 0 1 1 0 0 0 0 SLAVE 1 0 0 0 0 0 0 0 SLAVE ACK ACK B0h START 1 0 1 1 0 0 0 0 04h SLAVE SLAVE ACK 0 0 0 0 0 1 0 0 ACK DATA SLAVE ACK STOP B1h DATA 10110001 DATA DATA INTO 80h SLAVE ACK MASTER NACK STOP MASTER ACK DATA IN 05h DATA SLAVE ACK DATA INTO 81h B1h REPEATED START DATA IN 01h 10110001 SLAVE ACK STOP DATA SLAVE ACK DATA IN 04h DATA MASTER NACK STOP Figure 7. I2C Communication Examples ���������������������������������������������������������������� Maxim Integrated Products 13 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC bytes, after the last address counter position of FFh is accessed, the address counter automatically wraps back to the first location, 00h. Read operations can continue indefinitely. The Lower Memory is addressed from 00h–7Fh. Lower Memory contains temperature reading, VCC reading, status bits, control registers, table select bits, and all four DAC VALUE and DAC POR registers. I2C LUT Lockout 2 Both the I C port and the LUT controller have access to The Upper Memory consists of the following four memory tables. The table select bits, TS[3:0], determine which table is currently accessible through I2C at memory location 80h–FFh. the LUTs. To prevent bus/data contention, the LUT controller goes into a wait state instead of accessing the LUT if the I2C port is active. Register updates and memory access are briefly described below. • After a voltage or temperature conversion completes or the TINDEX register is calculated, the results are loaded into a shadow SRAM for the associated register by a backdoor that is not seen by the I2C port. The value is pushed forward to the SRAM cell seen by the I2C port at a later state. It is not pushed if the I2C port is active. • After TINDEX is calculated and loaded into the shadow SRAM, the LUT controller goes into a round-robin loop where it updates the VCC VALUE, TEMP VALUE, and TINDEX registers, reads the DAC OFFSET and DAC LUT, performs the calculation, and loads the result into the DAC VALUE register. This process is where contention could occur. As such, the state machine waits until I2C is inactive before performing this process. If the I2C port were to become active for a long time period, the temperature compensation does not run. Memory Description The device’s internal memory consists of both volatile and nonvolatile registers located in Lower Memory and four separate memory tables (Upper Memory), as shown in Figure 8. Table 04h contains a nonvolatile temperature-indexed DAC0 LUT and DAC0 OFFSET register designed to hold the pulse-density modulation profile for DAC0. Table 05h contains a nonvolatile temperature-indexed DAC1 LUT and DAC1 OFFSET register designed to hold the pulse-density modulation profile for DAC1. Table 06h contains a nonvolatile temperature-indexed DAC2 LUT and DAC2 OFFSET registers designed to hold the pulse-density modulation profile for DAC2. Table 07h contains a nonvolatile temperature-indexed DAC3 LUT and DAC3 OFFSET registers designed to hold the pulse-density modulation profile for DAC3. Shadowed EEPROM The DAC POR memory locations are actually shadowed EEPROM and are controlled by the shadowed EEPROM bit, SEE. By default, SEE is not set and these locations act as ordinary EEPROM. By setting SEE these locations function like SRAM cells, which allow an infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tW. Because changes made with SEE enabled do not affect the EEPROM, these changes are not retained through power cycles. The power-on value is the last value written with SEE disabled. This function can be used to speed up calibration and minimize the number of EEPROM write cycles. ���������������������������������������������������������������� Maxim Integrated Products 14 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC 00h 02h 04h 06h 08h 10h LOWER MEMORY CTRL MODE SRAM TINDEX TEMP VALUE VCC VALUE EMPTY TS[3:0] ARE THE TABLE SELECT BITS. THESE BITS DETERMINE THE CURRENTLY SELECTED/ADDRESSABLE UPPER MEMORY TABLE. NOTE: TABLES 00h–03h AND 08h–0Fh DO NOT EXIST. DAC VALUES (8 BYTES) 17h EMPTY 78h TS[3:0] = 0100b TS[3:0] = 0101b TS[3:0] = 0110b TS[3:0] = 0111b TABLE 04h TABLE 05h TABLE 06h TABLE 07h DAC0 LUT (48 BYTES) DAC1 LUT (48 BYTES) DAC2 LUT (48 BYTES) DAC3 LUT (48 BYTES) EMPTY EMPTY EMPTY EMPTY DAC0 OFFSET (8 BYTES) DAC1 OFFSET (8 BYTES) DAC2 OFFSET (8 BYTES) DAC3 OFFSET (8 BYTES) DAC POR (8 BYTES) 7Fh 80h UPPER MEMORY (TABLES) AFh F8h FFh Figure 8. Memory Map ���������������������������������������������������������������� Maxim Integrated Products 15 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Register Description This register map shows each byte/word (2-byte) in terms of its row and byte/word placement in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte/ word on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. See the Lower Memory Register Descriptions section for more information about each of these bytes. Lower Memory Register Map LOWER MEMORY WORD 0 WORD 1 WORD 2 ADDR (HEX) BYTE 0 BYTE 1 BYTE 2 BYTE 3 00h CTRL MODE SRAM TINDEX 08h BYTE 4 WORD 3 BYTE 5 BYTE 6 BYTE 7 TEMP VALUE VCC VALUE — 10h DAC3 VALUE DAC2 VALUE DAC1 VALUE DAC0 VALUE 78h DAC3 POR DAC2 POR DAC1 POR DAC0 POR Lower Memory Register Descriptions Lower Memory, Register 00h: CTRL 00h POWER-ON VALUE 00h ACCESS R/W MEMORY TYPE Volatile DONETEMP DONEVCC SRAM SRAM TS3 TS2 TS1 TS0 BIT 7 BIT 0 BIT 7 DONETEMP: Done Temp Status 0 = Temperature conversion in progress. 1 = Temperature conversion completed since this bit was last cleared. BIT 6 DONEVCC: Done VCC Status 0 = VCC conversion in progress. 1 = VCC conversion completed since this bit was last cleared. BITS 5:4 SRAM: General-Purpose SRAM. These bits have no affect on device operation. TS[3:0]: Table Select. The device’s memory tables are accessed by writing the desired table value in this bit field. The device only contains four addressable memory tables, 04h–07h, and therefore the values listed below are the only usable options. BITS 3:0 TS[3:0] TABLE SELECTED CORRESPONDING DAC LUT 0100b 04h 0 0101b 05h 1 0110b 06h 2 0111b 07h 3 ���������������������������������������������������������������� Maxim Integrated Products 16 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Lower Memory, Register 01h: MODE 01h POWER-ON VALUE 40h ACCESS R/W MEMORY TYPE Volatile AEN SEE BIT 7 SRAM SRAM SRAM SRAM SRAM SOFTTXD BIT 0 BIT 7 SEE: Shadowed EEPROM Disable 0 = Enables EEPROM writes to the shadowed EEPROM bytes. 1 = Disables EEPROM writes to shadowed EPPROM bytes during configuration, so that the configuration of the device is not delayed by the EEPROM cycle time. Once the values are known, write this bit to a 0 and write the shadowed EEPROM locations again for data to be written to the EEPROM. BIT 6 AEN: Automatic Enable 0 = The temperature-calculated index value TINDEX is writable by the user and the automatic updates of calculated indexes are disabled. This allows users to interactively test their modules by controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC VALUE registers after the next completion of a temperature conversion. 1 = The internal temperature sensor determines the value of TINDEX. BITS 5:1 BIT 0 SRAM: General-Purpose SRAM. These bits have no affect on device operation. SOFTTXD: Soft Transmit Disable 0 = DACs operate normally. 1 = The DAC outputs are forced to the bit value of the POL bit, which is located in the DAC’s associate DAC POR register. For example, when SOFTTXD is set and POL = 1 in the DAC0 POR register, DAC0 is forced to fullscale output, but if POL = 0, DAC0 is forced to a zero output. This applies to all four DACs. Lower Memory, Register 02h: SRAM 02h POWER-ON VALUE 00h ACCESS R/W MEMORY TYPE Volatile SRAM SRAM SRAM SRAM SRAM BIT 7 SRAM SRAM SRAM BIT 0 These general-purpose SRAM bits have no affect on device operation. ���������������������������������������������������������������� Maxim Integrated Products 17 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Lower Memory, Register 03h: TINDEX 03h POWER-ON VALUE 00h ACCESS When AEN = 1: R ACCESS When AEN = 0: R/W MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The TINDEX register is the temperature indexed address pointer. The TINDEX value corresponds directly to the LUT memory address for the given temperature ranges. The DAC OFFSET address is calculated based on the TINDEX value, so only one pointer is necessary. The pointer value is calculated based on the current temperature reading (see the below equation). The calculation uses different math depending on which LUT range (2NC or 4NC) the current temperature measurement resides in. TINDEX = temp< 56 Temperature + 40 Temperature − 8 + 128 = temp ≥ 56 + 128 4 2 A 1NC hysteresis is implemented in the TINDEX value calculation by adding 1NC to temperature changes of negative slope. When the AEN bit is high, the TINDEX register is read-only and the pointer is updated after the temperature and voltage conversions have completed. When the AEN bit is cleared, I2C writes to the TINDEX register are enabled and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based on the user-selected index. The TINDEX register directly addresses the LUT memory locations by dropping TINDEX and forcing it high. When AEN = 0, any address between 80h and FFh can be addressed. To obtain known results in the DAC VALUE register, TINDEX should be kept between 80h and AFh. TINDEX value is clamped for temperatures below -40NC and above 102NC. Lower Memory, Register 04h–05h: TEMP VALUE POWER-ON VALUE 0000h ACCESS R MEMORY TYPE Volatile 04h S 26 25 24 23 22 21 05h 2-1 2-2 2-3 2-4 0 0 0 BIT 7 20 0 BIT 0 Left-justified signed two’s complement direct-to-temperature measurement. The lower 4 bits always return zero. The temperature reading is clamped to -128NC and +127.9375NC. ���������������������������������������������������������������� Maxim Integrated Products 18 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Lower Memory, Register 06h–07h: VCC VALUE POWER-ON VALUE 0000h ACCESS R MEMORY TYPE Volatile 06h 212 211 210 29 28 27 26 25 07h 24 23 22 21 20 0 0 0 BIT 7 BIT 0 Left-justified unsigned voltage measurement. To calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the LSB as shown in the Analog Voltage Monitoring Characteristics electrical characteristics table. The lower 3 bits always return zero. Lower Lower Lower Lower Memory, Memory, Memory, Memory, Register Register Register Register 10h–11h: 12h–13h: 14h–15h: 16h–17h: DAC3 DAC2 DAC1 DAC0 VALUE VALUE VALUE VALUE POWER-ON VALUE 0000h ACCESS When EN = 1: R ACCESS When EN = 0: R/W MEMORY TYPE Volatile 10h, 12h, 14h, 16h 29 28 27 26 25 24 23 22 11h, 13h, 15h, 17h 21 20 SRAM SRAM SRAM SRAM SRAM SRAM BIT 7 BIT 0 These registers are the left- justified digital 10-bit value used for their associated DAC output. The lower 6 bits have no effect on device operation. At POR these registers are updated to the EEPROM value DAC POR. When the EN bit in DAC POR is set, this register is updated at the end of each temperature conversion, with the calculated result of values recalled from LUT and OFFSET LUT pointed to by TINDEX. V VDAC = REF × DAC VALUE 1024 ���������������������������������������������������������������� Maxim Integrated Products 19 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Lower Lower Lower Lower Memory, Memory, Memory, Memory, Register Register Register Register 78h–79h: DAC3 POR 7Ah–7Bh: DAC2 POR 7Ch–7Dh: DAC1 POR 7Eh–7Fh: DAC0 POR POWER-ON VALUE Recalled from EEPROM ACCESS R/W MEMORY TYPE Nonvolatile (SEE) 78h, 7Ah, 7Ch, 7Eh 29 28 27 26 25 24 23 22 79h, 7Bh, 7Dh, 7Fh 21 20 SEE SEE SEE SEE POL EN BIT 7 BIT 0 BITS 15:6 A left-justified, digital, 10-bit initial DAC value. During a POR these 10 bits are used to fill the corresponding DAC VALUE register. BITS 5:2 SEE: These bits have no effect on device operation. BIT 1 POL: Polarity Select 0 = Normal DAC mode, DAC VALUE = 3FFh results in full-scale output. 1 = Inverted DAC mode, DAC VALUE = 3FFh results in zero output. BIT 0 EN: LUT Enable 0 = DAC mode: At power-on, the corresponding DAC VALUE register is loaded with the value stored in the corresponding DAC POR register. Updates from the temperature-referenced LUT and LUT OFFSET are disabled. The user can write to the DAC VALUE register to set the value for the DAC. The DAC VALUE register is R/W. 1 = LUT mode: At power-on, the corresponding DAC VALUE register is loaded with the value stored in the corresponding DAC POR register. After the first valid temperature conversion, the DAC VALUE register is loaded with the value calculated from the LUT and LUT OFFSET that correspond to the measured temperature. The DAC VALUE register is read-only. ���������������������������������������������������������������� Maxim Integrated Products 20 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Upper Memory Register Descriptions Table Table Table Table 04h, 05h, 06h, 07h, Register Register Register Register 80h–AFh 80h–AFh: 80h–AFh: 80h–AFh: 80h–AFh: DAC0 DAC1 DAC2 DAC3 LUT LUT LUT LUT FACTORY DEFAULT 00h ACCESS R/W MEMORY TYPE Nonvolatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The DAC LUT is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC. The values in this table are added to four times the corresponding value in the DAC OFFSET table to determine the set point for the associated DAC. In all four DAC tables, the DAC LUT registers are formatted the same. Beginning at -40NC, the LUT increments in 4NC steps per address until the temperature reaches 56NC, then it increments in 2NC steps until it clamps at 102NC. See the LUT Temperature Mapping table for full register-totemperature mapping. Register 80h defines the -40NC to -36NC DAC LUT value, register 81h defines the ‑36NC to -32NC DAC LUT value, and so on. LUT TEMPERATURE MAPPING ROW (HEX) BYTE 0 BYTE 1 BYTE 2 80h < -36N -36N -32N BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 -24N -20N -16N -12N 4NC LUT -28N 88h -8N -4N 0N +4N +8N +12N +16N +20N 90h +24N +28N +32N +36N +40N +44N +48N +52N +68N +70N 2NC LUT 98h +56N +58N +60N +62N +64N +66N A0h +72N +74N +76N +78N +80N +82N +84N +86N A8h +88N +90N +92N +94N +96N +98N +100N R +102N ���������������������������������������������������������������� Maxim Integrated Products 21 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Table Table Table Table 04h, 05h, 06h, 07h, Register Register Register Register F8h–FFh F8h–FFh: F8h–FFh: F8h–FFh: F8h–FFh: DAC0 DAC1 DAC2 DAC3 OFFSET OFFSET OFFSET OFFSET FACTORY DEFAULT 00h ACCESS R/W MEMORY TYPE Nonvolatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The DAC OFFSET is a set of registers assigned to hold the pulse-density modulation profile for the associated DAC. The values in this table are multiplied by four and added to the corresponding value in the LUT table to determine the set point for the associated DAC. In all four DAC tables, the DAC OFFSET registers are formatted the same. The OFFSET registers increase in 16NC steps from -8NC to +88NC. Below -8NC the DAC OFFSET is indexed at 0xF8. See the Offset Temperature Mapping table for full register to temperature mapping. Register F8h defines the -40NC to -8NC DAC OFFSET value, register F9h defines the -8NC to +8NC DAC OFFSET value, and so on. OFFSET TEMPERATURE MAPPING ROW (HEX) BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 F8h < -8N -8N +8N +24N +40N +56N +72N R +88N Applications Information Power-Supply Decoupling To achieve the best results when using the DS3911, decouple the power supply with a 0.01FF or 0.1FF capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Likewise, a decoupling capacitor should be placed from VREF to GND. SDA and SCL Pullup Resistors SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics table are within specification. A typical value for the pullup resistors is 4.7kI. ���������������������������������������������������������������� Maxim Integrated Products 22 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Ordering Information PART TEMP RANGE PIN-PACKAGE DS3911T+ -40NC to +100NC 14 TDFN-EP* DS3911T+T -40NC to +100NC 14 TDFN-EP* Note: Contact the factory about CSBGA version availability. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 14 TDFN-EP T1435N+1 21-0253 90-0246 ���������������������������������������������������������������� Maxim Integrated Products 23 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC Revision History REVISION NUMBER REVISION DATE 0 6/11 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products 24 Maxim is a registered trademark of Maxim Integrated Products, Inc.