PI74AVC+16820 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 10-Bit Flip-Flop with Dual and 3-State Outputs Product Features Product Description • PI74AVC+16820 is designed for low voltage operation, VCC = 1.65V to 3.6V Pericom Semiconductor’s PI74AVC+ series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry leading speed. • True ±24mA Balanced Drive @ 3.3V The PI74AVC+16820, a 10-bit flip-flop designed for 1.65V to 3.6V VCC operation, is designed with edge-triggered D-type flip-flops. On the positive transition of clock (CLK) input, the device provides true data at the Q outputs. • IOFF supports partial power-down operation • 3.6V I/O Tolerant inputs and outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. • Industrial operation at –40°C to +85°C • Available Packages: – 56-pin 240-mil wide plastic TSSOP – 56-pin 173-mil wide plastic TVSOP OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor whose minimum value is determined by the current sinking capability of the driver. Logic Block Diagram 1 1OE 2OE CLK D1 28 2 56 55 C1 1D 3 1Q1 1Q2 TO 9 OTHER CHANNELS 1 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Configuration 1OE 1Q1 1Q2 GND 2Q1 2Q2 VCC 3Q1 3Q2 4Q2 GND 4Q2 5Q1 5Q2 6Q1 6Q2 7Q1 VCC 7Q2 8Q1 8Q2 VCC 9Q1 9Q2 GND 10Q1 10Q2 2OE Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 56-Pin 44 A,K 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLK D1 NC GND D2 NC VCC D3 NC D4 GND NC D5 NC D6 NC D7 GND NC D8 NC VCC D9 NC GND D10 NC NC Pin Name Description OE Output Enable Input (Active LOW) Ax Clock Input (Active HIGH) Yx 3-State Outputs GND Ground VCC Power Truth Table(1) Inputs Outputs 1OE 2OE A Y L L L L L L H H H X X Z X H X Z Note 1. H = High Signal Level; L = Low Signal Level X = Irrelevant; Z = High Impedance Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC ........................................ –0.5V to +4.6V Input voltage range, VI ............................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ................................... –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ...................................... –50mA Output clamp current, IOK (VO <0) ................................ –50mA Continuous output current, IO ................................................ ±50mA Continuous current through each VCC or GND ........... ±100mA Package thermal impedance, θ JA(3): package A ........... 64°C/W package K ............ 48°C/W Storage Temperature range, Tstg ............................. –65°C to 150°C Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions(1) VCC Supply Voltage M in. M ax. Operating 1.65 3.6 Data retention only 1.2 VCC = 1.2V VIH High- level Input Voltage VCC VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V 0.65 x VCC 1.7 2 VCC = 1.2V VIL Low- level Input Voltage VI Input Voltage VO Output Voltage IOH High- level output current IOL Low- level output current ∆t∆v Input transition rise or fall rate TA Units GND VCC = 1.65V to 1.95V V 0.35 x VCC VCC = 2.3V to 2.7V 0.7 VCC = 3V to 3.6V 0.8 0 3.6 Active State 0 VCC 3- State 0 3.6 VCC = 1.65V to 1.95V –6 VCC = 2.3V to 2.7V – 12 VCC = 3V to 3.6V – 24 mA VCC = 1.65V to 1.95V 6 VCC = 2.3V to 2.7V 12 VCC = 3V to 3.6V 24 VCC = 1.65V to 3.6V 5 ns/V 85 °C Operating free- air temperature –40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = -40°C +85°C) Parame te rs Te s t Conditions (1) IOH = –100µA VCC M in. 1.65V to 3.6V VCC –0.2V IOH = –6mA VIH = 1.07V 1.65V 1.2 IOH = –12mA VIH = 1.7V 2.3V 1. 7 5 IOH = –24mA VIH = 2V 3V 2.0 Typ. M ax. Units VOH V IOL = 100µA 1.65V to 3.6V 0.2 IOL = 6mA VIH = 0.57V 1.65V 0.45 IOL = 12mA VIH = 0.7V 2.3V 0.55 IOL = 24mA VIH = 0.8V 3V 0.8 VOL II Control Inputs VI = VCC or GND 3.6V ±2.5 IOFF VI or VO = 3.6V 0 ±10 IOZ VI = VCC or GND 3.6V ±10 ICC VO = VCC or GND mA IO = 0 3.6V 40 2.5V 4 3.3V 4 2.5V 6 3.3V 6 2.5V 8 3.3V 8 Control Inputs CI VI = VCC or GND Data Inputs CO Outputs pF VO = VCC or GND Note: Typical values are measured at TA = 25°C. 4 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) VCC = 1.2V VCC = 1.5V ± 0.1V M in. M in. M a x. VCC = 1.8V ± 0.15V M ax. M in. fclock Clock Frequency VCC = 2.5V ± 0.2V M ax. M in. 150 M ax. VCC = 3.3V ± 0.3V M in. 180 18 0 tw Pulse duration, CLK high or low 6.0 3.0 3.0 tsu Setup time, data before CLK↑ 5.7 3.5 2.5 th Hold time, data after CLK↑ 1.2 1.0 1.0 Units M ax. MHz ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) Parame te rs From (Input) To (Output) VCC = 1.2V VCC = 1.5V ± 0.1V M in. M in. M ax. VCC = 1.8V ± 0.15V M ax. M in. VCC = 2.5V ± 0.2V M a x. 150 fmax M in. M ax. 18 0 VCC = 3.3V ± 0.3V M in. Units M ax. 180 MHz tpd CLK Q 4.0 3.2 2.7 ten OE Q 5.8 5.1 4.5 tdis OE Q 5.0 4.6 4.2 ns Operating Characteristics, TA= 25°C Parame te rs Cpd Power Dissipation Capacitance Outputs Enabled Outputs Disabled Te s t Conditions CL = 0pF, f = 10 MHz, 2 outputs switching VCC = 1.8V ±0.15V VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V Typical Typical Typical 40 48 55 Units pF 23 5 27 32 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V AND 1.5V ± 0.1V S1 2Ω From Output Under Test CL = 15pF 2xVCC Open GND 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH –0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 6 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V ±0.15V S1 12ΩkΩ From Output Under Test CL = 30 15pF 2xVCC Open GND 2Ω 1 kΩ (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH –0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 7 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V ± 0.2V S1 500Ω 2Ω From Output Under Test CL =30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH –0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 8 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V ± 0.3V S1 500Ω 2Ω From Output Under Test CL = 30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH –0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 9 PS8446A 03/07/01 PI74AVC+16820 2.5V 10-Bit Flip-Flop w/Dual and 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical - 56-pin TSSOP (A-package) 56 .236 6.0 .244 6.2 1 .547 13.9 .555 14.1 1.20 SEATING PLANE .047 Max. .004 0.09 .008 0.20 .0197 BSC 0.50 .007 .011 0.17 0.27 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 0.45 .018 0.75 .030 .002 .006 0.05 0.15 .319 BSC 8.1 Packaging Mechanical - 56-pin TVSOP (K-package) 56 4.30 4.50 .169 .177 0.09 0.20 .0035 .008 1 .441 .449 .031 .041 0.80 1.05 11.20 11.40 0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .016 BSC 0.40 X.XX X.XX .005 .009 0.13 0.23 .002 .006 0.05 0.15 .047 1.20 Max. DENOTES DIMENSIONS IN MILLIMETERS Orde ring Info. De s cription PI74AVC+16820A 56- pin, 240- mil wide plastic TSSOP PI74AVC+16820K 56- pin, 173- mil wide plastic TSSOP Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8446A 03/07/01