ETC PI74AVC+16841K

PI74AVC+16841
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2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
Product Features
• PI74AVC+16841 is designed for low-voltage operation,
Product Description
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
VCC = 1.65V to 3.6V
• True ±24mA Balanced Drive @ 3.3V
The PI74AVC+16841, a 20-bit bus-interface D-type latch, is designed
for 1.65V to 3.6V VCC operation.
• IOFF supports partial power-down operation
• 3.6V I/O Tolerant Inputs and Outputs
The device features 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads.
It is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation: –40°C to +85°C
• Available Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
The device can be used as two 10-bit latches or one
20-bit latch (transparent D-type). The device has noninverting Data
(D) inputs and provides true data at its outputs. While the Latch
Enable (1LE or 2LE) input is HIGH, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken LOW, the Q
outputs are latched at the levels set up at the D inputs.
Logic Block Diagram
1OE
1LE
A buffered Output Enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedance state. In that
state, outputs neither load nor drive the bus lines significantly.
1
56
C1
2
1D1
55
The Output Enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
1Q1
1D
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
TO NINE OTHER CHANNELS
2OE
2LE
28
29
C1
15
2D1
42
2Q1
1D
TO NINE OTHER CHANNELS
1
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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Product Pin Description
Pin Name
Truth Table(1) Each 10-Bit Latch
Inputs
De s cription
Outputs
OE
LE
D
Q
Latch Enable
L
H
H
H
D
Data Input
L
H
L
L
Q
Data Output
L
L
X
QO
GND
Ground
H
X
X
Z
VCC
Power
OE
Output Enable Input (Active LOW)
LE
Note:
1. H=
L=
Z=
X=
Product Pin Configuration
56
55
1LE
1Q1
1
2
1Q2
3
54
1D2
GND
4
53
GND
1Q3
5
52
1D3
1Q4
6
7
8
51
50
49
1D4
9
10
48
47
1D6
1OE
VCC
1Q5
1Q6
1Q7
1D1
VCC
1D5
1D7
1Q8
11 56-Pin 46
12 A, K 45
1Q9
13
44
1D9
1Q10
14
15
16
43
42
41
1D10
17
18
40
39
2D3
19
20
21
38
37
36
2D4
22
23
24
35
34
33
VCC
32
31
GND
2Q9
25
26
2Q10
27
30
2D10
2OE
28
29
2LE
GND
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
High Signal Level
Low Signal Level
High Impedance
Irrelevant
GND
1D8
2D1
2D2
GND
2D5
2D6
2D7
2D8
2D9
2
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ................................................. –0.5V to +4.6V
Input voltage range, VI ....................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ........................ –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ........................................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ....................................................... –50mA
Output clamp current, IOK (VO <0) .................................................. –50mA
Continuous output current, IO ........................................................ ±50mA
Continuous current through each VCC or GND ............................. ±100mA
Package thermal impedance, θJA(3): package A ............................ 64°C/W
package K ........................... 48°C/W
Storage Temperature range, Tstg ........................................ –65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be
exceeded if the input and output curent rating are
observed.
2. Output positive-voltage rating may be exceeded up to
4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
VCC
Supply Voltage
M in.
M ax.
Operating
1.65
3.6
Data retention only
1.2
VCC = 1.2V
VIH
High- level Input Voltage
VCC
VCC = 1.65V to 1.95V
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
0.65 x VCC
1.7
2
VCC = 1.2V
VIL
Low- level Input Voltage
VI
Input Voltage
VO
Output Voltage
IOH High- level output current
IOL
Low- level output current
DtDv Input transition rise or fall rate
TA
Units
GND
VCC = 1.65V to 1.95V
V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.65V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C)
Te s t Conditions (1)
Parame te rs
VOH
IOH = –100µA
VOL
VCC
M in.
1.65V to 3.6V
VCC –0.2V
IOH = –6mA
VIH = 1.07V
1.65V
1.2
IOH = –12mA
VIH = 1.7V
2.3V
1.75
IOH = –24mA
VIH = 2V
3V
2.0
IOL = 100µA
M ax.
1.65V to 3.6V
0.2
IOL = 6mA
VIH = 0.57V
1.65V
0.45
IOL = 12mA
VIH = 0.7V
2.3V
0.55
IOL = 24mA
VIH = 0.8V
3V
0.8
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VI = VCC or GND
3.6V
±10
ICC
VO = VCC or GND
3.6V
40
2.5V
4
3.3V
4
2.5V
6
3.3V
6
2.5V
8
3.3V
8
II
CI
Control Inputs
Control Inputs
IO = 0
VI = VCC or GND
Data Inputs
CO
Outputs
VO = VCC or GND
Units
V
µA
pF
Note:
1. Typical values are measured at TA = 25°C.
4
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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Timing requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V
VCC = 1.5V
± 0.1V
M in.
M in.
M ax.
M ax. M in.
tw Pulse duration, LE HIGH
tsu Setup time, data before LE↓
VCC = 1.8V
± 0.15V
M ax.
VCC = 2.5V
± 0.2V
M in.
M ax.
VCC = 3.3V
± 0.3V
M in.
2.2
2.0
1.8
1.7
1.2
1.1
0.9
0.8
2
1.1
1.1
1.1
0.9
th Hold time, data after LE↓
M ax.
Units
ns
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parame te rs
tpd
From
(Input)
D
LE
To
(Output)
VCC = 1.2V
Q
VCC = 1.5V
± 0.1V
Typ.
M in.
6.0
1.2
4.6
7.0
1.4
VCC = 1.8V
± 0.15V
M ax. M in.
VCC = 2.5V
± 0.2V
VCC = 3.3V
± 0.3V
M ax.
M in.
M ax.
M in.
M ax.
1
4.0
0.8
3.1
0.7
2.6
4.8
1.1
4.0
0.8
3.0
0.7
2.8
ten
OE
Q
6.0
1.6
4.2
1.6
4.0
1.4
3.5
0.7
3.1
tdis
OE
Q
6.0
2.5
5.8
2.3
5.5
1.3
3.4
1.2
3.4
Units
ns
Operating Characteristics, TA= 25°C
Parame te rs
Cpd Power Dissipation Capacitance
O utputs Enabled
O utputs Disabled
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Te s t Conditions
Typical
Typical
Typical
CL = 0pF,
f = 10 MHz
50
53
59
25
28
30
5
PS8549
Units
pF
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V and 1.5V ±0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
6
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
12ΩkΩ
From Output
Under Test
CL = 30
15pF
Open
GND
2Ω
1 kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.15V
VOL
tPHZ
VCC/2
VOH –0.1V
0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
7
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL =30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
8
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ±0.3V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL = 30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.3V
VOL
tPHZ
VCC/2
VOH –0.1V
0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
9
PS8549
07/31/01
PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
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56-pin TSSOP (A) Package
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
56-pin TVSOP (K) Package
56
.169
.177
4.30
4.50
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
0.09
0.20
.0035
.008
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Orde ring D ata
D e s cription
PI74AVC+16841A
56- pin, 240- mil wide plastic TSSO P
PI74AVC+16841K
56- pin, 173- mil wide plastic TVSO P
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8549
07/31/01