ETC PI74AVC+16374A

PI74AVC+16374
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
2.5V 16-Bit Edge Triggered D-Type
Flip-Flop with 3-State Outputs
Product Features
Product Description
• PI74AVC+16374 is designed for low voltage operation,
VCC = 1.65V to 3.6V
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced submicron CMOS
technology, achieving industry leading speed.
• True ±24mA Balanced Drive @ 3.3V
The PI74ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit flip-flops or one
16-bit flip-flop. On the positive transition of the Clock (CLK) input,
the Q outputs of the flip-flop take on the logic levels set up at the
data (D) inputs. OE can be used to place the eight outputs in either
a normal logic state (high or low logic levels) or a high-impedance
state. In that state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive
provide the capability to drive bus lines without need for interface
or pullup components. OE does not affect internal operations of the
flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
• Compatible with Philips and T.I. AVC Logic family
• IOFF supports partial power-down operation
• 3.6V I/O Tolerant inputs and outputs
• All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
• Industrial operation at –40°C to +85°C
• Available Packages:
– 48-pin 240-mil wide plastic TSSOP
– 48-pin 173-mil wide plastic TVSOP
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
1OE
1CLK
1
48
C1
2
1D1
47
1Q1
1D
To Seven Other Channels
2OE
2CLK
24
25
C1
13
2D1
36
2Q1
1D
To Seven Other Channels
1
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Notes:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Supply voltage range, VCC ............................................. –0.5V to +4.6V
Input voltage range, VI ................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ...................... –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ......................................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) .................................................... –50mA
Output clamp current, IOK (VO <0) .............................................. –50mA
Continuous output current, IO .................................................... ±50mA
Continuous current through each VCC or GND ......................... ±100mA
Package thermal impedance, θJA(3): package A .........................64°C/W
package K ......................... 48°C/W
Storage Temperature range, Tstg .................................... –65°C to 150°C
Product Pin Configuration
Product Pin Description
1OE
1
48
1CLK
1Q1
2
47
1D1
1Q2
3
46
1D2
GND
4
45
GND
1Q3
5
44
1D3
1Q4
VCC
6
43
7
42
1D4
VCC
1Q5
8
41
1D5
1Q6
9
40
1D6
GND
10
39
GND
1Q7
11
38
1D7
1Q8
12
37
1D8
2Q1
13
36
2Q2
14
GND
48-Pin
A,K
1. Input & output negative-voltage ratings may be
exceeded if the input and output curent rating are
observed.
2. Output positive-voltage rating may be exceeded up to
4.6V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Pin Name
OE
CLK
Dx
Qx
GND
VCC
Description
3-State Output Enable Inputs (Active LOW)
Clock Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Truth Table(1)
Inputs
Outputs
OE
CLK
D
Q
L
↑
H
H
2D1
L
↑
L
L
35
2D2
L
H or L
X
Q0
15
34
GND
2Q3
X
X
Z
33
2D3
H
16
2Q4
17
32
2D4
VCC
2Q5
18
31
19
30
VCC
2D5
2Q6
20
29
2D6
GND
21
28
GND
2Q7
22
27
2D7
2Q8
23
26
2D8
2OE
24
25
2CLK
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Don't Care or Irrelevant
Z = High Impedance
2
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Recommended Operating Conditions(1)
VCC
Supply Voltage
M in.
M ax.
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2V
VIH
High- level Input Voltage
VCC
VCC = 1.4V to 1.6V
0.65 x VCC
VCC = 1.65V to 1.95V
0.65 x VCC
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
1.7
2
VCC = 1.2V
VIL
Low- level Input Voltage
VI
Input Voltage
VO
Output Voltage
IOHS High- level output current
IOLS
Low- level output current
∆t∆v Input transition rise or fall rate
TA
Units
V
GND
VCC = 1.4V to 1.6V
0.35 x VCC
VCC = 1.65V to 1.95V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.4V to 1.6V
–4
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.4V to 1.6V
4
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.4V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
DC Electrical Characteristics (Over the Operating Range, TA = -40°C +85°C)
Te s t Conditions (1)
Parame te rs
IOH = –100µA
VOH
II
M in.
1.4V to 3.6V
VCC –0.2V
IOHS = –4mA
VIH = 0.91V
1.4V
1.05
IOHS = –6mA
VIH = 1.07V
1.65V
1.2
IOHS = –12mA
VIH = 1.7V
2.3V
1.75
IOHS = –24mA
VIH = 2V
3V
2.0
IOLS = 100µA
VOL
VCC
M ax.
1.4V to 3.6V
0.2
VIL = 0.49V
1.4V
0.4
IOLS= 6mA
VIL = 0.57V
1.65V
0.45
IOLS = 12mA
VIL = 0.7V
2.3V
0.55
IOLS = 24mA
VIL = 0.8V
3V
0.8
Control Inputs
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND
3.6V
40
IO = 0
VI = VCC or GND
CI
Data Inputs
Outputs
VO = VCC or GND
2.5V
3.5
3.3V
3.5
2.5V
6
3.3V
6
2.5V
6.5
3.3V
6.5
Units
V
IOLS= 4mA
Control Inputs
CO
Typ.
µA
pF
Note: Typical values are measured at TA = 25°C.
4
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Timing requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V
M in.
M ax.
VCC = 1.5V
± 0.1V
M in.
VCC = 1.8V
± 0.15V
M ax. M in.
M ax.
fclock Clock frequency
VCC = 2.5V
± 0.2V
M in.
160
tw
Pulse duration, CLK high or low
tsu
Setup time, data before CLK↑
4.1
th
Hold time, data after CLK↑
1.7
M ax.
VCC = 3.3V
± 0.3V
M in.
Units
M ax.
200
200
3.1
2.5
2.5
2.7
1.9
1.4
1.4
1.3
1.2
1.1
1.1
ns
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
VCC = 1.2V
Typ.
VCC = 1.5V
± 0.1V
M in.
VCC = 1.8V
± 0.15V
M ax. M in.
fmax
M ax.
160
VCC = 2.5V
± 0.2V
M in.
M ax.
200
VCC = 3.3V
± 0.3V
M in.
Units
M ax.
200
tpd
CLK
Q
7.3
1.5
8.4
1.2
6.7
0.8
4.1
0.7
3.3
ten
OE
Q
7.4
1.6
8.5
1.6
6.7
0.9
4.3
0.7
3.4
tdis
OE
Q
8.4
2.5
9.4
2.3
7.8
1
4.2
1.5
3.9
ns
Operating Characteristics, TA= 25°C
Parame te rs
Cpd Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
Te s t Conditions
CL = 0pF,
f = 10 MHz
2 outputs switching
5
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Typical
Typical
Typical
74
81
89
52
57
63
Units
pF
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5V ± 0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
6
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
12ΩkΩ
From Output
Under Test
CL = 30
15pF
Open
GND
2Ω
1 kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.15V
VOL
tPHZ
VCC/2
VOH –0.1V
0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
7
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL =30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
8
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
2xVCC
S1
500Ω
2Ω
From Output
Under Test
CL = 30
15pF
Open
GND
500Ω
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
0.3V
VOL
tPHZ
VCC/2
VOH –0.1V
0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
9
PS8527
03/01/01
PI74AVC+16374
2.5V 16-Bit Edge Triggered D-Type
Flip Flop with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Packaging Mechanical - 48-pin TSSOP (A-package)
48
.236
.244
1
6.0
6.2
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.0197
BSC
0.50
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
0.17
0.27
.319
BSC
8.1
Packaging Mechanical - 48-pin TVSOP (TSSOP) (K-package)
48
.169
.177
4.30
4.50
.0035 0.09
.008 0.20
.031
.041
0.80
1.05
1
.378 9.60
.386 9.80
0.45 .018
0.75 .030
.252
BSC
6.4
SEATING
PLANE
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
.016
BSC
0.40
.0051
.009
0.13
0.23
.002
.006
0.05
0.15
Max.
.047
1.20
Orde ring Information
De s cription
PI74AVC+16374A
48- pin, 240- mil wide plastic TSSO P
PI74AVC+16374K
48- pin, 173- mil wide plastic TVSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
10
PS8527
03/01/01