ETC PI74AVC+16501A

PI74AVC+16501
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18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
Product Description
• PI74AVC+16501 is designed for low voltage operation,
VCC = 1.65V to 3.6V
• True ±24mA Balanced Drive @ 3.3V
• IOFF supports partial Power-down operation
• 3.6V I/O Tolerant inputs and outputs
• All outputs contain a potential DDC (Dynamic Drive Control)
that reduces noise without degradating propagation delay.
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74AVC+ 16501 univeral bus transceiver is designed for
1.65V to 3.6V VCC operation.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latch Enable (LEAB and LEBA), and CLOCK (CLKAB
and CLKBA) inputs. For A-to-B data flow, the device operates in
the transparent mode when LEAB is HIGH. When LEAB is LOW,
the A data is latched if CLKAB is held at a high or low logic level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB is HIGH, the
outputs are active. When OEAB is LOW, the outputs are in the highimpedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
and CLKBA. The Output Enables are complementary (OEAB is
active HIGH and OEBA is active LOW)
To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
OEAB 1
CLKAB 55
LEAB 2
LEBA 28
CLKBA 30
OEBA 27
A1 3
1D
C1
CLK
54
B1
C1
1D
C1
1D
CLK
TO 17 OTHER CHANNELS
1
PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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Product Pin Description
Pin Name
OE
LE
CLK
Ax
Bx
GND
VCC
Truth Table(1)†
Description
Output Enable Input (Active HIGH)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
Product Pin Configuration
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
1
2
56
55
GND
CLKAB
3
4
5
54
53
52
B1
6
7
8
51
50
49
B3
9
10
48
47
B5
11
12 56-Pin
13
A,K
46
45
44
GND
14
15
B2
VCC
B4
B6
16
17
18
40
39
B12
19
20
21
38
37
36
B13
B14
22
23
24
35
34
33
VCC
25
26
32
31
GND
B18
27
28
30
29
CLKBA
VCC
A16
A17
GND
A18
OEBA
LEBA
A
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
­
L
L
H
L
­
H
H
H
L
H
X
B0‡
H
L
L
X
B0§
B8
B9
A12
A14
A15
CLKAB
B7
A11
A13
LEAB
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is HIGH
before LEAB goes LOW.
§ Output level before the indicated steady-state input
conditions were established.
GND
43
42
41
GND
Output B
OEAB
B10
B11
GND
B15
B16
B17
GND
2
PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ............................................................................................ –0.5V to +4.6V
Input voltage range, VI .................................................................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ............................................................ –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2) ........................................................................................ –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................................................ –50mA
Output clamp current, IOK (VO <0) ...................................................................... –50mA
Continuous output current, IO ...................................................................................................... ±50mA
Continuous current through each VCC or GND ................................................. ±100mA
Package thermal impedance, θJA(3): package A .................................................. 64°C/W
package K ..................................................48°C/W
Storage Temperature range, Tstg ............................................................ –65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output current rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
VCC
Supply Voltage
M in.
M ax.
Operating
1.65
3.6
Data retention only
1.2
VCC = 1.2V
VIH
High- level Input Voltage
VCC
VCC = 1.65V to 1.95V
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
0.65 x VCC
1.7
2
VCC = 1.2V
VIL
Low- level Input Voltage
VI
Input Voltage
VO
Output Voltage
IOH High- level output current
IOL
Low- level output current
∆t∆v Input transition rise or fall rate
TA
Units
Gnd
V
0.35 x VCC
VCC = 1.65V to 1.95V
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
–6
VCC = 2.3V to 2.7V
– 12
VCC = 3V to 3.6V
– 24
mA
VCC = 1.65V to 1.95V
6
VCC = 2.3V to 2.7V
12
VCC = 3V to 3.6V
24
VCC = 1.65V to 3.6V
5
ns/V
85
°C
Operating free- air temperature
–40
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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DC Electrical Characteristics (Over Operating Range, TA = –40°C +85°C)
Parame te rs
Te s t Conditions (1)
IOH = –100µA
VOH
M in.
1.65V to 3.6V
VCC –0.2V
IOH = –6mA
VIH = 1.07V
1.65V
1.2
IOH = –12mA
VIH = 1.7V
2.3V
1.75
IOH = –24mA
VIH = 2V
3V
2.0
IOL = 100µA
VOL
VCC
M ax.
V
1.65V to 3.6V
0.2
IOL = 6mA
VIH = 0.57V
1.65V
0.45
IOL = 12mA
VIH = 0.7V
2.3V
0.55
IOL = 24mA
VIH = 0.8V
3V
0.8
VI = VCC or GND
3.6V
±2.5
IOFF
VI or VO = 3.6V
0
±10
IOZ
VI = VCC or GND
3.6V
±10
ICC
VO = VCC or GND
3.6V
40
2.5V
4
3.3V
4
2.5V
6
3.3V
6
2.5V
8
3.3V
8
II
CI
Control Inputs
Control Inputs
IO = 0
VI = VCC or GND
Data Inputs
CO
Outputs
VO = VCC or GND
Units
µA
pF
Note: Typical values are measured at TA = 25°C.
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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Timing Requirements
(Over recommended operating free-air temperature range,unless otherwise noted, see Figures 1 thru 4)
VCC = 1.5V
±0.1V
VCC = 1.2 V
VCC = 1.8V
±0.15V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
M in. M ax. M in. M ax. M in. M ax. M in. M ax. M in. M ax. Units
fclock Clock Frequency
180
tw
LE High
Pulse duration CLK high or low
tsu
Setup time
th
Hold timε
3
3
3
3
1.5
1.2
CLK High
1.5
1.2
CLK Low
1.0
1.0
0.7
0.7
1.4
1.2
Data before CLK↑
Data before LE ↓
Data before CLK↑
Data after LE ↓
180
CLK High
or Low
MHz
ns
Switching Characteristics
(Over recommended operating free-air temperature range,unless otherwise noted, see Figures 1 thru 4)
Parame te rs
From
(Input)
To
(Output)
VCC = 1.5V
±0.1V
VCC = 1.2V
M in.
M ax.
M in.
M ax.
fmax
M in.
M ax.
150
A or B
tpd
VCC = 1.8V
±0.15V
LE
CLK
B or A
A or B
VCC = 2.5V
±0.2V
M in.
M ax.
150
VCC = 3.3V
±0.3V
M in.
M ax.
150
Units
MHz
5.2
3.7
3.5
3.0
2.5
6.2
4.3
4.0
3.3
3.0
7.0
4.6
4.4
3.3
3.0
ten
OEAB
B
6.3
4.1
3.9
3.3
3.0
tdis
OEAB
B
6.3
4.7
4.3
3.3
3.3
ten
OEBA
A
6.8
4.6
4.2
3.6
3.3
tdis
OEBA
A
7.0
5.0
4.5
3.9
3.6
ns
Operating Characteristics, TA= 25°C
Parame te rs
Cpd Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 0pF,
f = 10 MHz
5
VCC = 1.8V
±0.2V
VCC = 2.5V
±0.2V
VCC = 3.3V
±0.3V
Typ.
Typ.
Typ.
21
24
30
2
4
7
Units
pF
PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5V ± 0.1V
2xVCC
S1
2Ω
From Output
Under Test
CL = 15pF
Open
GND
2Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.1V
VOL
tPHZ
VCC/2
VOH –0.1V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns,
tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
2xVCC
S1
1kΩ
From Output
Under Test
CL = 30pF
Open
GND
1kΩ
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
Input
th
VCC/2
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
0V
VOH
Output
VCC /2
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns,
tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns,
tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
2xVCC
S1
500Ω
From Output
Under Test
CL = 30pF
Open
GND
500Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
VCC/2
Input
tW
0V
tsu
VCC
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
VCC/2
Voltage Waveforms
Pulse Duration
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.3V
VOL
tPHZ
VCC/2
VOH –0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns,
tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
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PS8541
05/01/01
PI74AVC+16501
18-Bit
Universal
Bus Transceiver
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Packaging Mechanical - 56-pin TSSOP (A package)
56
.236
.244
1
.547
.555
6.0
6.2
13.9
14.1
1.20
SEATING PLANE
.047
Max.
.004 0.09
.008 0.20
.0197
BSC
0.50
.007
.011
0.17
0.27
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.319 BSC
8.1
Packaging Mechanical - 56-pin TVSOP (K package)
56
.169
.177
4.30
4.50
0.09
0.20
.0035
.008
1
.441
.449
0.45 .018
0.75 .030
.031
.041
0.80
1.05
11.20
11.40
.252
BSC
6.4
SEATING
PLANE
.016
BSC
0.40
X.XX
X.XX
.002
.006
0.05
0.15
.005
.009
0.13
0.23
.047
1.20
Max.
DENOTES DIMENSIONS
IN MILLIMETERS
Ordering Information
Orde ring Information
De s cription
PI74AVC+16501A
56- pin, 240- mil wide plastic TSSOP
PI74AVC+16501K
56- pin, 173- mil wide plastic TVSOP
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8541
05/01/01