IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPU877A DESCRIPTION: FEATURES: The CSPU877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500µA. The CSPU877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877A, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877A is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details. • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 270MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin MLF packages APPLICATIONS: • Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver • Along with SSTU32864/65/66, DDR2 register, provides complete solution for DDR2 DIMMs FUNCTIONAL BLOCK DIAGRAM OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK Y5 CLK Y5 10KΩ - 100KΩ PLL Y6 Y6 FBIN Y7 FBIN Y7 Y8 Y8 Y9 NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. Y9 FBOUT The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE FBOUT JANUARY 2004 1 c 2004 Integrated Device Technology, Inc. DSC-6495/4 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION Y8 Y8 GND GND Y9 VDDQ NB GND Y9 VDDQ NB GND Y4 VDDQ GND GND Y4 Y3 Y3 J K 6 Y6 Y6 Y7 Y7 FBIN 5 Y5 GND GND OS VDDQ OE VDDQ 4 Y5 GND NB VDDQ NB NB 3 Y0 GND NB VDDQ NB NB 2 Y0 GND GND 1 Y1 Y1 Y2 Y2 CLK CLK A B C D E F FBIN FBOUT FBOUT VDDQ VDDQ VDDQ AGND AVDD H G VFBGA TOP VIEW 52 BALL VFBGA PACKAGE LAYOUT 0.65mm 6 5 TOP VIEW 4 3 2 1 A B C D E F G H J K A B C D E F G H J K 1 2 3 4 5 6 2 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1,2) VDDQ 31 Y6 Y5 Y5 Y6 32 33 34 VDDQ 36 35 Y0 Y0 38 37 Y1 39 40 Y1 PIN CONFIGURATION VDDQ 1 30 Y7 Y2 2 29 Y7 Y2 3 28 VDDQ CLK 4 27 FBIN CLK 5 26 FBIN VDDQ 6 25 FBOUT AGND 7 24 FBOUT AVDD 8 23 VDDQ VDDQ 9 22 OE GND 10 21 OS 17 18 19 20 Y9 Y8 Y8 VDDQ Y4 16 14 Y4 Y9 13 VDDQ 12 Y3 15 11 Y3 GND Symbol Rating Max Unit VDDQ, AVDD VI(3) Supply Voltage Range Input Voltage Range –0.5 to +2.5 –0.5 to VDDQ + 0.5 V V VO(3) Voltage range applied to any output in the high or low state –0.5 to VDDQ + 0.5 V IIK (VI <0) Input clamp current ±50 mA IOK (VO <0 or Output Clamp Current ±50 mA Continuous Output Current ±50 mA ±100 mA – 65 to +150 °C VO > VDDQ) IO (VO =0 to VDDQ) VDDQ or GND Continuous Current TSTG Storage Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max. MLF TOP VIEW CAPACITANCE(1) Parameter Description CIN Input Capacitance Min. Typ. Max. Unit 2 — 3 pF 0.25 pF — pF VI = VDDQ or GND C I∆ Delta Input Capacitance CLK, CLK, FBIN, FBIN CL Load Capacitance — 10 NOTE: 1. Unused inputs must be held high or low to prevent them from floating. RECOMMENDED OPERATING CONDITIONS Symbol AVDD(1) VDDQ TA Parameter Min. Supply Voltage Typ. Max. VDDQ I/O Supply Voltage Operating Free-Air Temperature Unit V 1.7 1.8 1.9 V 0 +70 °C NOTE: 1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are guaranteed. 3 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (VFBGA) Pin Name Pin Number Description AGND G1 Ground for 1.8V analog supply AV DD H1 1.8V analog supply CLK, CLK E1, F1 Differential clock input with a 10KΩ to 100KΩ pulldown resistor FBIN, FBIN E6, F6 Feedback differential clock input FBOUT, FBOUT G6, H6 Feedback differential clock output GND B2 - B5, C2, C5, H2, H5, J2 - J5 VDDQ D2 - D4, E2, E5, F2, G2 - G5 OE F5 Ground 1.8V supply Output Enable OS D5 Y[0:9] A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 Buffered output of input clock, CLK Output Select (tied to GND or VDDQ) Y[0:9] A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 Buffered output of input clock, CLK NB No Ball PIN DESCRIPTION (MLF) Pin Name Pin Number Description AGND 7 Ground for 1.8V analog supply AVDD 8 1.8V analog supply CLK, CLK 4, 5 Differential clock input with a 10KΩ to 100KΩ pulldown resistor FBIN, FBIN 26, 27 Feedback differential clock input FBOUT, FBOUT 24, 25 Feedback differential clock output GND 10 VDDQ 1, 6, 9, 15, 20, 23, 28, 31, 36 OE 22 Ground 1.8V supply Output Enable OS 21 Y[0:9] 3, 11, 14, 16, 19, 29, 33, 34, 38, 39 Buffered output of input clock, CLK Output Select (tied to GND or VDDQ) Y[0:9] 2, 12, 13, 17, 18, 30, 32, 35, 37, 40 Buffered output of input clock, CLK NB No Ball 4 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE(1,2) INPUTS OUTPUTS AVDD OE OS CLK CLK Y Y FBOUT FBOUT PLL GND H X L H L H L H OFF GND H X H L H L H L OFF GND L H L H L(z) L(z) L H OFF L(z) L(z) H L OFF L H ON H L ON L H ON GND 1.8V (nom) L L L H H L Y7 Active L(z) L(z) L(z) L(z) Y7 Y7 Active Active L H H 1.8V (nom) L L H L 1.8V (nom) H X L H 1.8V (nom) H X H 1.8V (nom) X X L L X X X H H (3) Y7 Active L L (3) H L H L ON L(z) L(z) L(z) L(z) OFF Reserved NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. L(z) means the outputs are disabled to a LOW state, meeting the IODL limit in DC Electrical Characteristics table. 3. The device will enter a low power-down mode when CLK and CLK are both at logic LOW. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C Symbol Parameter Conditions Typ. Max. Unit – 1.2 V 0.35VDDQ V 0.65VDDQ VDDQ + 0.3 V VDDQ + 0.4 V V VDDQ - 0.2 V 1.1 Input Clamp Voltage (All Inputs) VIL(2) Input LOW Voltage (OE, OS, CLK, CLK) VIH(2) Input HIGH Voltage (OE, OS, CLK, CLK) VIN(1) Input Signal Voltage -0.3 VID(DC)(2) VOD(3) VOH VDDQ = 1.7V, II = -18mA Min. VIK DC Input Differential Voltage 0.3 Output Differential Voltage AVDD/VDDQ = 1.7V 0.5 Output HIGH Voltage IOH = -100µA, VDDQ = 1.7V to 1.9V IOH = -9mA, VDDQ = 1.7V VOL Output LOW Voltage IOL = 100µA, VDDQ = 1.7V to 1.9V IODL Output Disabled LOW Current OE = L, VODL = 100mV, AVDD/VDDQ = 1.7V Input Current CLK, CLK AVDD/VDDQ = Max., VI = 0V to VDDQ 0.1 IOL = 9mA, VDDQ = 1.7V IIN OE, OS, FBIN, FBIN IDDLD IDD V 0.6 100 µA ±250 µA ±10 Static Supply Current (IDDQ and IADD) AVDD/VDDQ = Max., CLK and CLK = GND 500 µA Dynamic Power Supply Current AVDD/VDDQ = Max., CLK = 270MHz 300 mA (IDDQ and IADD)(4,5) NOTES: 1. VIN specifies the allowable DC excursion of each different output. 2. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK VIH and VIL limits are used to define the DC LOW and HIGH levels for the power down mode. 3. VOD is the magnitude of the difference between the true output level and the complementary level. 4. All Outputs are left open (unconnected to PCB). 5. Total IDD = IDDQ + IADD = FCK * CPD * VDDQ, for Cpd = (IDDQ + IADD) / (FCK * VDDQ) where FCK is the input frequency, VDDQ is the power supply, and CPD is the Power Dissipation Capacitance. 5 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TIMING REQUIREMENTS Symbol Parameter Min. Max. Unit Operating Clock Frequency(1,2) 125 270 MHz Application Clock Frequency(1,3) 160 270 MHz tDC Input Clock Duty Cycle 40 60 % tL Stabilization Time(4) 15 µs fCLK NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle. AC ELECTRICAL CHARACTERISTICS(1) Symbol tPLH(2) Description Test Conditions LOW to HIGH Level Propagation Delay Time AVDD = GND, OE = H, OS = L, Min. Typ.(2) Max. Unit TBD ns TBD ns CLK to any output tPHL(2) HIGH to LOW Level Propagation Delay Time AVDD = GND, OE = H, OS = L, CLK to any output tJIT(CC+) Jitter (cycle-to-cycle) 166/200/266MHz 0 40 0 -40 166/200/266MHz -40 40 tJIT(CC-) tJIT(PER)(3) Jitter (period) tJIT(HPER)(3) Half-Period Jitter 166/200/266MHz -60 tSLR(O)(1,4) Output Clock Slew Rate (single-ended) 166/200/266MHz (20% to 80%) 1.5 tSLR(I)(1,4) Output Enable (OE) Input Clock Slew Rate ps ps 60 ps 2.5 3 V/ns 0.5 V/ns 1 2.5 4 t(∅)(5) Static Phase Offset 166/200/266MHz -50 50 ps t(∅)DYN Dynamic Phase Offset 166/200/266MHz -50 50 ps tSK(O) Output Skew 40 ps tEN Output Enable to any Y or Y 8 ns tDIS Output Disable to any Y or Y 8 ns (VDDQ/2) +0.1 V 0.6 VDDQ +0.4 V (VDDQ/2) -0.15 (VDDQ/2) +0.15 V VOX(6) AC Differential Output Crosspoint Voltage VID(AC) AC Differential Input Voltage VIX Differential outputs terminated with 120Ω AC Differential Input Crosspoint Voltage (VDDQ/2) -0.1 The PLL on the CSPU877A will meet all the above test parameters while supporting SSC synthesizers with the following parameters: SSC Modulation Frequency 30 33 KHz SSC Clock Input Frequency Deviation 0 -0.5 % f3dB PLL Loop Bandwidth 2 MHz NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50Ω equal length cables with SMA connectors on the test board. 2. Refers to transition of non-inverting output. 3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other. 4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 5. Static phase offset does not include jitter. 6. VOX is specified at the DDR DRAM clock input or test load. 6 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUIT AND SWITCHING WAVEFORMS VDDQ Z = 60Ω C = 10pF L = 2.97" R = 120Ω Z = 60Ω GND 0V R = 1MΩ C = 1pF 0V R = 1MΩ C = 1pF C = 10pF L = 2.97" GND CSPU877A SCOPE GND Figure 1: Output Load Test Circuit 1 VDDQ/2 R = 10Ω Z = 60Ω L = 2.97" Z = 50Ω C = 10pF R = 50Ω VDDQ/2 0V R = 10Ω Z = 60Ω L = 2.97" Z = 50Ω C = 10pF R = 50Ω 0V VDDQ/2 CSPU877A SCOPE VDDQ/2 Figure 2: Output Load Test Circuit 2 7 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT tcycle n tcycle n+1 tjit(cc) = tcycle n tcycle n+1 Cycle-to-Cycle jitter CLK CLK FBIN FBIN t(Ø)n + 1 t(Ø)n ∑ t(Ø) n=N 1 t(Ø)n = N Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT tsk(o) Output Skew 8 (N is a large number of samples) IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUIT AND SWITCHING WAVEFORMS Yx, FBOUT Yx, FBOUT tcycle n Yx, FBOUT Yx, FBOUT 1 fo tjit(per) = tcycle n 1 fo NOTE: fo = Average input frequency measured at CLK / CLK Period jitter Yx, FBOUT Yx, FBOUT thalf period n+1 thalf period n Yx, FBOUT Yx, FBOUT 1 fo tjit(hper) = thalf period n NOTE: fo = Average input frequency measured at CLK / CLK Half-Period jitter 9 1 2*f o IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUIT AND SWITCHING WAVEFORMS 50% VDDQ OE tEN Y 50% VDDQ Y/Y Y OE 50% VDDQ tDIS Y 50% VDDQ Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y) CLK CLK FBIN FBIN t(Ø) t(Ø) t(Ø)DYN SSC OFF SSC OFF SSC ON SSC ON t(Ø)DYN t(Ø)DYN Dynamic Phase Offset 10 t(Ø)DYN IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUIT AND SWITCHING WAVEFORMS 80% Clock Inputs and Outputs, OE 80% VID, VOD 20% 20% tSLR(I/O) = tF(I), tF(O) tR(I), tR(O) V80% V20% tSLF(I/O) = tR(I/O) V80% V20% tF(I/O) Input and Output Slew Rates VIA CARD 1Ω BEAD 0603 AVDD VDDQ VDDQ 4.7uF 1206 0.1uF 0603 2200pF 0603 1 10 CSPU877A GND AGND VIA CARD GND NOTES: Place all decoupling capacitors as close to the CSPU877A pins as possible. Use wide traces for AVDD and AGND. Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz). Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ) APPLICATION INFORMATION Clock Loading on the PLL outputs (pF) Clock Structure # of SDRAM Loads per Clock Min. Max. #1 2 3 5 #2 4 6 10 11 0.1uF 0603 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE APPLICATION INFORMATION ~0.6" (split to terminator) ~2.5" SDRAM CSPU877A Z = 60Ω CLK C = 10pF R = 120Ω R = 120Ω Z = 60Ω CLK FBIN C = 10pF 8 more SDRAM ~0.3" R = 120Ω FBIN Feedback path Clock Structure 1 ~2.5" ~0.6" (split to terminator) SDRAM Stacked SDRAM CSPU877A Z = 60Ω CLK C = 10pF R = 120Ω R = 120Ω Z = 60Ω CLK FBIN C = 10pF SDRAM 8 more ~0.3" R = 120Ω FBIN Feedback path Clock Structure 2 12 SDRAM Stacked IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDTCSPU XXXXX Device Type X XX Package Process CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Blank 0°C to +70°C (Commercial) BV BVG NL NLG Very Fine Pitch Ball Grid Array Very Fine Pitch Ball Grid Array. Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package VFQFPN - Green 877A 1.8V PLL Differential 1:10 SDRAM Clock Driver for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 13 for Tech Support: [email protected] (408) 654-6459