PI74AVC+16721 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 2.5V 20-Bit Flip-Flop with 3-State Outputs Product Description Product Features • PI74AVC+16721 is designed for low voltage operation, Pericom Semiconductor’s PI74AVC+ series of logic circuits are produced using the Company’s advanced submicron CMOS technology, achieving industry leading speed. The PI74AVC+16721 is a 20-bit flip-flop with 3-state outputs designed specifically for 1.65V to 3.6V VCC operation. The device is designed with edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of clock (CLK) input, the device provides true data at the Q outputs, provided that the clock-enable (CLKEN) input is LOW. If CLKEN is HIGH, no data is stored. VCC = 1.65V to 3.6V • True ±24mA Balanced Drive @ 3.3V • IOFF supports partial power-down operation • 3.6V I/O Tolerant inputs and outputs • All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. • Industrial operation at –40°C to +85°C • Available Packages: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 173 mil wide plastic TVSOP (TSSOP) (K) A buffered output-enable (OE) input can be used to place the 20 outputs in either a normal logic state (HIGH or LOW level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the highimpedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Logic Block Diagram 1 56 29 2 55 1 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name De s cription Inputs Outputs OE Output Enable Input (Active LOW) OE CLKEN CLK Dx Qx CLKEN Clock Enable Input (Active LOW) L H X X Q0 Clock Input (Active HIGH) L L – H H Dx Data Inputs L L – L L Qx 3- State Outputs L L L or H X Q0 GND Ground H X X X Z VCC Power CLK Notes: 1. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance ↑ = LOW-to-HIGH Transition Product Pin Configuration OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 43 56-Pin 15 A,V 42 16 41 17 40 18 39 19 38 20 37 21 22 36 35 23 24 25 26 34 27 28 30 29 33 32 31 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN 2 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings above which the useful life may be impaired. (For user guidelines, not tested.) Supply voltage range, VCC ............................................................................. –0.5V to +4.6V Input voltage range, VI .................................................................................... –0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ............................................... –0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ......................................................................... –0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ................................................................ –50mA Output clamp current, IOK (VO <0) ........................................................... –50mA Continuous output current, IO ...................................................................................... ±50mA Continuous current through each VCC or GND ...................................... ±100mA Package thermal impedance, θ JA(3): package A ..................................... 64°C/W package K ............................................ 48°C/W Storage Temperature range, Tstg ...................................................................................... –65°C to 150°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Conditions(1) VC C Supply Voltage M in. M ax. Units Operating 1.65 3.6 V Data retention only 1.2 VC C = 1.2V VIH High- level Input Voltage VCC VC C = 1.65V to 1.95V VC C = 2.3V to 2.7V VC C = 3V to 3.6V 0.65 x VC C 1.7 2 VC C = 1.2V VIL Low- level Input Voltage VI Input Voltage VO Output Voltage IO H High- level output current IO L Low- level output current ∆t∆v Input transition rise or fall rate TA Gnd 0.35 x VC C VC C = 1.65V to 1.95V VC C = 2.3V to 2.7V 0.7 VC C = 3V to 3.6V 0.8 0 3.6 Active State 0 VC C 3- State 0 3.6 VC C = 1.65V to 1.95V –6 VC C = 2.3V to 2.7V – 12 VC C = 3V to 3.6V – 24 mA VC C = 1.65V to 1.95V 6 VC C = 2.3V to 2.7V 12 VC C = 3V to 3.6V 24 VC C = 1.65V to 3.6V 5 ns/V 85 °C Operating free- air temperature –40 Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation. 3 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics over the Operating Range (TA = –40°C +85°C) Parame te rs VO H VO L II IO F F IO Z IC C Control Inputs Te s t Conditions (1) IO H = –100µA VIH = 1.07V IO H = –6mA VIH = 1.7V IO H = –12mA VIH = 2V IO H = –24mA IO L = 100µA VIH = 0.57V IO L = 6mA VIH = 0.7V IO L = 12mA VIH = 0.8V IO L = 24mA VI = VC C or GND VI or VO = 3.6V VI = VC C or GND VO = VC C or GND IO = 0 Control Inputs VI = VC C or GND CI Data Inputs CO Outputs VO = VC C or GND VCC M in. 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V VC C –0.2V 1. 2 1.75 2.0 Typ. M ax. 0.2 0.45 0.55 0.8 ±2.5 ±10 ±10 40 4 4 6 6 8 8 Units V µA pF Note: Typical values are measured at TA = 25°C. 4 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) VCC = 1.5V ±0.1V VCC = 1.2 V M in. M ax. M in. M ax. VCC = 1.8V ±0.15V M in. M ax. fclock Clock Frequency th Hold time M in. M ax. 150 tw Pulse duration, CLK high or low tsu Setup time VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V M in. 180 3.0 3.0 Data before CLK↑ 5.7 3.5 2.4 CLKEN before CLK↑ 2.2 2.0 1.6 0 0 0 1. 2 1. 0 1.0 Data after CLK↑ CLKEN after CLK↑ M a x. 18 0 6.0 Units MHz ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted, see Figures 1 thru 4) Parame te rs fmax tpd ten tdis From (Input) To (Output) CLK OE OE VCC = 1.2V M in. M ax. VCC = 1.5V ±0.1V M in. M ax. Q Q Q VCC = 1.8V ±0.15V M in. M a x. 150 4.3 5.8 4.8 VCC = 2.5V ±0.2V M in. M ax. 180 3.0 4.8 3.6 VCC = 3.3V ±0.3V M in. M ax. 180 2.6 4.0 3.4 Vcc = 1.8V ±0.15V Vcc = 2.5V ±0.2V Vcc = 3.3V ±0.3V Typical Typical Typical 65 80 100 40 50 75 Units MHz ns Operating Characteristics, TA= 25°C Parame te rs Cpd Power Dissipation Capacitance Te s t Conditions Outputs Enabled CL = 0pF, f = 10 MHz Outputs Disabled 5 Units pF PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V ±0.1V S1 2Ω From Output Under Test CL = 15pF 2xVCC Open GND 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V VOL tPHZ VCC/2 VOH –0.1V VOH 0V Voltage Waveforms Enable and Disable Times Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 6 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 1.8V ±0.15V S1 12ΩkΩ From Output Under Test CL = 30 15pF 2xVCC Open GND 2Ω 1 kΩ (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.15V VOL tPHZ VCC/2 VOH –0.1V 0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 7 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 2.5V ± 0.2V S1 500Ω 2Ω From Output Under Test CL =30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.15V VOL tPHZ VCC/2 VOH –0.15V VOH 0V Voltage Waveforms Enable and Disable Times Figure 3. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 8 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PARAMETER MEASUREMENT INFORMATION VCC = 3.3V ± 0.3V S1 500Ω 2Ω From Output Under Test CL = 30 15pF 2xVCC Open GND 500Ω 2Ω (See Note A) Te s t S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND Load Circuit VCC Timing Input VCC/2 tW 0V tsu VCC VCC/2 Input th 0V VCC Data Input VCC/2 VCC/2 Voltage Waveforms Pulse Duration 0V Voltage Waveforms Setup and Hold Times Output Control (Low Level Enabling) VCC Input VCC/2 VCC/2 tPLH tPHL VOH VCC /2 VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL Voltage Waveforms Propagation Delay Times VCC/2 0V tPZL Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH 0V Output VCC/2 tPLZ VCC VCC/2 VOL +0.1V 0.3V VOL tPHZ VCC/2 VOH –0.1V 0.3V VOH 0V Voltage Waveforms Enable and Disable Times Figure 4. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tR ≤2.0ns, tF ≤2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd 9 PS8483 03/07/01 PI74AVC+16721 2.5V 20-Bit Flip-Flop with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Diagram : 56-pin 240-mil, Wide Plastic TSSOP (A) 56 .236 6.0 .244 6.2 1 .547 13.9 .555 14.1 1.20 SEATING PLANE .047 Max. .004 0.09 .008 0.20 .0197 BSC 0.50 .007 .011 0.17 0.27 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 0.45 .018 0.75 .030 .002 .006 0.05 0.15 .319 BSC 8.1 Package Diagram : 56-pin 173-mil, Wide Plastic TVSOP (TSSOP) (K) 56 .169 .177 4.30 4.50 0.09 0.20 .0035 .008 1 .441 .449 .031 .041 0.80 1.05 11.20 11.40 0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .016 BSC 0.40 X.XX X.XX .005 .009 0.13 0.23 .002 .006 0.05 0.15 .047 1.20 Max. DENOTES DIMENSIONS IN MILLIMETERS Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 10 PS8483 03/07/01