ETC PI74ALVCH32501

PI74ALVCH32501
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36-Bit Universal Bus Transceiver
with 3-State Outputs
Product Features
Product Description
· PI74ALVCH32501 is designed for low voltage operation,
Vcc = 1.65 to 3.6V
· Bus Hold on data inputs eliminates the need for external
pullup resistors
· Industrial operation at –40ºC to 85ºC
· Packages available:
114 Ball, 16mm x 5.5mm x 1.4mm Low Profile
Fine Pitch Ball Grid Array,
LFBGA (NB114)
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 36-bit PI74ALVCH32501 universal bus transceiver is designed
for 1.65V to 3.6V VCC operation.
This device can be used as two 18-bit transceivers or one 36-bit
transceiver. Data flow in each direction is controlled by outputenable (OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is high. When LEAB
is low, the A-data is latched if CLKAB is held at a
high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is high, the outputs are active. When OEAB is low, the
outputs are in the high-impedance state.
Logic Block Diagram (Positive Logic), Two Sets
1OEAB B3
1CLKAB A4
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
and CLKBA. The output enables are complementary (OEAB is
active high and OEBA is active low).
1LEAB A3
To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pullup resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
1LEBA K3
1CLKBA J4
1OEBA J3
1A1 A2
C1
1D
1DC1
1D
C1
CLK
A5
1B1
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a logic level.
The PI74ALVCH32501 is characterized for operation from
–40°C to 85°C.
CLK
TO 17 OTHER CHANNELS
2OEAB L3
2CLKAB K5
2LEAB K2
2LEBA W3
2CLKBA V4
2OEBA V3
2A1 L2
C1
1D
1DC1
1D
C1
CLK
L5
2B1
CLK
TO 17 OTHER CHANNELS
1
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Product Pin Description
Pin Name
OE
LE
CLK
Ax
Bx
GND
V CC
Truth Table(1)†
Description
Output Enable Input (Active HIGH)
Latch Enable (Active HIGH)
Clock Input (Active HIGH)
Data I/O
Data I/O
Ground
Power
Inputs
Output
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
L or H
X
B0‡
Notes:
† A-to-B data flow is shown; B-toA flow is similar
but uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady state input
conditions were established, provided that CLKAB is
high before LEAB goes low.
NB PACKAGE
Top View
6
5
4
3
2
1
A B C D E F G H J K L MN P R T U V W
Terminal Assignments
6
1B2
1B4
1B6
1B8
1B10
1B12
1B14
1B15
1B17
NC
2B2
2B4
2B6
2B8
2B10
2B12
2B14
2B15
2B17
5
1B1
1B3
1B5
1B7
1B9
1B11
1B13
1B16
1B18
2CLK AB
2B1
2B3
2B5
2B7
2B9
2B11
2B13
2B16
2B18
4
1CLK AB
GND
GND
VCC
GND
GND
VCC
GND
1CLK BA
GND
GND
GND
VCC
GND
GND
VCC
GND
2CLK BA
GND
3
1LEAB
1O EAB
GND
VCC
GND
GND
VCC
GND
1O EBA
1LEBA
2O EAB
GND
VCC
GND
GND
VCC
GND
2O EBA
2LEBA
2
1A1
1A3
1A5
1A7
1A9
1A11
1A13
1A16
1A18
2LEAB
2A1
2A3
2A5
2A7
2A9
2A11
2A13
2A16
2A18
1
1A2
1A4
1A6
1A8
1A10
1A12
1A14
1A15
1A17
NC
2A2
2A4
2A6
2A8
2A10
2A12
2A14
2A15
2A17
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
2
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range,VCC ............................................................... –0.5V to 4.6V
Input Voltage Range, VI: Except I/O ports (1) .............................. –0.5V to 4.6V
I/O ports (1,2) ........................... –0.5V to VCC + 0.5V
Output Voltage Range, VO (1,2) ............................................ –0.5V to VCC +0.5V
Input Clamp Current, IIK (VI <0) ........................................................ –50mA
Output Clamp Current, IOK (VO <0) .................................................. –50mA
Continuous Output Current, IO ................................................................... ±50mA
Continuous Current through each VCC or GND ............................... ±100mA
Package Thermal Impedance, θJA(3) ............................................................ 39ºC/W
Storage Temperature Range, TSTG ............................................... –65ºC to 150ºC
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Note:
1. The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
Parame te rs
VCC
VIH
VIL
D e s cription
Te s t Conditions
Supply Voltage
HIGH Level Input Voltage
LO W Level Input Voltage
M in.
M ax.
1.65
3.6
VCC = 1.65V to 1.95V
0.65 x VCC
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2
VCC = 1.65V to 1.95V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VI
Input Voltage
0
VCC
VO
O utput Voltage
0
VCC
IOH
IOL
High- level O utput Current
Low- level O utput Current
VCC = 1.65V
–4
VCC = 2.3V
–12
VCC = 2.7V
–12
VCC = 3.0V
–24
VCC = 1.65V
4
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
Units
V
mA
∆t/∆v
Input Transition rise or fall time
0
10
ns/V
TA
O perating Free- Air Temperature
- 40
85
°C
Note:
1. Unused control inputs must be held at VCC or GND to ensure proper device operation.
3
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%)
Parame te rs
Te s t Conditions
IOH = –100µA
VOH
VOL
Typ.(1) M ax. Units
IOH = –4mA
1.65V
1.2
IOH = –6mA
2.3V
2.0
2.3V
1.7
2.7V
2.2
3.0V
2.4
IOH = –24mA
3.0V
2.0
IOL = 100µA
1.65V to 3.6V
0.2
IOL = 4mA
1.65V
0.45
IOL = 6mA
2.3V
0.4
2.3V
0.7
2.7V
0.4
3V
0.55
3.6V
±5
IOH = –12mA
IOL = 24mA
VI = VCC or GND
VI = 0.58V
VI = 0.7V
TBD
45
2.3V
VI = 1.7V
VI = 0.8V
–45
75
3V
VI = 2V
V
TBD
1.65V
VI = 1.07V
II (Hold)
M in.
1.65V to 3.6V VCC - 0.2
IOL = 12mA
II
VCC
µA
–75
VI = 0 to 3.6V(2)
3.6V
±500
IOZ(3)
VO = VCC or GND
3.6V
±10
ICC
VI = VCC or GND,
3.6V
20
∆ICC
One input at VCC –0.6V,
Other inputs at VCC or GND
3V to 3.6V
750
CI Control Inputs
VI = VCC or GND
CIO A or B ports VO = VCC or GND
IO = 0
3.3V
4
3.3V
8
pF
Notes:
1. All typical values are at VCC = 3.3V, TA = 25ºC.
2. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to
switch the input from one state to another.
3. For I/O ports, the IOZ includes the input leakage current.
4
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Timing Requirements over Operating Range, Figures 1,2,3
Conditions (1)
VCC = 1.8V ±0.15V VCC = 2.5V ±0.2V
VCC = 2.7V
VCC = 3.3V ±0.3V
Parame te rs
De s cription
fCLOCK
Clock frequency
tW, Pulse
Duration
LE high
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
2.2
2.1
1.7
1.9
1.6
1.5
Data before LE ↓, CLK low
1.3
1.1
1
Data after CLK ↑
0.6
0.6
0.7
Data after LE ↓ CLK high or low
1.4
1.7
1.4
tH Hold time
M ax.
M in.
M ax.
M in.
M ax.
150
Data before CLK ↑
tSU, Setup
time
M in.
Data before LE ↓, CLK high
CL = 50pF
RL = 500Ω
TBD
M in.
150
M ax.
150
Units
MHz
ns
Switching Characteristics Over Operating Range, Figures 1,2,3
Parame te rs
From
To
(Input) (Output)
Conditions
VCC = 1.8V ±0.15V
M in.
M ax.
VCC = 2.5V ±0.2V
M in.
M ax.
150
fMAX
VCC = 2.7V
M in.
M ax.
150
VCC = 3.3V ±0.V
M in.
M ax.
150
MHz
A or B
B or A
1.0
4.8
4.5
1.0
3.9
LE
A or B
1.1
5.7
5.3
1.3
4.6
CLK
A or B
1.2
6.1
5.6
1.4
4.9
tEN
OEAB
B
1.0
5.8
5.3
1.0
4.6
tDIS
OEAB
B
1.5
6.2
5.7
1.4
5.0
tEN
OEBA
A
1.3
6.3
6.0
1.1
5.0
tDIS
OEBA
A
1.3
5.3
4.6
1.3
4.2
tPD
CL = 50pF
RL = 500Ω
TBD
Units
ns
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 0, f = 10 MHz
5
VCC = 1.8V
Typ.
TBD
VCC = 2.5V VCC = 3.3V
Typ.
Typ.
44
54
6
6
Units
pF
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Parameter Measurement Information
VCC = 1.8V ±0.15V
Load Circuit
Te s t
S1
tpd
O pen
tPLZ/tPZL
2 x VCC
tPHZ/tPZH
O pen
2 x VCC
1kΩ
From Output
S1
Open
GND
Under Test
1kΩ
CL = 30pF
(See Note A)
Voltage Waveforms Setup and Holdtimes
Voltage Waveforms Pulse Duration
tw
VCC
Timing
VCC
VCC/2
Input
Input
0V
tsu
Input
th
Voltage Waveforms Enable and Disable Times
VCC/2
VCC/2
Output
Control
(Low-level
enabling)
0V
Voltage Waveforms Propagation Delay Times
tPLH
Output
0V
tPHL
VCC/2
Output
Waveform 1
S1 at 2xVcc
(see Note B)
VCC
VCC/2
VCC/2
Input
VCC/2
0V
VCC
Data
VCC/2
VCC/2
VOH
Output
Waveform 2
S1 at OPEN
(see note B)
VCC/2
tPZL
VCC/2
tPLZ
VCC
0V
VCC/2
VCC
VOL+0.15V VOL
VCC/2
tPHZ
VOH-0.15V VOH
0V
tPZH
VOL
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2ns, tf ≤ 2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tten.
G. tPLH and tPHL are the same as tpd.
.
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PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Parameter Measurement Information
VCC = 2.5V ±0.2V
Load Circuit
2 x VCC
500Ω
From Output
S1
Under Test
500Ω
CL = 30pF
Te s t
S1
tpd
O pen
tPLZ/tPZL
2 x VCC
tPHZ/tPZH
GND
Open
GND
(See Note A)
Voltage Waveforms Setup and Hold Times
Voltage Waveforms Pulse Duration
tw
VCC
Timing
VCC
VCC/2
Input
Input
VCC/2
0V
VCC/2
0V
tsu
th
VCC
Data
VCC/2
Input
Voltage Waveforms Enable and Disable Times
VCC/2
0V
VCC
Output
VCC/2
Control
(Low-level
enabling)
tPLH
OUTPUT
VCC
VCC/2
VCC/2
VCC/2
VCC/2
VOL +0.15V
VOL
(see Note B)
tPZH
0V
tPHL
tPLZ
VCC
Waveform 1
S1 at 2 x VCC
VCC/2
0V
tPZL
Output
Voltage Waveforms Propagation Delay Times
INPUT
VCC/2
tPHZ
Output
Waveform 2
S1 at GND
VOH
VCC/2
VOH -0.15V
VOH
0V
(see Note B)
VOL
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tr ≤ 2ns, tf ≤ 2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tten.
G. tPLH and tPHL are the same as tpd.
.
7
PS8405A
09/15/99
PI74ALVCH32501
36-Bit
Universal
Bus Transceiver
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Parameter Measurement Information
VCC = 2.7V and 3.3V ±0.3V
Load Circuit
6V
S1
500Ω
From Output
S1
tpd
O pen
tPLZ/tPZL
6V
tPHZ/tPZH
GND
GND
Under Test
500Ω
CL = 50pF
Te s t
Open
(See Note A)
Voltage Waveforms Setup and Hold Times
Voltage Waveforms Pulse Duration
2.7V
Timing
tw
1.5V
2.7V
Input
1.5V
Input
0V
1.5V
0V
tsu
th
2.7V
Data
1.5V
Input
Voltage Waveforms Enable and Disable Times
1.5V
0V
2.7V
Output
1.5V
Control
1.5V
(Low-level
enabling)
Voltage Waveforms Propagation Delay Times
3V
1.5V
S1 at 6V
1.5V
INPUT
tPLH
OUTPUT
tPHL
1.5V
1.5V
tPLZ
Output
Waveform 1
1.5V
0V
tPZL
2.7V
(see Note B)
0V
Output
tPZH
Waveform 2
S1 at GND
VOL +0.3V
tPHZ
1.5V
VOH
VOH -0.3V
0V
(see Note B)
VOH
VOL
VOL
Figure 3. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tten.
G. tPLH and tPHL are the same as tpd.
.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8405A
09/15/99