PI74ALVCH16344 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1-Bit to 4-Bit Address/Driver with 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • PI74ALVCH16344 is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Bus Hold retains last active bus state during 3-State, eliminating the need for external pullup resistors Industrial operation at 40°C to +85°C Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 300 mil wide plastic SSOP (V) The PI74ALVCH16344 is a 1-bit to 4-bit buffer/driver designed for 2.3V to 3.6V Vcc operation. The address/driver is designed for applications where four seperate memory locations must be addressed by a single address. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The PI74ALVCH16344 has “Bus Hold” which retains the data input’s last state whenever the data input goes to high-impedance preventing “floating” inputs and eliminating the need for pullup/ down resistors. Logic Block Diagram OE1 1 OE3 2 A1 34 B51 B11 8 A5 6 9 30 B21 41 A6 13 36 B14 A2 14 OE2 29 37 OE4 A4 48 B71 15 A7 20 B64 56 16 B31 A3 B61 42 B24 28 B54 43 B34 44 B74 23 B41 55 B81 21 A8 27 B44 49 51 1 B84 PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Product Pin Description Pin Name OE A B GND VCC Inputs Description 3-State Output Enable Inputs (Active LOW) Inputs 3-State Outputs Ground Power OE A Bn L H H L L L H H Z Notes: 1. H = High Signal Level L = Low Signal Level X = Don’t Care or Irrelevant Z = High Impedance Product Pin Configuration OE1 1 56 OE4 B11 2 55 B81 B12 3 54 B82 GND 4 53 GND B13 5 52 B83 B14 6 51 B84 VCC 7 50 VCC A1 8 49 A8 B21 9 48 B71 B22 10 47 B72 GND 11 46 GND B23 12 B24 13 A2 A3 45 B73 44 B74 14 43 A7 15 42 A6 B31 16 41 B61 56-Pin A,V Outputs B32 17 40 B62 GND 18 39 GND B33 19 38 B63 B34 20 37 B64 A4 21 36 A5 VCC 22 35 VCC B41 23 34 B51 B42 24 33 B52 GND 25 32 GND B43 26 31 B53 B44 27 30 B54 OE2 28 29 OE3 2 PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage Range,VCC ............................................................... 0.5V to 4.6V Input Voltage Range, VI: Except I/O ports (1) .............................. 0.5V to 4.6V I/O ports (1,2) ........................... 0.5V to VCC + 0.5V Output Voltage Range, VO (1,2) ............................................ 0.5V to VCC +0.5V Input Clamp Current, IIK (VI <0) ........................................................ 50mA Output Clamp Current, IOK (VO <0) .................................................. 50mA Continuous Output Current, IO ................................................................... ±50mA Continuous Current through each VCC or GND ............................... ±100mA Package Thermal Impedance, θJA(3) ............................................................ 39ºC/W Storage Temperature Range, TSTG ............................................... 65ºC to 150ºC Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Note: 1. The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. Recommended Operating Condition(1) Parame te rs VCC VIH VIL D e s cription Te s t Conditions Supply Voltage HIGH Level Input Voltage LO W Level Input Voltage M in. Typ. 1.65 VCC = 1.65V to 1.95V 0.65x VCC VCC = 2.3V to 2.7V 1.7 VCC = 2.7V to 3.6V 2 M ax. 3.6 VCC = 1.65V to 1.95V 0.35x VCC VCC = 2.3V to 2.7V 0.7 VCC = 2.7V to 3.6V 0.8 VI Input Voltage 0 VCC VO O utput Voltage 0 VCC IOH IOL High- level O utput Current Low- level O utput Current Units VCC = 1.65V 4 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 VCC = 1.65V 4 VCC = 2.3V 12 VCC = 2.7V 12 VCC = 3.0V 24 V mA ∆t/∆v Input Transition rise or fall time 0 10 ns/V TA O perating Free- Air Temperature - 40 85 °C Note: 1. Unused control inputs must be held at VCC or GND to ensure proper device operation. 3 PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ±10%) Parame te rs Te s t Conditions IOH = 100µA VOH VOL Typ.(1) M ax. Units IOH = 4mA 1.65V 1.2 IOH = 6mA 2.3V 2.0 2.3V 1.7 2.7V 2.2 3.0V 2.4 IOH = 24mA 3.0V 2.0 IOL = 100µA 1.65V to 3.6V 0.2 IOL = 4mA 1.65V 0.45 IOL = 6mA 2.3V 0.4 2.3V 0.7 2.7V 0.4 3V 0.55 3.6V ±5 IOH = 12mA IOL = 24mA VI = VCC or GND VI = 0.58V VI = 0.7V 25 45 2.3V VI = 1.7V VI = 0.8V 45 75 3V VI = 2V V 25 1.65V VI = 1.07V II (Hold) M in. 1.65V to 3.6V VCC 0.2 IOL = 12mA II VCC µA 75 VI = 0 to 3.6V(2) 3.6V ±500 IOZ(3) VO = VCC or GND 3.6V ±10 ICC VI = VCC or GND 3.6V 20 ∆ICC One input at VCC 0.6V, Other inputs at VCC or GND 3V to 3.6V 750 CI Control Inputs VI = VCC or GND CIO A or B ports VO = VCC or GND IO = 0 3.3V 4 3.3V 8 pF Notes: 1. All typical values are at VCC = 3.3V, TA = 25ºC. 2. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 3. For I/O ports, the IOZ includes the input leakage current. 4 PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics over Operating Range(1) Parame te rs VCC = 2.5V ± 0.2V From To (INPUT) (OUTPUT) M in.(2) M ax. VCC = 2.7V M in.(2) VCC = 3.3V ± 0.3V M ax. M in.(2) M ax. tPD A B 1.0 5.0 4.0 1.0 3.6 tEN OE B 1.0 6.8 6.0 1.0 5.0 tDIS OE B 1.0 6.0 5.2 1.0 5.0 - 0.35 - 0.5 tsk(0)(3) tsk(0)(4) Units ns Notes: 1. See test circuit and waveforms, Figures 1 and 2. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between outputs of same bank, and same device and same transition. This parameter is warranted but not production tested. 4. Skew between outputs of all banks, and same device, A1-A8 tied together. This parameter is warranted but not production tested. Operating Characteristics, TA = 25ºC Parame te r Te s t Conditions VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Units Typical CPD Power Dissipation O utputs Enabled Capacitance O utputs Disabled CL = 50pF, f = 10 MHz 5 68 84 11 14 pF PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Parameter Measurement Information VCC = 2.5V ±0.2V Load Circuit 2 x VCC 500Ω From Output S1 Under Test 500Ω CL = 30pF Te s t S1 tpd O pen tPLZ/tPZL 2 x VCC tPHZ/tPZH GND Open GND (See Note A) Voltage Waveforms Setup and Hold Times Voltage Waveforms Pulse Duration tw VCC Timing VCC VCC/2 Input Input VCC/2 0V VCC/2 0V tsu th VCC Data VCC/2 Input Voltage Waveforms Enable and Disable Times VCC/2 0V VCC Output VCC/2 Control (Low-level enabling) VCC/2 tPLH OUTPUT VCC/2 VCC/2 VCC/2 S1 at 2 x VCC (see Note B) tPZH 0V tPHL tPLZ VCC Waveform 1 VCC VCC/2 0V tPZL Output Voltage Waveforms Propagation Delay Times INPUT VCC/2 S1 at GND VOH VOL tPHZ Output Waveform 2 VOL +0.15V VCC/2 VOH -0.15V VOH 0V (see Note B) VOL Figure 1. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50Ω, tr ≤ 2ns, tf ≤ 2ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tten. G. tPLH and tPHL are the same as tpd. . 6 PS8166B 10/19/99 PI74ALVCH16344 1-Bit to 4-Bit Address Driver with 3-State Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Parameter Measurement Information VCC = 2.7V and 3.3V ±0.3V Load Circuit 6V S1 500Ω From Output S1 tpd O pen tPLZ/tPZL 6V tPHZ/tPZH GND GND Under Test 500Ω CL = 50pF Te s t Open (See Note A) Voltage Waveforms Setup and Hold Times Voltage Waveforms Pulse Duration 2.7V Timing tw 1.5V 2.7V Input 1.5V Input 0V 1.5V 0V tsu th 2.7V Data 1.5V Input Voltage Waveforms Enable and Disable Times 1.5V 0V 2.7V Output 1.5V Control 1.5V (Low-level enabling) Voltage Waveforms Propagation Delay Times 3V 1.5V S1 at 6V 1.5V INPUT tPLH OUTPUT tPHL 1.5V 1.5V tPLZ Output Waveform 1 1.5V 0V tPZL 2.7V (see Note B) 0V Output tPZH Waveform 2 S1 at GND VOL +0.3V tPHZ 1.5V VOH VOH -0.3V 0V (see Note B) VOH VOL VOL Figure 2. Load Circuit and Voltage Waveforms Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tten. G. tPLH and tPHL are the same as tpd. . Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS8166B 10/19/99