ETC PI74AVC16835A

PI74AVC16835
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18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
Product Description
• Very high-speed, low-noise universal bus driver with
embedded resistor outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and
heavy-load applications
• Fast Propagation Delay:
2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Pericom Semiconductor’s PI74AVC series of logic circuits
are produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74AVC16835 universal bus driver is designed for 1.8V
to 3.6V Vcc operation.
Data flow from A to Y is controlled by Output Enable (OE). The device
operates in the transparent mode when LE is HIGH. The A data is
latched if CLK is held at a high or low logic level. If LE is LOW, the
A-bus is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16835 bus driver is designed to drive an array of 133
MHz synchronous memory chips, with minimal undershoot/
overshoot noise, and to meet the input signal rise/fall time requirement
of memory chips.
The output drivers of this part have an embedded series-resistor. For
DIMM module design, no external series termination resistors near
the buffer drivers or any other termination resistors are required. This
feature simplifies DIMM module layout design, and results in cost
savings.
Product Pin Configuration
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
2
56
55
GND
3
4
5
54
53
52
A1
6
7
8
51
50
49
A3
9
10
48
47
A5
11
12
13 56-Pin
46
45
44
GND
14
15
16
43
42
41
A9
17
18
40
39
A12
19
20
21
38
37
36
A13
22
23
24
35
34
33
VCC
25
26
32
31
GND
27
28
30
29
CLK
A, K
NC
GND
A2
VCC
A4
A6
A7
A8
A10
A11
GND
A14
A15
A16
A17
A18
GND
1
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Truth Table(1)
Logic Block Diagram
Inputs
OE
CLK
27
30
28
LE
A1
54
1D
C1
3
Y1
LE
CLK
A
Outputs Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
Yo(2)
L
L
L
X
Yo(3)
Note:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑ = Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established, provided that CLK is HIGH
before LE goes LOW.
3. Output level before the indicated steady-state input
conditions were established.
CLK
TO 17 OTHER CHANNELS
Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
VCC
OE
Description
Output Enable Input (Active LOW)
Latch Enable
Clock Input
Data Input
Data Output
Ground
Power
2
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................................................................. –65°C to +150°C
Ambient Temperature with Power Applied ............................................................................ –40°C to +85°C
Supply Voltage Range, VCC ............................................................................................................................................................................... –0.5V to +4.6V
Input Voltage Range, VI(1) .................................................................................................................................................................................... –0.5V to +4.6V
Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........... –0.5V to +4.6V
Voltage range applied to any output in the high or low state, VO(1,2) ............................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................................................................................. –50mA
Output clamp current, IOK (VO <0) ........................................................................................................ –50mA
Continuous output current, IO ................................................................................................................ ±50mA
Continuous current through each VCC or GND .................................................................................... ±100mA
Package thermal impedance, θJA(3): A (TSSOP) package .................................................................... 81°C/W
K (TVSOP) package .................................................................... 86°C/W
Note:
1. Input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.
2. Output positive voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed.
3. Package thermal impedance is calculated in accordance with JESD 51.
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
3
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Recommended Operating Conditions(1)
Parame te rs
VCC
VIH
D e s cription
Supply Voltage
High- level Input Voltage
Te s t Conditions
M in.
M ax.
O perating
1.65
3.6
Data Retention O nly
1.2
VCC = 1.2V
VCC
VCC = 1.65V to 1.95V
0.65 x VCC
VCC = 2.3V to 2.7V
VCC = 3V to 3.6V
1.7
2
VCC = 1.2V
VIL
Low- level Input Voltage
VIN
Input Voltage
VOUT
O utput Voltage
IOHS
IOLS
∆t/∆v
TA
High- level O utput Current (2)
Low- level O utput Current (2)
Input transition rise or fall rate
Units
GND
VCC = 1.65V to 1.95V
V
0.35 x VCC
VCC = 2.3V to 2.7V
0.7
VCC = 3V to 3.6V
0.8
0
3.6
Active State
0
VCC
3- State
0
3.6
VCC = 1.65V to 1.95V
-4
VCC = 2.3V to 2.7V
-8
VCC = 3V to 3.6V
- 12
mA
VCC = 1.65V to 1.95V
4
VCC = 2.3V to 2.7V
8
VCC = 3V to 3.6V
12
VCC = 1.65V to 3.6V
5
ns/V
85
°C
O perating Free- Air Temperature
- 40
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Dynamic drive is greater than standard output drive of IOH = –24mA and IOL = 24mA
4
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ± 10%)
Parame te rs
VOH
VOL
II
Control Inputs
Te s t Conditions
1.65 to 3.6
VCC - 0.2
M ax. Units
IOHS = –4mA
VIH = 1.07V
1.65
1.2
IOHS = –8mA
VIH = 1.7V
2.3
1.75
IOHS = –12mA
VIH = 2V
3.0
2.3
IOLS = 100µA
VIH or VIL
1.65 to 3.6
0.2
IOLS = 4mA
VIL = 0.57V
1.65
0.45
IOLS = 8mA
VIL = 0.7V
2.3
0.55
IOLS = 12mA
VIL = 0.8V
3.0
0.7
3.6
2.5
0
±10
3.6
±10
3.6
40
VI = VCC or GND
IOZ(3)
VO = VCC or GND
ICC
VI = VCC or GND
OE = VCC
IO = 0
Control Inputs
VI = VCC or GND
Data Input
Outputs
Typ.(2)
VIH or VIL
VI = 0 or 3.6V
CO
M in.
IOHS = –100µA
IOFF
CI
VCC(1)
VO = VCC or GND
2.5
4.5
3.3
4.5
2.5
4.0
3.3
4.0
2.5
6.5
3.3
6.5
V
µA
pF
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are measured at +25°C.
3. For I/O ports, the IOZ includes the input leakage current.
Timing Requirements over Operating Range
Parame te rs
De s cription
VCC = 1.8 V
± 0.15V
M in.
M ax.
VCC = 2.5V
± 0.2V
M in.
M in.
fCLOCK
Clock Frequency
tW Pulse
Duration
LE High
2.0
1.2
1.0
CLK High or Low
2.0
1.2
1.0
Data before CLK↑
1.4
1.2
1.0
Data before LE↓, CLK High or Low
1.4
1.2
1.0
Data after CLK↑
1.0
0.8
0.6
Data after LE↓, CLK High or Low
1.0
0.8
0.6
tSU Setup time
tH Hold time
150
M ax.
VCC = 3.3V
± 0.3V
5
150
Units
M ax.
150
MHz
ns
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Switching Characteristics Over Recommended Operating Free-Air Temperature Range
Unless otherwise noted, see Figures 3 through 5.
Parame te r
From
(Input)
To
(Output)
fmax
tpd
VCC = 1.8V
±0.15V
M in.
VCC = 2.5V
±0.2V
M ax.
M in.
150
M ax.
150
VCC = 3.3V(1)
±0.3V
M in.
M ax.
150
MHz
A
1.0
4.5
0.8
3.0
0.7
2.4
LE
1.0
5.0
0.8
3.3
0.7
2.5
1.0
4.5
0.8
3.0
0.7
2.5
CLK
Y
Units
ten
OE
1.5
5.5
1.0
4.5
1.0
4.0
tDIS
OE
1.5
5.0
1.0
4.5
1.0
4.0
ns
Note 1. Load at 50pF and 500Ω.
Operating Characteristics, TA = 25°C
Parame te rs
Cpd Power dissipation
capacitance
O utputs Enabled
O utputs Disabled
Te s t
Conditions
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
Typ.
Typ.
Typ.
CL = 0,
f = 10 MHz
45
48
52
23
25
28
6
Units
pF
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Parameter Measurement Information (VCC = 1.8V ±0.15V)
From Output
Under Test
TEST
2 x VCC
R1
500Ω
Open
GND
tpd
tPLZ/tPZL
tPHZ/tPZH
1kΩ
CL=30pF
S1
Ope n
2 x VCC
GND
(See Note A)
Load Circuit
tW
VCC
Timing
Input
VCC/2
VCC
0V
tsu
Input
VCC/2
0V
Voltage Waveforms
Pulse Duration
VCC/2
0V
(Low-level
enabling)
Vcc/2
0V
tPLH
(see Note B)
tPLH
tPZL
Vcc/2
VCC/2
tPLZ
tPZH
VOL +0.15V
VOL
tPHZ
VCC/2
VOH
VOH –0.15V
(see Note B)
VOL
Voltage Waveforms
Propagation Delay Times
0V
VCC
VCC/2
Output
Waveform 2
S1 at GND
VOH
Vcc/2
VCC/2
Output
Waveform 1
S1 at 2 x VSS
VCC
Vcc/2
VCC
Output
Control
Voltage Waveforms
Setup and Hold Times
Input
VCC/2
th
VCC
Data
Input
Output
VCC/2
0V
Voltage Waveforms
Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tdis.
G. tPLH and tPHL are the same as tdis.
Figure 3. Load Circuit and Voltage Waveforms
7
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Parameter Measurement Information (VCC = 2.5V ±0.2V)
500Ω
From Output
Under Test
2 x VCC
Open
GND
S1
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
500Ω
CL=30pF
S1
(See Note A)
Ope n
2 x VCC
GND
Load Circuit
tW
VCC
Timing
Input
VCC
VCC/2
Input
0V
tsu
VCC/2
Voltage Waveforms
Pulse Duration
VCC/2
0V
Voltage Waveforms
Setup and Hold Times
(Low-level
enabling)
0V
tPLH
(see Note B)
tPLH
tPZL
Vcc/2
VOL
VCC/2
tPLZ
tPZH
VOL +0.15V
VOL
tPHZ
VCC/2
VOH
VOH –0.15V
0V
(see Note B)
Voltage Waveforms
Propagation Delay Times
0V
VCC
VCC/2
Output
Waveform 2
S1 at GND
VOH
Vcc/2
VCC/2
Output
Waveform 1
S1 at 2 x VSS
Vcc/2
Vcc/2
VCC
Output
Control
VCC
Input
Output
VCC/2
0V
th
VCC
Data
Input
VCC/2
Voltage Waveforms
Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tdis.
G. tPLH and tPHL are the same as tdis.
Figure 4. Load Circuit and Voltage Waveforms
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
8
PS8373D
08/03/99
PI74AVC16835
18-Bit Universal Bus Driver
with 3-State Outputs
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Parameter Measurement Information (VCC = 3.3V ±0.3V)
500Ω
From Output
Under Test
S1
2 x VCC
Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
500Ω
CL=50pF
S1
(See Note A)
Ope n
2 x VCC
GND
Load Circuit
tW
VCC
Timing
Input
VCC
VCC/2
Input
VCC/2
0V
tsu
0V
th
Voltage Waveforms
Pulse Duration
VCC
Data
Input
VCC/2
VCC/2
0V
Voltage Waveforms
Setup and Hold Times
Input
(Low-level
enabling)
(see Note B)
0V
tPLH
tPLH
tPZL
Vcc/2
VOL
VCC/2
tPLZ
tPZH
VOL +0.3V
VOL
tPHZ
VCC/2
VOH
VOH –0.3V
0V
(see Note B)
Voltage Waveforms
Propagation Delay Times
0V
VCC
VCC/2
Output
Waveform 2
S1 at GND
VOH
Vcc/2
VCC/2
Output
Waveform 1
S1 at 2 x VSS
Vcc/2
Vcc/2
VCC
Output
Control
VCC
Output
VCC/2
Voltage Waveforms
Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as tdis.
G. tPLH and tPHL are the same as tdis.
Figure 5. Load Circuit and Voltage Waveforms
9
PS8373D
08/03/99