RF4E20N50S Data Sheet 20A, 500V, 0.240 Ohm, N-Channel Power MOSFETs May 2002 Features • 20A, 500V [ /Title These are N-Channel enhancement mode silicon gate • rDS(ON) = 0.240Ω (HUF75 power field effect transistors. They are advanced power • Single Pulse Avalanche Energy Rated 337G3, MOSFETs designed, tested, and guaranteed to withstand a • SOA is Power Dissipation Limited HUF753 specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for 37P3, • Nanosecond Switching Speeds applications such as switching regulators, switching HUF753 convertors, motor drivers, relay drivers, and drivers for high • Linear Transfer Characteristics 37S3, power bipolar switching transistors requiring high speed and • High Input Impedance HUF753 low gate drive power. These types can be operated directly • Related Literature 37S3S) from integrated circuits. - TB334 “Guidelines for Soldering Surface Mount Compo/Subject Formerly developmental type TA17465. nents to PC Boards” (62A, Ordering Information 55V, Symbol 0.014 PART NUMBER PACKAGE BRAND D Ohm, N- RF4E20N50S TO-268AA RF4E20N50S Channel NOTE: When ordering, use the entire part number. UltraFE G T Power S MOSFETs) /Author () /Keywords (Harris Packaging SemiJEDEC TO-268AA conductor, NDRAIN Channel (TAB) UltraFE T Power GATE MOSSOURCE FETs, TO-247, TO220AB, TO262AA, TO263AB) ©2002 Fairchild Semiconductor Corporation RF4E20N50S revA1 RF4 E2 0 N50 S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RF4E20N50S 500 500 20 12 80 ±20 250 2.0 960 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 500 - - V Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 10) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2 - 4 V VDS = Rated BVDSS, VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS,, VGS = 0V TJ = 125o - - 250 µA 20 - - A VGS = ±20V - - ±100 nA rDS(ON) ID = 11A, VGS = 10V, (Figures 8, 9) - - 0.240 Ω gfs VDS ≥ 50V, IDS > 11A, (Figure 12) 13 19 - S - 23 35 ns - 81 120 ns - 85 130 ns - 65 98 ns - 120 190 nC - 18 - nC - 62 - nC - 4100 - pF Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate-Drain) td(ON) tr td(OFF) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V VDD = 250V, ID = 20A, RGS = 4.3Ω, RD = 12.5Ω, VGS = 10V, (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature tf Qg(TOT) VGS = 10V, ID = 20A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figures 14, 19, 20) Gate Charge is Essentially Independent of OperatingTemperature Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 480 - pF Reverse Transfer Capacitance CRSS - 84 - pF VDS = 25V, VGS = 0V, f = 1MHz, (Figure 10) RF4 E2 0 N50 S Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS Internal Drain Inductance LD Measured from the Drain Lead, 6mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad MIN TYP MAX UNITS - 5.0 - nH - 13 - nH - - 0.50 oC/W - - 30 oC/W Modified MOSFET Symbol Showing the Internal Device Inductances D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA Free Air Operation Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier MIN TYP MAX UNITS - - 20 A - - 80 A - - 1.8 V 280 580 1200 ns 3.8 8.1 18 µC D G S Source to Drain Diode Voltage (Note 2) VSD TJ trr TJ QRR TJ Reverse Recovery Time Reverse Recovery Charge = 25oC, ISD = 20A, VGS = 0V, (Figure 13) = 25oC, ISD = 20A, dISD/dt = 100A/µs = 25oC, ISD = 20A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤300µs, duty cycle ≤2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 4.3mH, RGS = 25Ω, Peak IAS = 20A (Figures 15, 16). Typical Performance Curves 20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 16 12 8 4 0 0 50 100 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 150 25 50 75 100 125 TC, CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 150 RF4 E2 0 N50 S Typical Performance Curves (Continued) ZθJC, THERMAL IMPEDANCE (oC/W) 1 0.5 0.1 0.2 0.1 0.05 PDM 0.02 10-2 0.01 t1 t2 SINGLE PULSE 10-3 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (S) 1 10 FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 103 5 40 32 102 5 10µs 100µs 2 10 1ms 5 10ms 2 1 5 T = 25oC C T = MAX RATED 2 J SINGLE PULSE 0.1 1 2 5 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 2 DC VGS = 5.5V 24 16 VGS = 5.0V 8 VGS = 4.5V VGS = 4.0V 2 102 5 2 5 0 103 0 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 150 200 250 FIGURE 5. OUTPUT CHARACTERISTICS 102 40 80µs PULSE TEST VGS = 10V VDS ≥ 50V 80µs PULSE TEST VGS = 6.0V 32 ID, DRAIN CURRENT(A) ID, DRAIN CURRENT (A) 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA VGS = 5.5V 24 16 VGS = 5.0V 8 VGS = 4.5V VGS = 4.0V 4 8 12 16 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 10 TJ = 150oC 1 TJ = 25oC 0.1 10-2 0 0 80µs PULSE TEST VGS = 10V VGS = 6.0V OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 20 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 10 RF4 E2 0 N50 S Typical Performance Curves (Continued) 2.5 3.0 VGS = 10V, ID = 11A NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) 80µs PULSE TEST 2.0 VGS = 10V 1.5 1.0 0.5 0 VGS = 20V 1.8 1.2 0.6 0 0 20 40 60 ID, DRAIN CURRENT (A) 80 -40 100 40 80 C, CAPACITANCE (pF) 1.15 1.05 0.95 0.85 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 8000 CISS 6000 COSS 4000 -40 0 40 80 120 0 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 2 5 10 2 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) 32 TJ = 25oC 24 16 TJ = 150oC 8 5 2 10 16 24 ID, DRAIN CURRENT (A) 32 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 40 TJ = 150oC 5 2 TJ = 25oC 1 5 2 0.1 8 1 102 VDS ≥ 50V 80µs PULSE TEST 0 CRSS 2000 0.75 0 160 10000 ID = 250µA 40 120 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.25 gfs, TRANSCONDUCTANCE (S) 0 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 2.4 0 0.4 0.8 1.2 1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 2.0 RF4 E2 0 N50 S Typical Performance Curves (Continued) VGS, GATE TO SOURCE (V) 20 ID = 20A VDS = 400V VDS = 250V 16 VDS = 100V 12 8 4 0 0 40 80 120 160 200 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS RF4 E2 0 N50 S Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT IG(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORM TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E2CMOSTM EnSignaTM FACT FACT Quiet Series FAST â FASTr FRFET GlobalOptoisolator GTO HiSeC I2C ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC â OPTOPLANAR PACMAN POP Power247 PowerTrench â QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER â UHC SMART START UltraFET â SPM VCX STAR*POWER Stealth SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic TruTranslation STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H5