INTERSIL IRFF420

IRFF420
Data Sheet
March 1999
1.6A, 500V, 3.000 Ohm, N-Channel
Power MOSFET
• 1.6A, 500V
Formerly developmental type TA17405.
Ordering Information
PACKAGE
1891.4
Features
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
PART NUMBER
File Number
• rDS(ON) = 3.000Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
BRAND
D
IRFF420
TO-205AF
IRFF420
NOTE: When ordering, include the entire part number.
G
S
Packaging
JEDEC TO-205AF
SOURCE
DRAIN
(CASE)
GATE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRFF420
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
IRFF420
500
500
1.6
6.5
±20
20
0.16
210
-55 to 150
UNITS
V
V
A
A
V
W
W/oC
mJ
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
SYMBOL
BVDSS
VGS = 0V, ID = 250µA (Figure 10)
500
-
-
V
Gate to Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
2.0
-
4.0
V
-
-
25
µA
Zero-Gate Voltage Drain Current
On-State Drain Current (Note 2)
IDSS
ID(ON)
Gate to Source Leakage
IGSS
Drain to Source On Resistance
(Note 2)
rDS(ON)
Forward Transconductance (Note 2)
Turn-On Delay Time
gfs
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Total Gate Charge
(Gate to Source + Gate to Drain)
Qg(TOT)
Gate to Source Charge
Qgs
Gate to Drain “Miller” Charge
Qgd
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
TEST CONDITIONS
VDS = Rated BVDSS, VGS = 0V
VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC
-
-
250
µA
VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7)
1.6
-
-
A
VGS = ±20V
-
-
±100
nA
VGS = 10V, ID = 1.0A (Figures 8, 9)
-
2.5
3.000
Ω
1.5
2.5
-
S
VDD = 0.5 x Rated BVDSS, RG = 9.1Ω, VGS = 10V,
ID ≈ 1.6A (Figures 17, 18), RL = 152Ω for VDSS = 250V,
RL = 137Ω for VDSS = 225V, MOSFET Switching
Times are Essentially Independent of Operating
Temperature
-
30
60
ns
-
25
50
ns
-
30
60
ns
-
15
30
ns
VGS = 10V, ID = 1.6A, VDS = 0.8 x Rated BVDSS,
IG(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is
Essentially Independent of Operating Temperature.
-
11
15
nC
-
5.0
-
nC
-
6.0
-
nC
-
300
-
pF
-
75
-
pF
-
20
-
pF
-
5.0
-
nH
-
15
-
nH
-
-
6.25
oC/W
-
-
175
oC/W
VDS ≥ 10V, ID = 2.0A (Figure 12)
VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11)
Internal Drain Inductance
LD
Measured from the Drain
Lead, 5mm (0.2in) from
Header to Center of Die
Internal Source Inductance
LS
Measured from the
Source Lead, 5mm (0.2in)
from Header and Source
Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
D
LD
G
LS
S
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
2
Free Air Operation
IRFF420
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Continuous Source to Drain Current
ISD
Pulse Source to Drain Current (Note 3)
ISM
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier
D
MIN
TYP
MAX
UNITS
-
-
1.6
A
-
-
6.5
A
G
S
Source to Drain Diode Voltage (Note 2)
VSD
TJ
trr
TJ
QRR
TJ
Reverse Recovery Time
Reverse Recovered Charge
= 25oC, ISD = 1.6A, VGS = 0V (Figure 13)
= 150oC, ISD = 1.6A, dISD/dt = 100A/µs
= 150oC, ISD = 1.6A, dISD/dt = 100A/µs
-
-
1.4
V
-
600
-
ns
-
3.5
-
µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, start TJ = 25oC, L = 143.5mH, RG = 25Ω, peak IAS = 1.6A (Figures 15,16).
Typical Performance Curves
2.0
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
0
0
50
100
1.6
1.2
0.8
0.4
0
25
150
50
TC , CASE TEMPERATURE (oC)
75
100
125
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
THERMAL IMPEDANCE
2
ZθJC, NORMALIZED
POWER DISSIPATION MULTIPLIER
1.2
1.0
0.5
0.2
PDM
0.1 0.1
t1
0.05
t2
0.02
0.01
0.01
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
10-4
10-3
10-2
0.1
t1, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
3
1
10
IRFF420
Typical Performance Curves
(Continued)
10
5
10µs
80µs PULSE TEST
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100µs
1ms
1.0
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
10ms
100ms
0.05
DC
TC = 25oC
TJ = MAX RATED
4
VGS = 7.5V
VGS = 6V
3
VGS = 5.5V
2
VGS = 5V
1
0
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
1000
0
VGS = 10V
80µs PULSE TEST
5
VGS = 7V
ID, DRAIN CURRENT (A)
VGS = 6.5V
4
VGS = 6V
3
VGS = 5.5V
2
VGS = 5V
1
VGS = 4V
100
150
200
250
FIGURE 5. OUTPUT CHARACTERISTICS
VGS = 4.5V
ID, ON-STATE DRAIN CURRENT (A)
5
50
VGS = 4.5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
VDS > ID(ON) x rDS(ON) MAX
80µs PULSE TEST
4
3
TJ = 125oC
2
TJ = -25oC
TJ = -55oC
1
0
0
0
4
8
12
16
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
20
FIGURE 6. SATURATION CHARACTERISTICS
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 7. TRANSFER CHARACTERISTICS
2.6
2µs PULSE TEST
VGS = 10V
TJ = 25oC
8
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
9
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (Ω)
VGS = 6.5V
VGS = 4V
0.01
1
VGS = 7V
VGS = 20V
7
6
5
4
3
2.2
1.8
1.4
1.0
0.6
0.2
2
0
2
4
6
8
10
ID, DRAIN CURRENT (A)
12
14
ID = 1A
VGS = 10V
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
160
IRFF420
Typical Performance Curves
(Continued)
1000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
ID = 250µA
1.15
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.25
1.05
0.95
0.85
800
600
400
CISS
200
COSS
CRSS
0.75
-40
0
40
80
0
160
120
10
20
30
40
VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
100
ISD, SOURCE TO DRAIN CURRENT (A)
80µs PULSE TEST
4
TJ = -50oC
3
TJ = 25oC
TJ = 125oC
2
1
80µs PULSE TEST
TJ = 25oC
TJ = 150oC
10
TJ = 150oC
TJ = 25oC
1
0
0
1
2
3
ID , DRAIN CURRENT (A)
4
0
5
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
VGS , GATE TO SOURCE VOLTAGE (V)
gfs, TRANSCONDUCTANCE (S)
5
50
1
3
2
VSD , SOURCE TO DRAIN VOLTAGE (V)
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 1.6A
VDS = 100V
VDS = 250V
VDS = 400V
15
10
5
0
0
4
8
12
16
20
Qg(TOT) , TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
4
IRFF420
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
-
VGS
VDS
IAS
VDD
VDD
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
RG
-
VDD
10%
10%
0
DUT
90%
VGS
VGS
0
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
0.2µF
50%
PULSE WIDTH
10%
FIGURE 17. SWITCHING TIME TEST CIRCUIT
12V
BATTERY
50%
VDD
Qg(TOT)
SAME TYPE
AS DUT
50kΩ
Qgd
0.3µF
VGS
Qgs
D
VDS
DUT
G
IG(REF)
0
S
0
IG CURRENT
SAMPLING
RESISTOR
VDS
ID CURRENT
SAMPLING
RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
6
IG(REF)
0
FIGURE 20. GATE CHARGE WAVEFORMS
IRFF420
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
7
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029